| #ifndef __MDP_REG_TDSHP_H__ |
| #define __MDP_REG_TDSHP_H__ |
| |
| #include "mmsys_reg_base.h" |
| |
| #define MDP_TDSHP_00 (0x000) |
| #define MDP_TDSHP_01 (0x004) |
| #define MDP_TDSHP_02 (0x008) |
| #define MDP_TDSHP_03 (0x00C) |
| #define MDP_TDSHP_05 (0x014) |
| #define MDP_TDSHP_06 (0x018) |
| #define MDP_TDSHP_07 (0x01C) |
| #define MDP_TDSHP_08 (0x020) |
| #define MDP_TDSHP_09 (0x024) |
| #define MDP_PBC_00 (0x040) |
| #define MDP_PBC_01 (0x044) |
| #define MDP_PBC_02 (0x048) |
| #define MDP_PBC_03 (0x04C) |
| #define MDP_PBC_04 (0x050) |
| #define MDP_PBC_05 (0x054) |
| #define MDP_PBC_06 (0x058) |
| #define MDP_PBC_07 (0x05C) |
| #define MDP_PBC_08 (0x060) |
| #define MDP_HIST_CFG_00 (0x064) |
| #define MDP_HIST_CFG_01 (0x068) |
| #define MDP_LUMA_HIST_00 (0x06C) |
| #define MDP_LUMA_HIST_01 (0x070) |
| #define MDP_LUMA_HIST_02 (0x074) |
| #define MDP_LUMA_HIST_03 (0x078) |
| #define MDP_LUMA_HIST_04 (0x07C) |
| #define MDP_LUMA_HIST_05 (0x080) |
| #define MDP_LUMA_HIST_06 (0x084) |
| #define MDP_LUMA_HIST_07 (0x08C) |
| #define MDP_LUMA_HIST_08 (0x090) |
| #define MDP_LUMA_HIST_09 (0x094) |
| #define MDP_LUMA_HIST_10 (0x098) |
| #define MDP_LUMA_HIST_11 (0x09C) |
| #define MDP_LUMA_HIST_12 (0x0A0) |
| #define MDP_LUMA_HIST_13 (0x0A4) |
| #define MDP_LUMA_HIST_14 (0x0A8) |
| #define MDP_LUMA_HIST_15 (0x0AC) |
| #define MDP_LUMA_HIST_16 (0x0B0) |
| #define MDP_LUMA_SUM (0x0B4) |
| #define MDP_Y_FTN_1_0_MAIN (0x0BC) |
| #define MDP_Y_FTN_3_2_MAIN (0x0C0) |
| #define MDP_Y_FTN_5_4_MAIN (0x0C4) |
| #define MDP_Y_FTN_7_6_MAIN (0x0C8) |
| #define MDP_Y_FTN_9_8_MAIN (0x0CC) |
| #define MDP_Y_FTN_11_10_MAIN (0x0D0) |
| #define MDP_Y_FTN_13_12_MAIN (0x0D4) |
| #define MDP_Y_FTN_15_14_MAIN (0x0D8) |
| #define MDP_Y_FTN_17_16_MAIN (0x0DC) |
| #define MDP_C_BOOST_MAIN (0x0E0) |
| #define MDP_C_BOOST_MAIN_2 (0x0E4) |
| #define MDP_TDSHP_C_BOOST_MAIN (0x0E8) |
| #define MDP_TDSHP_C_BOOST_MAIN_2 (0x0EC) |
| #define MDP_TDSHP_ATPG (0x0FC) |
| #define MDP_TDSHP_CTRL (0x100) |
| #define MDP_TDSHP_INTEN (0x104) |
| #define MDP_TDSHP_INTSTA (0x108) |
| #define MDP_TDSHP_STATUS (0x10C) |
| #define MDP_TDSHP_CFG (0x110) |
| #define MDP_TDSHP_INPUT_COUNT (0x114) |
| #define MDP_TDSHP_CHKSUM (0x118) |
| #define MDP_TDSHP_OUTPUT_COUNT (0x11C) |
| #define MDP_TDSHP_INPUT_SIZE (0x120) |
| #define MDP_TDSHP_OUTPUT_OFFSET (0x124) |
| #define MDP_TDSHP_OUTPUT_SIZE (0x128) |
| #define MDP_TDSHP_BLANK_WIDTH (0x12C) |
| #define MDP_TDSHP_DEMO_HMASK (0x130) |
| #define MDP_TDSHP_DEMO_VMASK (0x134) |
| #define MDP_TDSHP_DUMMY_REG (0x14C) |
| #define MDP_LUMA_HIST_INIT_00 (0x200) |
| #define MDP_LUMA_HIST_INIT_01 (0x204) |
| #define MDP_LUMA_HIST_INIT_02 (0x208) |
| #define MDP_LUMA_HIST_INIT_03 (0x20C) |
| #define MDP_LUMA_HIST_INIT_04 (0x210) |
| #define MDP_LUMA_HIST_INIT_05 (0x214) |
| #define MDP_LUMA_HIST_INIT_06 (0x218) |
| #define MDP_LUMA_HIST_INIT_07 (0x21C) |
| #define MDP_LUMA_HIST_INIT_08 (0x220) |
| #define MDP_LUMA_HIST_INIT_09 (0x224) |
| #define MDP_LUMA_HIST_INIT_10 (0x228) |
| #define MDP_LUMA_HIST_INIT_11 (0x22C) |
| #define MDP_LUMA_HIST_INIT_12 (0x230) |
| #define MDP_LUMA_HIST_INIT_13 (0x234) |
| #define MDP_LUMA_HIST_INIT_14 (0x238) |
| #define MDP_LUMA_HIST_INIT_15 (0x23C) |
| #define MDP_LUMA_HIST_INIT_16 (0x240) |
| #define MDP_LUMA_SUM_INIT (0x244) |
| #define MDP_DC_DBG_CFG_MAIN (0x250) |
| #define MDP_DC_WIN_X_MAIN (0x254) |
| #define MDP_DC_WIN_Y_MAIN (0x258) |
| #define MDP_DC_TWO_D_W1 (0x25C) |
| #define MDP_DC_TWO_D_W1_RESULT_INIT (0x260) |
| #define MDP_DC_TWO_D_W1_RESULT (0x264) |
| #define MDP_EDF_GAIN_00 (0x300) |
| #define MDP_EDF_GAIN_01 (0x304) |
| #define MDP_EDF_GAIN_02 (0x308) |
| #define MDP_EDF_GAIN_03 (0x30C) |
| #define MDP_EDF_GAIN_04 (0x310) |
| #define MDP_EDF_GAIN_05 (0x314) |
| #define MDP_TDSHP_10 (0x320) |
| #define MDP_TDSHP_11 (0x324) |
| #define MDP_TDSHP_12 (0x328) |
| #define MDP_TDSHP_13 (0x32C) |
| #define PAT1_GEN_SET (0x330) |
| #define PAT1_GEN_FRM_SIZE (0x334) |
| #define PAT1_GEN_COLOR0 (0x338) |
| #define PAT1_GEN_COLOR1 (0x33C) |
| #define PAT1_GEN_COLOR2 (0x340) |
| #define PAT1_GEN_POS (0x344) |
| #define PAT1_GEN_TILE_POS (0x354) |
| #define PAT1_GEN_TILE_OV (0x358) |
| #define PAT2_GEN_SET (0x360) |
| #define PAT2_GEN_COLOR0 (0x368) |
| #define PAT2_GEN_COLOR1 (0x36C) |
| #define PAT2_GEN_POS (0x374) |
| #define PAT2_GEN_CURSOR_RB0 (0x378) |
| #define PAT2_GEN_CURSOR_RB1 (0x37C) |
| #define PAT2_GEN_TILE_POS (0x384) |
| #define PAT2_GEN_TILE_OV (0x388) |
| #define MDP_BITPLUS_00 (0x38C) |
| #define MDP_BITPLUS_01 (0x390) |
| #define MDP_BITPLUS_02 (0x394) |
| #define MDP_DC_SKIN_RANGE0 (0x420) |
| #define MDP_CONTOUR_HIST_INIT_00 (0x398) |
| #define MDP_CONTOUR_HIST_INIT_01 (0x39C) |
| #define MDP_CONTOUR_HIST_INIT_02 (0x3A0) |
| #define MDP_CONTOUR_HIST_INIT_03 (0x3A4) |
| #define MDP_CONTOUR_HIST_INIT_04 (0x3A8) |
| #define MDP_CONTOUR_HIST_INIT_05 (0x3AC) |
| #define MDP_CONTOUR_HIST_INIT_06 (0x3B0) |
| #define MDP_CONTOUR_HIST_INIT_07 (0x3B4) |
| #define MDP_CONTOUR_HIST_INIT_08 (0x3B8) |
| #define MDP_CONTOUR_HIST_INIT_09 (0x3BC) |
| #define MDP_CONTOUR_HIST_INIT_10 (0x3C0) |
| #define MDP_CONTOUR_HIST_INIT_11 (0x3C4) |
| #define MDP_CONTOUR_HIST_INIT_12 (0x3C8) |
| #define MDP_CONTOUR_HIST_INIT_13 (0x3CC) |
| #define MDP_CONTOUR_HIST_INIT_14 (0x3D0) |
| #define MDP_CONTOUR_HIST_INIT_15 (0x3D4) |
| #define MDP_CONTOUR_HIST_INIT_16 (0x3D8) |
| #define MDP_CONTOUR_HIST_00 (0x3DC) |
| #define MDP_CONTOUR_HIST_01 (0x3E0) |
| #define MDP_CONTOUR_HIST_02 (0x3E4) |
| #define MDP_CONTOUR_HIST_03 (0x3E8) |
| #define MDP_CONTOUR_HIST_04 (0x3EC) |
| #define MDP_CONTOUR_HIST_05 (0x3F0) |
| #define MDP_CONTOUR_HIST_06 (0x3F4) |
| #define MDP_CONTOUR_HIST_07 (0x3F8) |
| #define MDP_CONTOUR_HIST_08 (0x3FC) |
| #define MDP_CONTOUR_HIST_09 (0x400) |
| #define MDP_CONTOUR_HIST_10 (0x404) |
| #define MDP_CONTOUR_HIST_11 (0x408) |
| #define MDP_CONTOUR_HIST_12 (0x40C) |
| #define MDP_CONTOUR_HIST_13 (0x410) |
| #define MDP_CONTOUR_HIST_14 (0x414) |
| #define MDP_CONTOUR_HIST_15 (0x418) |
| #define MDP_CONTOUR_HIST_16 (0x41C) |
| #define MDP_DC_SKIN_RANGE1 (0x424) |
| #define MDP_DC_SKIN_RANGE2 (0x428) |
| #define MDP_DC_SKIN_RANGE3 (0x42C) |
| #define MDP_DC_SKIN_RANGE4 (0x430) |
| #define MDP_DC_SKIN_RANGE5 (0x434) |
| #define MDP_POST_YLEV_00 (0x480) |
| #define MDP_POST_YLEV_01 (0x484) |
| #define MDP_POST_YLEV_02 (0x488) |
| #define MDP_POST_YLEV_03 (0x48C) |
| #define MDP_POST_YLEV_04 (0x490) |
| #define MDP_HFG_CTRL (0x500) |
| #define MDP_HFG_RAN_0 (0x504) |
| #define MDP_HFG_RAN_1 (0x508) |
| #define MDP_HFG_RAN_2 (0x50C) |
| #define MDP_HFG_RAN_3 (0x510) |
| #define MDP_HFG_RAN_4 (0x514) |
| #define MDP_HFG_CROP_X (0x518) |
| #define MDP_HFG_CROP_Y (0x51C) |
| #define MDP_HFC_CON_0 (0x524) |
| #define MDP_HFC_LUMA_0 (0x528) |
| #define MDP_HFC_LUMA_1 (0x52C) |
| #define MDP_HFC_LUMA_2 (0x530) |
| #define MDP_HFC_SL2_0 (0x534) |
| #define MDP_HFC_SL2_1 (0x538) |
| #define MDP_HFC_SL2_2 (0x53C) |
| #define MDP_SL2_CEN (0x544) |
| #define MDP_SL2_RR_CON0 (0x548) |
| #define MDP_SL2_RR_CON1 (0x54C) |
| #define MDP_SL2_GAIN (0x550) |
| #define MDP_SL2_RZ (0x554) |
| #define MDP_SL2_XOFF (0x558) |
| #define MDP_SL2_YOFF (0x55C) |
| #define MDP_SL2_SLP_CON0 (0x560) |
| #define MDP_SL2_SLP_CON1 (0x564) |
| #define MDP_SL2_SLP_CON2 (0x568) |
| #define MDP_SL2_SLP_CON3 (0x66C) |
| #define MDP_SL2_SIZE (0x670) |
| #define MDP_HFG_OUTPUT_COUNT (0x678) |
| |
| // MASK |
| #define MDP_TDSHP_00_MASK (0xF7FFFFFF) |
| #define MDP_TDSHP_01_MASK (0xFFFF0FFF) |
| #define MDP_TDSHP_02_MASK (0xFFFFFF00) |
| #define MDP_TDSHP_03_MASK (0x9FFF0F3F) |
| #define MDP_TDSHP_05_MASK (0xFFFFFFFF) |
| #define MDP_TDSHP_06_MASK (0xFFFFFFFF) |
| #define MDP_TDSHP_07_MASK (0xFFFFFFFF) |
| #define MDP_TDSHP_08_MASK (0xFFFFFFFF) |
| #define MDP_TDSHP_09_MASK (0xFF3F4000) |
| #define MDP_PBC_00_MASK (0xFFFFFFFF) |
| #define MDP_PBC_01_MASK (0xFFFFFFFF) |
| #define MDP_PBC_02_MASK (0xFFCF7F3F) |
| #define MDP_PBC_03_MASK (0xFFFFFFFF) |
| #define MDP_PBC_04_MASK (0xFFFFFFFF) |
| #define MDP_PBC_05_MASK (0xFFCF7F3F) |
| #define MDP_PBC_06_MASK (0xFFFFFFFF) |
| #define MDP_PBC_07_MASK (0xFFFFFFFF) |
| #define MDP_PBC_08_MASK (0xFFCF7F3F) |
| #define MDP_HIST_CFG_00_MASK (0xFFFFFFFF) |
| #define MDP_HIST_CFG_01_MASK (0xFFFFFFFF) |
| #define MDP_LUMA_HIST_00_MASK (0x07FFFFFF) |
| #define MDP_LUMA_HIST_01_MASK (0x07FFFFFF) |
| #define MDP_LUMA_HIST_02_MASK (0x07FFFFFF) |
| #define MDP_LUMA_HIST_03_MASK (0x07FFFFFF) |
| #define MDP_LUMA_HIST_04_MASK (0x07FFFFFF) |
| #define MDP_LUMA_HIST_05_MASK (0x07FFFFFF) |
| #define MDP_LUMA_HIST_06_MASK (0x07FFFFFF) |
| #define MDP_LUMA_HIST_07_MASK (0x07FFFFFF) |
| #define MDP_LUMA_HIST_08_MASK (0x07FFFFFF) |
| #define MDP_LUMA_HIST_09_MASK (0x07FFFFFF) |
| #define MDP_LUMA_HIST_10_MASK (0x07FFFFFF) |
| #define MDP_LUMA_HIST_11_MASK (0x07FFFFFF) |
| #define MDP_LUMA_HIST_12_MASK (0x07FFFFFF) |
| #define MDP_LUMA_HIST_13_MASK (0x07FFFFFF) |
| #define MDP_LUMA_HIST_14_MASK (0x07FFFFFF) |
| #define MDP_LUMA_HIST_15_MASK (0x07FFFFFF) |
| #define MDP_LUMA_HIST_16_MASK (0x07FFFFFF) |
| #define MDP_LUMA_SUM_MASK (0xFFFFFFFF) |
| #define MDP_Y_FTN_1_0_MAIN_MASK (0x01FF01FF) |
| #define MDP_Y_FTN_3_2_MAIN_MASK (0x01FF01FF) |
| #define MDP_Y_FTN_5_4_MAIN_MASK (0x01FF01FF) |
| #define MDP_Y_FTN_7_6_MAIN_MASK (0x01FF01FF) |
| #define MDP_Y_FTN_9_8_MAIN_MASK (0x01FF01FF) |
| #define MDP_Y_FTN_11_10_MAIN_MASK (0x01FF01FF) |
| #define MDP_Y_FTN_13_12_MAIN_MASK (0x01FF01FF) |
| #define MDP_Y_FTN_15_14_MAIN_MASK (0x01FF01FF) |
| #define MDP_Y_FTN_17_16_MAIN_MASK (0x03FF) |
| #define MDP_C_BOOST_MAIN_MASK (0xFFFF20FF) |
| #define MDP_C_BOOST_MAIN_2_MASK (0xFF03007F) |
| #define MDP_TDSHP_C_BOOST_MAIN_MASK (0xFFFF20FF) |
| #define MDP_TDSHP_C_BOOST_MAIN_2_MASK (0xFF03007F) |
| #define MDP_TDSHP_ATPG_MASK (0x03) |
| #define MDP_TDSHP_CTRL_MASK (0x07) |
| #define MDP_TDSHP_INTEN_MASK (0x07) |
| #define MDP_TDSHP_INTSTA_MASK (0x07) |
| #define MDP_TDSHP_STATUS_MASK (0x0F3) |
| #define MDP_TDSHP_CFG_MASK (0x03F7) |
| #define MDP_TDSHP_INPUT_COUNT_MASK (0x3FFF3FFF) |
| #define MDP_TDSHP_CHKSUM_MASK (0xB0FFFFFF) |
| #define MDP_TDSHP_OUTPUT_COUNT_MASK (0x3FFF3FFF) |
| #define MDP_TDSHP_INPUT_SIZE_MASK (0x3FFF3FFF) |
| #define MDP_TDSHP_OUTPUT_OFFSET_MASK (0x0FF00FF) |
| #define MDP_TDSHP_OUTPUT_SIZE_MASK (0x3FFF3FFF) |
| #define MDP_TDSHP_BLANK_WIDTH_MASK (0x0FFFFFF) |
| #define MDP_TDSHP_DEMO_HMASK_MASK (0x3FFF3FFF) |
| #define MDP_TDSHP_DEMO_VMASK_MASK (0x3FFF3FFF) |
| |
| #define MDP_LUMA_HIST_INIT_00_MASK (0x07FFFFFF) |
| #define MDP_LUMA_HIST_INIT_01_MASK (0x07FFFFFF) |
| #define MDP_LUMA_HIST_INIT_02_MASK (0x07FFFFFF) |
| #define MDP_LUMA_HIST_INIT_03_MASK (0x07FFFFFF) |
| #define MDP_LUMA_HIST_INIT_04_MASK (0x07FFFFFF) |
| #define MDP_LUMA_HIST_INIT_05_MASK (0x07FFFFFF) |
| #define MDP_LUMA_HIST_INIT_06_MASK (0x07FFFFFF) |
| #define MDP_LUMA_HIST_INIT_07_MASK (0x07FFFFFF) |
| #define MDP_LUMA_HIST_INIT_08_MASK (0x07FFFFFF) |
| #define MDP_LUMA_HIST_INIT_09_MASK (0x07FFFFFF) |
| #define MDP_LUMA_HIST_INIT_10_MASK (0x07FFFFFF) |
| #define MDP_LUMA_HIST_INIT_11_MASK (0x07FFFFFF) |
| #define MDP_LUMA_HIST_INIT_12_MASK (0x07FFFFFF) |
| #define MDP_LUMA_HIST_INIT_13_MASK (0x07FFFFFF) |
| #define MDP_LUMA_HIST_INIT_14_MASK (0x07FFFFFF) |
| #define MDP_LUMA_HIST_INIT_15_MASK (0x07FFFFFF) |
| #define MDP_LUMA_HIST_INIT_16_MASK (0x07FFFFFF) |
| #define MDP_LUMA_SUM_INIT_MASK (0xFFFFFFFF) |
| /*MT6755 New feature*/ |
| #define MDP_DC_DBG_CFG_MAIN_MASK (0x07) |
| #define MDP_DC_WIN_X_MAIN_MASK (0xFFFFFFFF) |
| #define MDP_DC_WIN_Y_MAIN_MASK (0xFFFFFFFF) |
| #define MDP_DC_TWO_D_W1_MASK (0xFFFFFFFF) |
| #define MDP_DC_TWO_D_W1_RESULT_INIT_MASK (0x007FFFFF) |
| #define MDP_DC_TWO_D_W1_RESULT_MASK (0x007FFFFF) |
| /*MT6797 New feature*/ |
| #define MDP_EDF_GAIN_00_MASK (0x9FFF1F07) |
| #define MDP_EDF_GAIN_01_MASK (0x7EFFFFFF) |
| #define MDP_EDF_GAIN_02_MASK (0x07071F1F) |
| #define MDP_EDF_GAIN_03_MASK (0x1F1F7F0F) |
| #define MDP_EDF_GAIN_04_MASK (0x3F1F1F00) |
| #define MDP_EDF_GAIN_05_MASK (0x00FFFFFF) |
| #define MDP_TDSHP_10_MASK (0xFFFF000F) |
| #define MDP_TDSHP_11_MASK (0xFFFFFFFF) |
| #define MDP_TDSHP_12_MASK (0xFFFF000F) |
| #define MDP_TDSHP_13_MASK (0xFFFFFFFF) |
| #define PAT1_GEN_SET_MASK (0x00FF00FD) |
| #define PAT1_GEN_FRM_SIZE_MASK (0x3FFF3FFF) |
| #define PAT1_GEN_COLOR0_MASK (0x03FF03FF) |
| #define PAT1_GEN_COLOR1_MASK (0x03FF03FF) |
| #define PAT1_GEN_COLOR2_MASK (0x03FF03FF) |
| #define PAT1_GEN_POS_MASK (0x3FFF3FFF) |
| #define PAT1_GEN_TILE_POS_MASK (0x3FFF3FFF) |
| #define PAT1_GEN_TILE_OV_MASK (0x0000FFFF) |
| #define PAT2_GEN_SET_MASK (0x00FF0003) |
| #define PAT2_GEN_COLOR0_MASK (0x03FF03FF) |
| #define PAT2_GEN_COLOR1_MASK (0x000003FF) |
| #define PAT2_GEN_POS_MASK (0x3FFF3FFF) |
| #define PAT2_GEN_CURSOR_RB0_MASK (0x03FF03FF) |
| #define PAT2_GEN_CURSOR_RB1_MASK (0x000003FF) |
| #define PAT2_GEN_TILE_POS_MASK (0x3FFF3FFF) |
| #define PAT2_GEN_TILE_OV_MASK (0x0000FFFF) |
| |
| #define MDP_BITPLUS_01_MASK (0x03FFFFFF) |
| #define MDP_BITPLUS_02_MASK (0x03FFFFFF) |
| #define MDP_DC_SKIN_RANGE0_MASK (0x003FFFFF) |
| |
| #define MDP_CONTOUR_HIST_INIT_00_MASK (0x07FFFFFF) |
| #define MDP_CONTOUR_HIST_INIT_01_MASK (0x07FFFFFF) |
| #define MDP_CONTOUR_HIST_INIT_02_MASK (0x07FFFFFF) |
| #define MDP_CONTOUR_HIST_INIT_03_MASK (0x07FFFFFF) |
| #define MDP_CONTOUR_HIST_INIT_04_MASK (0x07FFFFFF) |
| #define MDP_CONTOUR_HIST_INIT_05_MASK (0x07FFFFFF) |
| #define MDP_CONTOUR_HIST_INIT_06_MASK (0x07FFFFFF) |
| #define MDP_CONTOUR_HIST_INIT_07_MASK (0x07FFFFFF) |
| #define MDP_CONTOUR_HIST_INIT_08_MASK (0x07FFFFFF) |
| #define MDP_CONTOUR_HIST_INIT_09_MASK (0x07FFFFFF) |
| #define MDP_CONTOUR_HIST_INIT_10_MASK (0x07FFFFFF) |
| #define MDP_CONTOUR_HIST_INIT_11_MASK (0x07FFFFFF) |
| #define MDP_CONTOUR_HIST_INIT_12_MASK (0x07FFFFFF) |
| #define MDP_CONTOUR_HIST_INIT_13_MASK (0x07FFFFFF) |
| #define MDP_CONTOUR_HIST_INIT_14_MASK (0x07FFFFFF) |
| #define MDP_CONTOUR_HIST_INIT_15_MASK (0x07FFFFFF) |
| #define MDP_CONTOUR_HIST_INIT_16_MASK (0x07FFFFFF) |
| #define MDP_POST_YLEV_00_MASK (0xFFFFFFFF) |
| #define MDP_POST_YLEV_01_MASK (0xFFFFFFFF) |
| #define MDP_POST_YLEV_02_MASK (0xFFFFFFFF) |
| #define MDP_POST_YLEV_03_MASK (0xFFFFFFFF) |
| #define MDP_POST_YLEV_04_MASK (0xFF3F4000) |
| |
| #define MDP_HFG_CTRL_MASK (0x303) |
| #define MDP_HFG_RAN_0_MASK (0xFFFFFFFF) |
| #define MDP_HFG_RAN_1_MASK (0xFFFFFFFF) |
| #define MDP_HFG_RAN_2_MASK (0xFFFFFFFF) |
| #define MDP_HFG_RAN_3_MASK (0xFFFF) |
| #define MDP_HFG_RAN_4_MASK (0xFFFFFFFF) |
| #define MDP_HFG_CROP_X_MASK (0xFFFFFFFF) |
| #define MDP_HFG_CROP_Y_MASK (0xFFFFFFFF) |
| #define MDP_HFC_CON_0_MASK (0xFF) |
| #define MDP_HFC_LUMA_0_MASK (0xFFFFFF) |
| #define MDP_HFC_LUMA_1_MASK (0x3F3F3F3F) |
| #define MDP_HFC_LUMA_2_MASK (0x1F1F1F1F) |
| #define MDP_HFC_SL2_0_MASK (0x1FFFFFF) |
| #define MDP_HFC_SL2_1_MASK (0x3F3F3F3F) |
| #define MDP_HFC_SL2_2_MASK (0x1F1F1F1F) |
| #define MDP_SL2_CEN_MASK (0x1FFF1FFF) |
| #define MDP_SL2_RR_CON0_MASK (0x1FFF1FFF) |
| #define MDP_SL2_RR_CON1_MASK (0xFFFF3FFF) |
| #define MDP_SL2_GAIN_MASK (0x1FFFFFF) |
| #define MDP_SL2_RZ_MASK (0x3FFF3FFF) |
| #define MDP_SL2_XOFF_MASK (0xFFFFFFF) |
| #define MDP_SL2_YOFF_MASK (0xFFFFFFF) |
| #define MDP_SL2_SLP_CON0_MASK (0xFFFFFF) |
| #define MDP_SL2_SLP_CON1_MASK (0xFFFFFF) |
| #define MDP_SL2_SLP_CON2_MASK (0xFFFFFF) |
| #define MDP_SL2_SLP_CON3_MASK (0xFFFFFF) |
| #define MDP_SL2_SIZE_MASK (0x3FFF3FFF) |
| #define MDP_HFG_OUTPUT_COUNT_MASK (0x3FFF3FFF) |
| |
| #endif // __MDP_REG_TDSHP_H__ |
