| Catalin Marinas | 136848d | 2011-11-22 17:30:28 +0000 | [diff] [blame] | 1 | #ifndef __ARCH_ARM_FAULT_H |
| 2 | #define __ARCH_ARM_FAULT_H |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3 | |
| Catalin Marinas | 136848d | 2011-11-22 17:30:28 +0000 | [diff] [blame] | 4 | /* |
| 5 | * Fault status register encodings. We steal bit 31 for our own purposes. |
| 6 | */ |
| 7 | #define FSR_LNX_PF (1 << 31) |
| 8 | #define FSR_WRITE (1 << 11) |
| 9 | #define FSR_FS4 (1 << 10) |
| 10 | #define FSR_FS3_0 (15) |
| Catalin Marinas | f7b8156 | 2011-11-22 17:30:31 +0000 | [diff] [blame] | 11 | #define FSR_FS5_0 (0x3f) |
| Catalin Marinas | 136848d | 2011-11-22 17:30:28 +0000 | [diff] [blame] | 12 | |
| Catalin Marinas | f7b8156 | 2011-11-22 17:30:31 +0000 | [diff] [blame] | 13 | #ifdef CONFIG_ARM_LPAE |
| Alexander Sverdlin | 97a98ae | 2017-01-17 21:10:11 +0100 | [diff] [blame] | 14 | #define FSR_FS_AEA 17 |
| 15 | |
| Catalin Marinas | f7b8156 | 2011-11-22 17:30:31 +0000 | [diff] [blame] | 16 | static inline int fsr_fs(unsigned int fsr) |
| 17 | { |
| 18 | return fsr & FSR_FS5_0; |
| 19 | } |
| 20 | #else |
| Alexander Sverdlin | 97a98ae | 2017-01-17 21:10:11 +0100 | [diff] [blame] | 21 | #define FSR_FS_AEA 22 |
| 22 | |
| Catalin Marinas | 136848d | 2011-11-22 17:30:28 +0000 | [diff] [blame] | 23 | static inline int fsr_fs(unsigned int fsr) |
| 24 | { |
| 25 | return (fsr & FSR_FS3_0) | (fsr & FSR_FS4) >> 6; |
| 26 | } |
| Catalin Marinas | f7b8156 | 2011-11-22 17:30:31 +0000 | [diff] [blame] | 27 | #endif |
| Catalin Marinas | 136848d | 2011-11-22 17:30:28 +0000 | [diff] [blame] | 28 | |
| 29 | void do_bad_area(unsigned long addr, unsigned int fsr, struct pt_regs *regs); |
| Lucas Stach | 9254970 | 2015-10-19 13:38:09 +0100 | [diff] [blame] | 30 | void early_abt_enable(void); |
| Catalin Marinas | 136848d | 2011-11-22 17:30:28 +0000 | [diff] [blame] | 31 | |
| 32 | #endif /* __ARCH_ARM_FAULT_H */ |
