| /* SPDX-License-Identifier: MIT */ |
| /* |
| * Copyright 2023 Advanced Micro Devices, Inc. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included in |
| * all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| * OTHER DEALINGS IN THE SOFTWARE. |
| * |
| * Authors: AMD |
| * |
| */ |
| |
| #ifndef __DC_HUBBUB_DCN35_H__ |
| #define __DC_HUBBUB_DCN35_H__ |
| |
| #include "dcn32/dcn32_hubbub.h" |
| |
| #define HUBBUB_REG_LIST_DCN35(id)\ |
| SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\ |
| SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\ |
| SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\ |
| SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\ |
| SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\ |
| SR(DCHUBBUB_ARB_DRAM_STATE_CNTL),\ |
| SR(DCHUBBUB_ARB_SAT_LEVEL),\ |
| SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\ |
| SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ |
| SR(DCHUBBUB_SOFT_RESET),\ |
| SR(DCHUBBUB_CRC_CTRL), \ |
| SR(DCN_VM_FB_LOCATION_BASE),\ |
| SR(DCN_VM_FB_LOCATION_TOP),\ |
| SR(DCN_VM_FB_OFFSET),\ |
| SR(DCN_VM_AGP_BOT),\ |
| SR(DCN_VM_AGP_TOP),\ |
| SR(DCN_VM_AGP_BASE),\ |
| HUBBUB_SR_WATERMARK_REG_LIST(), \ |
| SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A),\ |
| SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B),\ |
| SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C),\ |
| SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D),\ |
| SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A),\ |
| SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B),\ |
| SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C),\ |
| SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D),\ |
| SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A),\ |
| SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B),\ |
| SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C),\ |
| SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D),\ |
| SR(DCHUBBUB_DET0_CTRL),\ |
| SR(DCHUBBUB_DET1_CTRL),\ |
| SR(DCHUBBUB_DET2_CTRL),\ |
| SR(DCHUBBUB_DET3_CTRL),\ |
| SR(DCHUBBUB_COMPBUF_CTRL),\ |
| SR(COMPBUF_RESERVED_SPACE),\ |
| SR(DCHUBBUB_DEBUG_CTRL_0),\ |
| SR(DCHUBBUB_ARB_USR_RETRAINING_CNTL),\ |
| SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A),\ |
| SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B),\ |
| SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C),\ |
| SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D),\ |
| SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A),\ |
| SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B),\ |
| SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C),\ |
| SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D),\ |
| SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A),\ |
| SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B),\ |
| SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C),\ |
| SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D),\ |
| SR(DCN_VM_FAULT_ADDR_MSB),\ |
| SR(DCN_VM_FAULT_ADDR_LSB),\ |
| SR(DCN_VM_FAULT_CNTL),\ |
| SR(DCN_VM_FAULT_STATUS),\ |
| SR(SDPIF_REQUEST_RATE_LIMIT),\ |
| SR(DCHUBBUB_CLOCK_CNTL),\ |
| SR(DCHUBBUB_SDPIF_CFG0),\ |
| SR(DCHUBBUB_SDPIF_CFG1),\ |
| SR(DCHUBBUB_MEM_PWR_MODE_CTRL),\ |
| SR(DCHUBBUB_ARB_HOSTVM_CNTL),\ |
| SR(DCHVM_CTRL0),\ |
| SR(DCHVM_MEM_CTRL),\ |
| SR(DCHVM_CLK_CTRL),\ |
| SR(DCHVM_RIOMMU_CTRL0),\ |
| SR(DCHVM_RIOMMU_STAT0),\ |
| SR(DCHUBBUB_COMPBUF_CTRL),\ |
| SR(COMPBUF_RESERVED_SPACE),\ |
| SR(DCHUBBUB_DEBUG_CTRL_0),\ |
| SR(DCHUBBUB_CLOCK_CNTL),\ |
| SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A),\ |
| SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A),\ |
| SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B),\ |
| SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B),\ |
| SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C),\ |
| SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C),\ |
| SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D),\ |
| SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D),\ |
| SR(DCHUBBUB_ARB_QOS_FORCE) |
| |
| |
| #define HUBBUB_MASK_SH_LIST_DCN35(mask_sh)\ |
| HUBBUB_MASK_SH_LIST_DCN32(mask_sh), \ |
| HUBBUB_SF(DCHVM_CTRL0, HOSTVM_INIT_REQ, mask_sh),\ |
| HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_PWR_REQ_DIS, mask_sh),\ |
| HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_FORCE_REQ, mask_sh),\ |
| HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_POWER_STATUS, mask_sh),\ |
| HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DISPCLK_R_GATE_DIS, mask_sh),\ |
| HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DISPCLK_G_GATE_DIS, mask_sh),\ |
| HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DCFCLK_R_GATE_DIS, mask_sh),\ |
| HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DCFCLK_G_GATE_DIS, mask_sh),\ |
| HUBBUB_SF(DCHVM_CLK_CTRL, TR_REQ_REQCLKREQ_MODE, mask_sh),\ |
| HUBBUB_SF(DCHVM_CLK_CTRL, TW_RSP_COMPCLKREQ_MODE, mask_sh),\ |
| HUBBUB_SF(DCHVM_RIOMMU_CTRL0, HOSTVM_PREFETCH_REQ, mask_sh),\ |
| HUBBUB_SF(DCHVM_RIOMMU_CTRL0, HOSTVM_POWERSTATUS, mask_sh),\ |
| HUBBUB_SF(DCHVM_RIOMMU_STAT0, RIOMMU_ACTIVE, mask_sh),\ |
| HUBBUB_SF(DCHVM_RIOMMU_STAT0, HOSTVM_PREFETCH_DONE, mask_sh),\ |
| HUBBUB_SF(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE, mask_sh),\ |
| HUBBUB_SF(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE_CURRENT, mask_sh),\ |
| HUBBUB_SF(DCHUBBUB_COMPBUF_CTRL, CONFIG_ERROR, mask_sh),\ |
| HUBBUB_SF(COMPBUF_RESERVED_SPACE, COMPBUF_RESERVED_SPACE_64B, mask_sh),\ |
| HUBBUB_SF(COMPBUF_RESERVED_SPACE, COMPBUF_RESERVED_SPACE_ZS, mask_sh),\ |
| HUBBUB_SF(DCHUBBUB_CLOCK_CNTL, DCHUBBUB_FGCG_REP_DIS, mask_sh),\ |
| HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A, mask_sh), \ |
| HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B, mask_sh), \ |
| HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C, mask_sh), \ |
| HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D, mask_sh), \ |
| HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A, mask_sh), \ |
| HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B, mask_sh), \ |
| HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C, mask_sh), \ |
| HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, mask_sh), \ |
| HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_CSTATE_DEEPSLEEP_LEGACY_MODE, mask_sh), \ |
| HUBBUB_SF(DCHUBBUB_ARB_HOSTVM_CNTL, DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD, mask_sh),\ |
| HUBBUB_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD, mask_sh) |
| |
| void hubbub35_construct(struct dcn20_hubbub *hubbub2, |
| struct dc_context *ctx, |
| const struct dcn_hubbub_registers *hubbub_regs, |
| const struct dcn_hubbub_shift *hubbub_shift, |
| const struct dcn_hubbub_mask *hubbub_mask, |
| int det_size_kb, |
| int pixel_chunk_size_kb, |
| int config_return_buffer_size_kb); |
| #endif |
