| [ |
| { |
| "BriefDescription": "Each cycle count number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from it's allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic.", |
| "CounterType": "PGMABLE", |
| "EventCode": "0x80", |
| "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", |
| "PerPkg": "1", |
| "PublicDescription": "UNC_ARB_TRK_OCCUPANCY.ALL", |
| "UMask": "0x01", |
| "Unit": "ARB" |
| }, |
| { |
| "BriefDescription": "Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.", |
| "Counter": "1", |
| "CounterType": "FREERUN", |
| "EventName": "UNC_MC0_RDCAS_COUNT_FREERUN", |
| "PerPkg": "1", |
| "PublicDescription": "UNC_MC0_RDCAS_COUNT_FREERUN", |
| "Unit": "h_imc" |
| }, |
| { |
| "BriefDescription": "Counts every 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.", |
| "CounterType": "FREERUN", |
| "EventName": "UNC_MC0_TOTAL_REQCOUNT_FREERUN", |
| "PerPkg": "1", |
| "PublicDescription": "UNC_MC0_TOTAL_REQCOUNT_FREERUN", |
| "Unit": "h_imc" |
| }, |
| { |
| "BriefDescription": "Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.", |
| "Counter": "2", |
| "CounterType": "FREERUN", |
| "EventName": "UNC_MC0_WRCAS_COUNT_FREERUN", |
| "PerPkg": "1", |
| "PublicDescription": "UNC_MC0_WRCAS_COUNT_FREERUN", |
| "Unit": "h_imc" |
| }, |
| { |
| "BriefDescription": "Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.", |
| "Counter": "4", |
| "CounterType": "FREERUN", |
| "EventName": "UNC_MC1_RDCAS_COUNT_FREERUN", |
| "PerPkg": "1", |
| "PublicDescription": "UNC_MC1_RDCAS_COUNT_FREERUN", |
| "Unit": "h_imc" |
| }, |
| { |
| "BriefDescription": "Counts every 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.", |
| "Counter": "3", |
| "CounterType": "FREERUN", |
| "EventName": "UNC_MC1_TOTAL_REQCOUNT_FREERUN", |
| "PerPkg": "1", |
| "PublicDescription": "UNC_MC1_TOTAL_REQCOUNT_FREERUN", |
| "Unit": "h_imc" |
| }, |
| { |
| "BriefDescription": "Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.", |
| "Counter": "5", |
| "CounterType": "FREERUN", |
| "EventName": "UNC_MC1_WRCAS_COUNT_FREERUN", |
| "PerPkg": "1", |
| "PublicDescription": "UNC_MC1_WRCAS_COUNT_FREERUN", |
| "Unit": "h_imc" |
| } |
| ] |
