| [ |
| { |
| "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)", |
| "MetricExpr": "100 * (( BR_INST_RETIRED.COND + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) ) / TOPDOWN.SLOTS)", |
| "MetricGroup": "Ret", |
| "MetricName": "Branching_Overhead" |
| }, |
| { |
| "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)", |
| "MetricExpr": "100 * (( 5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING ) / TOPDOWN.SLOTS) * ( (ICACHE_64B.IFTAG_STALL / CPU_CLK_UNHALTED.THREAD) + (ICACHE_16B.IFDATA_STALL / CPU_CLK_UNHALTED.THREAD) + (10 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) ) / #(( 5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING ) / TOPDOWN.SLOTS)", |
| "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB", |
| "MetricName": "Big_Code" |
| }, |
| { |
| "BriefDescription": "Instructions Per Cycle (per Logical Processor)", |
| "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", |
| "MetricGroup": "Ret;Summary", |
| "MetricName": "IPC" |
| }, |
| { |
| "BriefDescription": "Cycles Per Instruction (per Logical Processor)", |
| "MetricExpr": "1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD)", |
| "MetricGroup": "Pipeline;Mem", |
| "MetricName": "CPI" |
| }, |
| { |
| "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", |
| "MetricExpr": "CPU_CLK_UNHALTED.THREAD", |
| "MetricGroup": "Pipeline", |
| "MetricName": "CLKS" |
| }, |
| { |
| "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", |
| "MetricExpr": "TOPDOWN.SLOTS", |
| "MetricGroup": "TmaL1", |
| "MetricName": "SLOTS" |
| }, |
| { |
| "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor", |
| "MetricExpr": "TOPDOWN.SLOTS / ( TOPDOWN.SLOTS / 2 ) if #SMT_on else 1", |
| "MetricGroup": "SMT;TmaL1", |
| "MetricName": "Slots_Utilization" |
| }, |
| { |
| "BriefDescription": "The ratio of Executed- by Issued-Uops", |
| "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", |
| "MetricGroup": "Cor;Pipeline", |
| "MetricName": "Execute_per_Issue", |
| "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage." |
| }, |
| { |
| "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", |
| "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.DISTRIBUTED", |
| "MetricGroup": "Ret;SMT;TmaL1", |
| "MetricName": "CoreIPC" |
| }, |
| { |
| "BriefDescription": "Floating Point Operations Per Cycle", |
| "MetricExpr": "( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) / CPU_CLK_UNHALTED.DISTRIBUTED", |
| "MetricGroup": "Ret;Flops", |
| "MetricName": "FLOPc" |
| }, |
| { |
| "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)", |
| "MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) ) / ( 2 * CPU_CLK_UNHALTED.DISTRIBUTED )", |
| "MetricGroup": "Cor;Flops;HPC", |
| "MetricName": "FP_Arith_Utilization", |
| "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)." |
| }, |
| { |
| "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core", |
| "MetricExpr": "UOPS_EXECUTED.THREAD / (( UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 ) if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)", |
| "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", |
| "MetricName": "ILP" |
| }, |
| { |
| "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", |
| "MetricExpr": "CPU_CLK_UNHALTED.DISTRIBUTED", |
| "MetricGroup": "SMT", |
| "MetricName": "CORE_CLKS" |
| }, |
| { |
| "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", |
| "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS", |
| "MetricGroup": "InsType", |
| "MetricName": "IpLoad" |
| }, |
| { |
| "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", |
| "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES", |
| "MetricGroup": "InsType", |
| "MetricName": "IpStore" |
| }, |
| { |
| "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", |
| "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", |
| "MetricGroup": "Branches;Fed;InsType", |
| "MetricName": "IpBranch" |
| }, |
| { |
| "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", |
| "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", |
| "MetricGroup": "Branches;Fed;PGO", |
| "MetricName": "IpCall" |
| }, |
| { |
| "BriefDescription": "Instruction per taken branch", |
| "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", |
| "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO", |
| "MetricName": "IpTB" |
| }, |
| { |
| "BriefDescription": "Branch instructions per taken branch. ", |
| "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", |
| "MetricGroup": "Branches;Fed;PGO", |
| "MetricName": "BpTkBranch" |
| }, |
| { |
| "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", |
| "MetricExpr": "INST_RETIRED.ANY / ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE )", |
| "MetricGroup": "Flops;InsType", |
| "MetricName": "IpFLOP" |
| }, |
| { |
| "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)", |
| "MetricExpr": "INST_RETIRED.ANY / ( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) )", |
| "MetricGroup": "Flops;InsType", |
| "MetricName": "IpArith", |
| "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW." |
| }, |
| { |
| "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)", |
| "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE", |
| "MetricGroup": "Flops;FpScalar;InsType", |
| "MetricName": "IpArith_Scalar_SP", |
| "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." |
| }, |
| { |
| "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)", |
| "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", |
| "MetricGroup": "Flops;FpScalar;InsType", |
| "MetricName": "IpArith_Scalar_DP", |
| "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." |
| }, |
| { |
| "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)", |
| "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE )", |
| "MetricGroup": "Flops;FpVector;InsType", |
| "MetricName": "IpArith_AVX128", |
| "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." |
| }, |
| { |
| "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)", |
| "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )", |
| "MetricGroup": "Flops;FpVector;InsType", |
| "MetricName": "IpArith_AVX256", |
| "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." |
| }, |
| { |
| "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate)", |
| "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE )", |
| "MetricGroup": "Flops;FpVector;InsType", |
| "MetricName": "IpArith_AVX512", |
| "PublicDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." |
| }, |
| { |
| "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)", |
| "MetricExpr": "INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\\,umask\\=0xF@", |
| "MetricGroup": "Prefetches", |
| "MetricName": "IpSWPF" |
| }, |
| { |
| "BriefDescription": "Total number of retired Instructions, Sample with: INST_RETIRED.PREC_DIST", |
| "MetricExpr": "INST_RETIRED.ANY", |
| "MetricGroup": "Summary;TmaL1", |
| "MetricName": "Instructions" |
| }, |
| { |
| "BriefDescription": "", |
| "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@", |
| "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", |
| "MetricName": "Execute" |
| }, |
| { |
| "BriefDescription": "Average number of Uops issued by front-end when it issued something", |
| "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=1@", |
| "MetricGroup": "Fed;FetchBW", |
| "MetricName": "Fetch_UpC" |
| }, |
| { |
| "BriefDescription": "Fraction of Uops delivered by the LSD (Loop Stream Detector; aka Loop Cache)", |
| "MetricExpr": "LSD.UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)", |
| "MetricGroup": "Fed;LSD", |
| "MetricName": "LSD_Coverage" |
| }, |
| { |
| "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", |
| "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)", |
| "MetricGroup": "DSB;Fed;FetchBW", |
| "MetricName": "DSB_Coverage" |
| }, |
| { |
| "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.", |
| "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / cpu@DSB2MITE_SWITCHES.PENALTY_CYCLES\\,cmask\\=1\\,edge@", |
| "MetricGroup": "DSBmiss", |
| "MetricName": "DSB_Switch_Cost" |
| }, |
| { |
| "BriefDescription": "Number of Instructions per non-speculative DSB miss (lower number means higher occurrence rate)", |
| "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS", |
| "MetricGroup": "DSBmiss;Fed", |
| "MetricName": "IpDSB_Miss_Ret" |
| }, |
| { |
| "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", |
| "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", |
| "MetricGroup": "Bad;BadSpec;BrMispredicts", |
| "MetricName": "IpMispredict" |
| }, |
| { |
| "BriefDescription": "Fraction of branches that are non-taken conditionals", |
| "MetricExpr": "BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_BRANCHES", |
| "MetricGroup": "Bad;Branches;CodeGen;PGO", |
| "MetricName": "Cond_NT" |
| }, |
| { |
| "BriefDescription": "Fraction of branches that are taken conditionals", |
| "MetricExpr": "BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHES", |
| "MetricGroup": "Bad;Branches;CodeGen;PGO", |
| "MetricName": "Cond_TK" |
| }, |
| { |
| "BriefDescription": "Fraction of branches that are CALL or RET", |
| "MetricExpr": "( BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN ) / BR_INST_RETIRED.ALL_BRANCHES", |
| "MetricGroup": "Bad;Branches", |
| "MetricName": "CallRet" |
| }, |
| { |
| "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps", |
| "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES", |
| "MetricGroup": "Bad;Branches", |
| "MetricName": "Jump" |
| }, |
| { |
| "BriefDescription": "Fraction of branches of other types (not individually covered by other metrics in Info.Branches group)", |
| "MetricExpr": "1 - ( (BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_BRANCHES) + (BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHES) + (( BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN ) / BR_INST_RETIRED.ALL_BRANCHES) + ((BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES) )", |
| "MetricGroup": "Bad;Branches", |
| "MetricName": "Other_Branches" |
| }, |
| { |
| "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", |
| "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT )", |
| "MetricGroup": "Mem;MemoryBound;MemoryLat", |
| "MetricName": "Load_Miss_Real_Latency" |
| }, |
| { |
| "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", |
| "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", |
| "MetricGroup": "Mem;MemoryBound;MemoryBW", |
| "MetricName": "MLP" |
| }, |
| { |
| "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", |
| "MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", |
| "MetricGroup": "Mem;CacheMisses", |
| "MetricName": "L1MPKI" |
| }, |
| { |
| "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)", |
| "MetricExpr": "1000 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY", |
| "MetricGroup": "Mem;CacheMisses", |
| "MetricName": "L1MPKI_Load" |
| }, |
| { |
| "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", |
| "MetricExpr": "1000 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", |
| "MetricGroup": "Mem;Backend;CacheMisses", |
| "MetricName": "L2MPKI" |
| }, |
| { |
| "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)", |
| "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY", |
| "MetricGroup": "Mem;CacheMisses;Offcore", |
| "MetricName": "L2MPKI_All" |
| }, |
| { |
| "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)", |
| "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY", |
| "MetricGroup": "Mem;CacheMisses", |
| "MetricName": "L2MPKI_Load" |
| }, |
| { |
| "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", |
| "MetricExpr": "1000 * ( L2_RQSTS.REFERENCES - L2_RQSTS.MISS ) / INST_RETIRED.ANY", |
| "MetricGroup": "Mem;CacheMisses", |
| "MetricName": "L2HPKI_All" |
| }, |
| { |
| "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", |
| "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY", |
| "MetricGroup": "Mem;CacheMisses", |
| "MetricName": "L2HPKI_Load" |
| }, |
| { |
| "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", |
| "MetricExpr": "1000 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", |
| "MetricGroup": "Mem;CacheMisses", |
| "MetricName": "L3MPKI" |
| }, |
| { |
| "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)", |
| "MetricExpr": "1000 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", |
| "MetricGroup": "Mem;CacheMisses", |
| "MetricName": "FB_HPKI" |
| }, |
| { |
| "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", |
| "MetricConstraint": "NO_NMI_WATCHDOG", |
| "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING ) / ( 2 * CPU_CLK_UNHALTED.DISTRIBUTED )", |
| "MetricGroup": "Mem;MemoryTLB", |
| "MetricName": "Page_Walks_Utilization" |
| }, |
| { |
| "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", |
| "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", |
| "MetricGroup": "Mem;MemoryBW", |
| "MetricName": "L1D_Cache_Fill_BW" |
| }, |
| { |
| "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", |
| "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", |
| "MetricGroup": "Mem;MemoryBW", |
| "MetricName": "L2_Cache_Fill_BW" |
| }, |
| { |
| "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", |
| "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time", |
| "MetricGroup": "Mem;MemoryBW", |
| "MetricName": "L3_Cache_Fill_BW" |
| }, |
| { |
| "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]", |
| "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / duration_time", |
| "MetricGroup": "Mem;MemoryBW;Offcore", |
| "MetricName": "L3_Cache_Access_BW" |
| }, |
| { |
| "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]", |
| "MetricExpr": "(64 * L1D.REPLACEMENT / 1000000000 / duration_time)", |
| "MetricGroup": "Mem;MemoryBW", |
| "MetricName": "L1D_Cache_Fill_BW_1T" |
| }, |
| { |
| "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]", |
| "MetricExpr": "(64 * L2_LINES_IN.ALL / 1000000000 / duration_time)", |
| "MetricGroup": "Mem;MemoryBW", |
| "MetricName": "L2_Cache_Fill_BW_1T" |
| }, |
| { |
| "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]", |
| "MetricExpr": "(64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time)", |
| "MetricGroup": "Mem;MemoryBW", |
| "MetricName": "L3_Cache_Fill_BW_1T" |
| }, |
| { |
| "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]", |
| "MetricExpr": "(64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / duration_time)", |
| "MetricGroup": "Mem;MemoryBW;Offcore", |
| "MetricName": "L3_Cache_Access_BW_1T" |
| }, |
| { |
| "BriefDescription": "Average CPU Utilization", |
| "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", |
| "MetricGroup": "HPC;Summary", |
| "MetricName": "CPU_Utilization" |
| }, |
| { |
| "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", |
| "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time", |
| "MetricGroup": "Summary;Power", |
| "MetricName": "Average_Frequency" |
| }, |
| { |
| "BriefDescription": "Giga Floating Point Operations Per Second", |
| "MetricExpr": "( ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) / 1000000000 ) / duration_time", |
| "MetricGroup": "Cor;Flops;HPC", |
| "MetricName": "GFLOPs", |
| "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine." |
| }, |
| { |
| "BriefDescription": "Average Frequency Utilization relative nominal frequency", |
| "MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC", |
| "MetricGroup": "Power", |
| "MetricName": "Turbo_Utilization" |
| }, |
| { |
| "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0", |
| "MetricExpr": "CORE_POWER.LVL0_TURBO_LICENSE / CPU_CLK_UNHALTED.DISTRIBUTED", |
| "MetricGroup": "Power", |
| "MetricName": "Power_License0_Utilization", |
| "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes." |
| }, |
| { |
| "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1", |
| "MetricExpr": "CORE_POWER.LVL1_TURBO_LICENSE / CPU_CLK_UNHALTED.DISTRIBUTED", |
| "MetricGroup": "Power", |
| "MetricName": "Power_License1_Utilization", |
| "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions." |
| }, |
| { |
| "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX)", |
| "MetricExpr": "CORE_POWER.LVL2_TURBO_LICENSE / CPU_CLK_UNHALTED.DISTRIBUTED", |
| "MetricGroup": "Power", |
| "MetricName": "Power_License2_Utilization", |
| "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX). This includes high current AVX 512-bit instructions." |
| }, |
| { |
| "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", |
| "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_on else 0", |
| "MetricGroup": "SMT", |
| "MetricName": "SMT_2T_Utilization" |
| }, |
| { |
| "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", |
| "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", |
| "MetricGroup": "OS", |
| "MetricName": "Kernel_Utilization" |
| }, |
| { |
| "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", |
| "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", |
| "MetricGroup": "OS", |
| "MetricName": "Kernel_CPI" |
| }, |
| { |
| "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", |
| "MetricExpr": "64 * ( arb@event\\=0x81\\,umask\\=0x1@ + arb@event\\=0x84\\,umask\\=0x1@ ) / 1000000 / duration_time / 1000", |
| "MetricGroup": "HPC;Mem;MemoryBW;SoC", |
| "MetricName": "DRAM_BW_Use" |
| }, |
| { |
| "BriefDescription": "Average number of parallel requests to external memory. Accounts for all requests", |
| "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@", |
| "MetricGroup": "Mem;SoC", |
| "MetricName": "MEM_Parallel_Requests" |
| }, |
| { |
| "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", |
| "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", |
| "MetricGroup": "Branches;OS", |
| "MetricName": "IpFarBranch" |
| }, |
| { |
| "BriefDescription": "C6 residency percent per core", |
| "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100", |
| "MetricGroup": "Power", |
| "MetricName": "C6_Core_Residency" |
| }, |
| { |
| "BriefDescription": "C7 residency percent per core", |
| "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100", |
| "MetricGroup": "Power", |
| "MetricName": "C7_Core_Residency" |
| }, |
| { |
| "BriefDescription": "C2 residency percent per package", |
| "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100", |
| "MetricGroup": "Power", |
| "MetricName": "C2_Pkg_Residency" |
| }, |
| { |
| "BriefDescription": "C3 residency percent per package", |
| "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100", |
| "MetricGroup": "Power", |
| "MetricName": "C3_Pkg_Residency" |
| }, |
| { |
| "BriefDescription": "C6 residency percent per package", |
| "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100", |
| "MetricGroup": "Power", |
| "MetricName": "C6_Pkg_Residency" |
| }, |
| { |
| "BriefDescription": "C7 residency percent per package", |
| "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100", |
| "MetricGroup": "Power", |
| "MetricName": "C7_Pkg_Residency" |
| }, |
| { |
| "BriefDescription": "C8 residency percent per package", |
| "MetricExpr": "(cstate_pkg@c8\\-residency@ / msr@tsc@) * 100", |
| "MetricGroup": "Power", |
| "MetricName": "C8_Pkg_Residency" |
| }, |
| { |
| "BriefDescription": "C9 residency percent per package", |
| "MetricExpr": "(cstate_pkg@c9\\-residency@ / msr@tsc@) * 100", |
| "MetricGroup": "Power", |
| "MetricName": "C9_Pkg_Residency" |
| }, |
| { |
| "BriefDescription": "C10 residency percent per package", |
| "MetricExpr": "(cstate_pkg@c10\\-residency@ / msr@tsc@) * 100", |
| "MetricGroup": "Power", |
| "MetricName": "C10_Pkg_Residency" |
| } |
| ] |
