| [ |
| { |
| "BriefDescription": "Number of clocks", |
| "Counter": "0,1,2,3,4", |
| "CounterType": "PGMABLE", |
| "EventCode": "0x01", |
| "EventName": "UNC_M_CLOCKTICKS", |
| "PerPkg": "1", |
| "Unit": "iMC" |
| }, |
| { |
| "BriefDescription": "Incoming VC0 read request", |
| "Counter": "0,1,2,3,4", |
| "CounterType": "PGMABLE", |
| "EventCode": "0x02", |
| "EventName": "UNC_M_VC0_REQUESTS_RD", |
| "PerPkg": "1", |
| "Unit": "iMC" |
| }, |
| { |
| "BriefDescription": "Incoming VC0 write request", |
| "Counter": "0,1,2,3,4", |
| "CounterType": "PGMABLE", |
| "EventCode": "0x03", |
| "EventName": "UNC_M_VC0_REQUESTS_WR", |
| "PerPkg": "1", |
| "Unit": "iMC" |
| }, |
| { |
| "BriefDescription": "Incoming VC1 read request", |
| "Counter": "0,1,2,3,4", |
| "CounterType": "PGMABLE", |
| "EventCode": "0x04", |
| "EventName": "UNC_M_VC1_REQUESTS_RD", |
| "PerPkg": "1", |
| "Unit": "iMC" |
| }, |
| { |
| "BriefDescription": "Incoming VC1 write request", |
| "Counter": "0,1,2,3,4", |
| "CounterType": "PGMABLE", |
| "EventCode": "0x05", |
| "EventName": "UNC_M_VC1_REQUESTS_WR", |
| "PerPkg": "1", |
| "Unit": "iMC" |
| }, |
| { |
| "BriefDescription": "Incoming read prefetch request from IA", |
| "Counter": "0,1,2,3,4", |
| "CounterType": "PGMABLE", |
| "EventCode": "0x0A", |
| "EventName": "UNC_M_PREFETCH_RD", |
| "PerPkg": "1", |
| "Unit": "iMC" |
| }, |
| { |
| "BriefDescription": "Any Rank at Hot state", |
| "Counter": "0,1,2,3,4", |
| "CounterType": "PGMABLE", |
| "EventCode": "0x19", |
| "EventName": "UNC_M_DRAM_THERMAL_HOT", |
| "PerPkg": "1", |
| "Unit": "iMC" |
| }, |
| { |
| "BriefDescription": "Any Rank at Warm state", |
| "Counter": "0,1,2,3,4", |
| "CounterType": "PGMABLE", |
| "EventCode": "0x1A", |
| "EventName": "UNC_M_DRAM_THERMAL_WARM", |
| "PerPkg": "1", |
| "Unit": "iMC" |
| }, |
| { |
| "BriefDescription": "incoming read request page status is Page Hit", |
| "Counter": "0,1,2,3,4", |
| "CounterType": "PGMABLE", |
| "EventCode": "0x1C", |
| "EventName": "UNC_M_DRAM_PAGE_HIT_RD", |
| "PerPkg": "1", |
| "Unit": "iMC" |
| }, |
| { |
| "BriefDescription": "incoming read request page status is Page Empty", |
| "Counter": "0,1,2,3,4", |
| "CounterType": "PGMABLE", |
| "EventCode": "0x1D", |
| "EventName": "UNC_M_DRAM_PAGE_EMPTY_RD", |
| "PerPkg": "1", |
| "Unit": "iMC" |
| }, |
| { |
| "BriefDescription": "incoming read request page status is Page Miss", |
| "Counter": "0,1,2,3,4", |
| "CounterType": "PGMABLE", |
| "EventCode": "0x1E", |
| "EventName": "UNC_M_DRAM_PAGE_MISS_RD", |
| "PerPkg": "1", |
| "Unit": "iMC" |
| }, |
| { |
| "BriefDescription": "incoming write request page status is Page Hit", |
| "Counter": "0,1,2,3,4", |
| "CounterType": "PGMABLE", |
| "EventCode": "0x1F", |
| "EventName": "UNC_M_DRAM_PAGE_HIT_WR", |
| "PerPkg": "1", |
| "Unit": "iMC" |
| }, |
| { |
| "BriefDescription": "incoming write request page status is Page Empty", |
| "Counter": "0,1,2,3,4", |
| "CounterType": "PGMABLE", |
| "EventCode": "0x20", |
| "EventName": "UNC_M_DRAM_PAGE_EMPTY_WR", |
| "PerPkg": "1", |
| "Unit": "iMC" |
| }, |
| { |
| "BriefDescription": "incoming write request page status is Page Miss", |
| "Counter": "0,1,2,3,4", |
| "CounterType": "PGMABLE", |
| "EventCode": "0x21", |
| "EventName": "UNC_M_DRAM_PAGE_MISS_WR", |
| "PerPkg": "1", |
| "Unit": "iMC" |
| }, |
| { |
| "BriefDescription": "Read CAS command sent to DRAM", |
| "Counter": "0,1,2,3,4", |
| "CounterType": "PGMABLE", |
| "EventCode": "0x22", |
| "EventName": "UNC_M_CAS_COUNT_RD", |
| "PerPkg": "1", |
| "Unit": "iMC" |
| }, |
| { |
| "BriefDescription": "Write CAS command sent to DRAM", |
| "Counter": "0,1,2,3,4", |
| "CounterType": "PGMABLE", |
| "EventCode": "0x23", |
| "EventName": "UNC_M_CAS_COUNT_WR", |
| "PerPkg": "1", |
| "Unit": "iMC" |
| }, |
| { |
| "BriefDescription": "ACT command for a read request sent to DRAM", |
| "Counter": "0,1,2,3,4", |
| "CounterType": "PGMABLE", |
| "EventCode": "0x24", |
| "EventName": "UNC_M_ACT_COUNT_RD", |
| "PerPkg": "1", |
| "Unit": "iMC" |
| }, |
| { |
| "BriefDescription": "ACT command for a write request sent to DRAM", |
| "Counter": "0,1,2,3,4", |
| "CounterType": "PGMABLE", |
| "EventCode": "0x25", |
| "EventName": "UNC_M_ACT_COUNT_WR", |
| "PerPkg": "1", |
| "Unit": "iMC" |
| }, |
| { |
| "BriefDescription": "ACT command sent to DRAM", |
| "Counter": "0,1,2,3,4", |
| "CounterType": "PGMABLE", |
| "EventCode": "0x26", |
| "EventName": "UNC_M_ACT_COUNT_TOTAL", |
| "PerPkg": "1", |
| "Unit": "iMC" |
| }, |
| { |
| "BriefDescription": "PRE command sent to DRAM for a read/write request", |
| "Counter": "0,1,2,3,4", |
| "CounterType": "PGMABLE", |
| "EventCode": "0x27", |
| "EventName": "UNC_M_PRE_COUNT_PAGE_MISS", |
| "PerPkg": "1", |
| "Unit": "iMC" |
| }, |
| { |
| "BriefDescription": "PRE command sent to DRAM due to page table idle timer expiration", |
| "Counter": "0,1,2,3,4", |
| "CounterType": "PGMABLE", |
| "EventCode": "0x28", |
| "EventName": "UNC_M_PRE_COUNT_IDLE", |
| "PerPkg": "1", |
| "Unit": "iMC" |
| }, |
| { |
| "BriefDescription": "Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channels)", |
| "CounterType": "FREERUN", |
| "EventName": "UNC_MC0_RDCAS_COUNT_FREERUN", |
| "PerPkg": "1", |
| "Unit": "iMC" |
| }, |
| { |
| "BriefDescription": "Counts every 64B read request entering the Memory Controller 1 to DRAM (sum of all channels)", |
| "Counter": "3", |
| "CounterType": "FREERUN", |
| "EventName": "UNC_MC1_RDCAS_COUNT_FREERUN", |
| "PerPkg": "1", |
| "Unit": "iMC" |
| }, |
| { |
| "BriefDescription": "Counts every 64B write request entering the Memory Controller 0 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM", |
| "Counter": "1", |
| "CounterType": "FREERUN", |
| "EventName": "UNC_MC0_WRCAS_COUNT_FREERUN", |
| "PerPkg": "1", |
| "Unit": "iMC" |
| }, |
| { |
| "BriefDescription": "Counts every 64B write request entering the Memory Controller 1 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM", |
| "Counter": "4", |
| "CounterType": "FREERUN", |
| "EventName": "UNC_MC1_WRCAS_COUNT_FREERUN", |
| "PerPkg": "1", |
| "Unit": "iMC" |
| } |
| ] |
