| [ |
| { |
| "BriefDescription": "Counts the number of floating point operations retired that required microcode assist.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3,4,5", |
| "EventCode": "0xc3", |
| "EventName": "MACHINE_CLEARS.FP_ASSIST", |
| "PEBScounters": "0,1,2,3,4,5", |
| "SampleAfterValue": "20003", |
| "Speculative": "1", |
| "UMask": "0x4", |
| "Unit": "cpu_atom" |
| }, |
| { |
| "BriefDescription": "Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt).", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3,4,5", |
| "EventCode": "0xc2", |
| "EventName": "UOPS_RETIRED.FPDIV", |
| "PEBS": "1", |
| "PEBScounters": "0,1,2,3,4,5", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x8", |
| "Unit": "cpu_atom" |
| }, |
| { |
| "BriefDescription": "ARITH.FPDIV_ACTIVE", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "CounterMask": "1", |
| "EventCode": "0xb0", |
| "EventName": "ARITH.FPDIV_ACTIVE", |
| "PEBScounters": "0,1,2,3,4,5,6,7", |
| "SampleAfterValue": "1000003", |
| "Speculative": "1", |
| "UMask": "0x1", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Counts all microcode FP assists.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc1", |
| "EventName": "ASSISTS.FP", |
| "PEBScounters": "0,1,2,3,4,5,6,7", |
| "SampleAfterValue": "100003", |
| "Speculative": "1", |
| "UMask": "0x2", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "ASSISTS.SSE_AVX_MIX", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc1", |
| "EventName": "ASSISTS.SSE_AVX_MIX", |
| "PEBScounters": "0,1,2,3,4,5,6,7", |
| "SampleAfterValue": "1000003", |
| "Speculative": "1", |
| "UMask": "0x10", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "FP_ARITH_DISPATCHED.PORT_0", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xb3", |
| "EventName": "FP_ARITH_DISPATCHED.PORT_0", |
| "PEBScounters": "0,1,2,3,4,5,6,7", |
| "SampleAfterValue": "2000003", |
| "Speculative": "1", |
| "UMask": "0x1", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "FP_ARITH_DISPATCHED.PORT_1", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xb3", |
| "EventName": "FP_ARITH_DISPATCHED.PORT_1", |
| "PEBScounters": "0,1,2,3,4,5,6,7", |
| "SampleAfterValue": "2000003", |
| "Speculative": "1", |
| "UMask": "0x2", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "FP_ARITH_DISPATCHED.PORT_5", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xb3", |
| "EventName": "FP_ARITH_DISPATCHED.PORT_5", |
| "PEBScounters": "0,1,2,3,4,5,6,7", |
| "SampleAfterValue": "2000003", |
| "Speculative": "1", |
| "UMask": "0x4", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc7", |
| "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", |
| "PEBScounters": "0,1,2,3,4,5,6,7", |
| "SampleAfterValue": "100003", |
| "UMask": "0x4", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc7", |
| "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", |
| "PEBScounters": "0,1,2,3,4,5,6,7", |
| "SampleAfterValue": "100003", |
| "UMask": "0x8", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc7", |
| "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", |
| "PEBScounters": "0,1,2,3,4,5,6,7", |
| "SampleAfterValue": "100003", |
| "UMask": "0x10", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc7", |
| "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", |
| "PEBScounters": "0,1,2,3,4,5,6,7", |
| "SampleAfterValue": "100003", |
| "UMask": "0x20", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc7", |
| "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", |
| "PEBScounters": "0,1,2,3,4,5,6,7", |
| "SampleAfterValue": "100003", |
| "UMask": "0x1", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc7", |
| "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", |
| "PEBScounters": "0,1,2,3,4,5,6,7", |
| "SampleAfterValue": "100003", |
| "UMask": "0x2", |
| "Unit": "cpu_core" |
| } |
| ] |
