| /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ |
| /* |
| * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. |
| */ |
| |
| #ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ5210_H |
| #define _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ5210_H |
| |
| #define GCC_ADSS_PWM_CLK 0 |
| #define GCC_ADSS_PWM_CLK_SRC 1 |
| #define GCC_CMN_12GPLL_AHB_CLK 2 |
| #define GCC_CMN_12GPLL_SYS_CLK 3 |
| #define GCC_CNOC_LPASS_CFG_CLK 4 |
| #define GCC_CNOC_PCIE0_1LANE_S_CLK 5 |
| #define GCC_CNOC_PCIE1_2LANE_S_CLK 6 |
| #define GCC_CNOC_USB_CLK 7 |
| #define GCC_GEPHY_SYS_CLK 8 |
| #define GCC_LPASS_AXIM_CLK_SRC 9 |
| #define GCC_LPASS_CORE_AXIM_CLK 10 |
| #define GCC_LPASS_SWAY_CLK 11 |
| #define GCC_LPASS_SWAY_CLK_SRC 12 |
| #define GCC_MDIO_AHB_CLK 13 |
| #define GCC_MDIO_GEPHY_AHB_CLK 14 |
| #define GCC_NSS_TS_CLK 15 |
| #define GCC_NSS_TS_CLK_SRC 16 |
| #define GCC_NSSCC_CLK 17 |
| #define GCC_NSSCFG_CLK 18 |
| #define GCC_NSSNOC_ATB_CLK 19 |
| #define GCC_NSSNOC_MEMNOC_1_CLK 20 |
| #define GCC_NSSNOC_MEMNOC_BFDCD_CLK_SRC 21 |
| #define GCC_NSSNOC_MEMNOC_CLK 22 |
| #define GCC_NSSNOC_MEMNOC_DIV_CLK_SRC 23 |
| #define GCC_NSSNOC_NSSCC_CLK 24 |
| #define GCC_NSSNOC_PCNOC_1_CLK 25 |
| #define GCC_NSSNOC_QOSGEN_REF_CLK 26 |
| #define GCC_NSSNOC_SNOC_1_CLK 27 |
| #define GCC_NSSNOC_SNOC_CLK 28 |
| #define GCC_NSSNOC_TIMEOUT_REF_CLK 29 |
| #define GCC_NSSNOC_XO_DCD_CLK 30 |
| #define GCC_PCIE0_AHB_CLK 31 |
| #define GCC_PCIE0_AUX_CLK 32 |
| #define GCC_PCIE0_AXI_M_CLK 33 |
| #define GCC_PCIE0_AXI_M_CLK_SRC 34 |
| #define GCC_PCIE0_AXI_S_BRIDGE_CLK 35 |
| #define GCC_PCIE0_AXI_S_CLK 36 |
| #define GCC_PCIE0_AXI_S_CLK_SRC 37 |
| #define GCC_PCIE0_PIPE_CLK 38 |
| #define GCC_PCIE0_PIPE_CLK_SRC 39 |
| #define GCC_PCIE0_RCHNG_CLK 40 |
| #define GCC_PCIE0_RCHNG_CLK_SRC 41 |
| #define GCC_PCIE1_AHB_CLK 42 |
| #define GCC_PCIE1_AUX_CLK 43 |
| #define GCC_PCIE1_AXI_M_CLK 44 |
| #define GCC_PCIE1_AXI_M_CLK_SRC 45 |
| #define GCC_PCIE1_AXI_S_BRIDGE_CLK 46 |
| #define GCC_PCIE1_AXI_S_CLK 47 |
| #define GCC_PCIE1_AXI_S_CLK_SRC 48 |
| #define GCC_PCIE1_PIPE_CLK 49 |
| #define GCC_PCIE1_PIPE_CLK_SRC 50 |
| #define GCC_PCIE1_RCHNG_CLK 51 |
| #define GCC_PCIE1_RCHNG_CLK_SRC 52 |
| #define GCC_PCIE_AUX_CLK_SRC 53 |
| #define GCC_PCNOC_BFDCD_CLK_SRC 54 |
| #define GCC_PON_APB_CLK 55 |
| #define GCC_PON_TM_CLK 56 |
| #define GCC_PON_TM2X_CLK 57 |
| #define GCC_PON_TM2X_CLK_SRC 58 |
| #define GCC_QDSS_AT_CLK 59 |
| #define GCC_QDSS_AT_CLK_SRC 60 |
| #define GCC_QDSS_DAP_CLK 61 |
| #define GCC_QDSS_TSCTR_CLK_SRC 62 |
| #define GCC_QPIC_AHB_CLK 63 |
| #define GCC_QPIC_CLK 64 |
| #define GCC_QPIC_CLK_SRC 65 |
| #define GCC_QPIC_IO_MACRO_CLK 66 |
| #define GCC_QPIC_IO_MACRO_CLK_SRC 67 |
| #define GCC_QRNG_AHB_CLK 68 |
| #define GCC_QUPV3_AHB_MST_CLK 69 |
| #define GCC_QUPV3_AHB_SLV_CLK 70 |
| #define GCC_QUPV3_WRAP_SE0_CLK 71 |
| #define GCC_QUPV3_WRAP_SE0_CLK_SRC 72 |
| #define GCC_QUPV3_WRAP_SE1_CLK 73 |
| #define GCC_QUPV3_WRAP_SE1_CLK_SRC 74 |
| #define GCC_QUPV3_WRAP_SE2_CLK 75 |
| #define GCC_QUPV3_WRAP_SE2_CLK_SRC 76 |
| #define GCC_QUPV3_WRAP_SE3_CLK 77 |
| #define GCC_QUPV3_WRAP_SE3_CLK_SRC 78 |
| #define GCC_QUPV3_WRAP_SE4_CLK 79 |
| #define GCC_QUPV3_WRAP_SE4_CLK_SRC 80 |
| #define GCC_QUPV3_WRAP_SE5_CLK 81 |
| #define GCC_QUPV3_WRAP_SE5_CLK_SRC 82 |
| #define GCC_SDCC1_AHB_CLK 83 |
| #define GCC_SDCC1_APPS_CLK 84 |
| #define GCC_SDCC1_APPS_CLK_SRC 85 |
| #define GCC_SDCC1_ICE_CORE_CLK 86 |
| #define GCC_SDCC1_ICE_CORE_CLK_SRC 87 |
| #define GCC_SLEEP_CLK_SRC 88 |
| #define GCC_SNOC_LPASS_CLK 89 |
| #define GCC_SNOC_PCIE0_AXI_M_CLK 90 |
| #define GCC_SNOC_PCIE1_AXI_M_CLK 91 |
| #define GCC_SYSTEM_NOC_BFDCD_CLK_SRC 92 |
| #define GCC_UNIPHY0_AHB_CLK 93 |
| #define GCC_UNIPHY0_SYS_CLK 94 |
| #define GCC_UNIPHY1_AHB_CLK 95 |
| #define GCC_UNIPHY1_SYS_CLK 96 |
| #define GCC_UNIPHY2_AHB_CLK 97 |
| #define GCC_UNIPHY2_SYS_CLK 98 |
| #define GCC_UNIPHY_SYS_CLK_SRC 99 |
| #define GCC_USB0_AUX_CLK 100 |
| #define GCC_USB0_AUX_CLK_SRC 101 |
| #define GCC_USB0_MASTER_CLK 102 |
| #define GCC_USB0_MASTER_CLK_SRC 103 |
| #define GCC_USB0_MOCK_UTMI_CLK 104 |
| #define GCC_USB0_MOCK_UTMI_CLK_SRC 105 |
| #define GCC_USB0_MOCK_UTMI_DIV_CLK_SRC 106 |
| #define GCC_USB0_PHY_CFG_AHB_CLK 107 |
| #define GCC_USB0_PIPE_CLK 108 |
| #define GCC_USB0_PIPE_CLK_SRC 109 |
| #define GCC_USB0_SLEEP_CLK 110 |
| #define GCC_XO_CLK_SRC 111 |
| #define GPLL0_MAIN 112 |
| #define GPLL0 113 |
| #define GPLL2_MAIN 114 |
| #define GPLL2 115 |
| #define GPLL4_MAIN 116 |
| #endif |
