| /* SPDX-License-Identifier: GPL-2.0 */ |
| /* |
| * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. All rights reserved. |
| */ |
| |
| #ifndef QCOM_PHY_QMP_PCS_PCIE_V8_H_ |
| #define QCOM_PHY_QMP_PCS_PCIE_V8_H_ |
| |
| /* Only for QMP V8 PHY - PCIE PCS registers */ |
| |
| #define QPHY_PCIE_V8_PCS_POWER_STATE_CONFIG2 0x00c |
| #define QPHY_PCIE_V8_PCS_TX_RX_CONFIG 0x018 |
| #define QPHY_PCIE_V8_PCS_ENDPOINT_REFCLK_DRIVE 0x01c |
| #define QPHY_PCIE_V8_PCS_OSC_DTCT_ACTIONS 0x090 |
| #define QPHY_PCIE_V8_PCS_EQ_CONFIG1 0x0a0 |
| #define QPHY_PCIE_V8_PCS_G3_RXEQEVAL_TIME 0x0f0 |
| #define QPHY_PCIE_V8_PCS_G4_RXEQEVAL_TIME 0x0f4 |
| #define QPHY_PCIE_V8_PCS_G4_EQ_CONFIG5 0x108 |
| #define QPHY_PCIE_V8_PCS_G4_PRE_GAIN 0x15c |
| #define QPHY_PCIE_V8_PCS_G12S1_TXDEEMPH_M6DB 0x170 |
| #define QPHY_PCIE_V8_PCS_G3S2_PRE_GAIN 0x178 |
| #define QPHY_PCIE_V8_PCS_RX_MARGINING_CONFIG1 0x17c |
| #define QPHY_PCIE_V8_PCS_RX_MARGINING_CONFIG3 0x184 |
| #define QPHY_PCIE_V8_PCS_RX_MARGINING_CONFIG5 0x18c |
| #define QPHY_PCIE_V8_PCS_RX_SIGDET_LVL 0x190 |
| #define QPHY_PCIE_V8_PCS_G3_FOM_EQ_CONFIG5 0x1ac |
| #define QPHY_PCIE_V8_PCS_ELECIDLE_DLY_SEL 0x1b8 |
| #define QPHY_PCIE_V8_PCS_G4_FOM_EQ_CONFIG5 0x1c0 |
| #define QPHY_PCIE_V8_PCS_POWER_STATE_CONFIG6 0x1d0 |
| #define QPHY_PCIE_V8_PCS_PCS_TX_RX_CONFIG1 0x1dc |
| #define QPHY_PCIE_V8_PCS_PCS_TX_RX_CONFIG2 0x1e0 |
| #define QPHY_PCIE_V8_PCS_EQ_CONFIG4 0x1f8 |
| #define QPHY_PCIE_V8_PCS_EQ_CONFIG5 0x1fc |
| #endif |
