Documentation/devicetree/bindings/timer/renesas,rzn1-timer.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/renesas,rzn1-timer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas RZ/N1 timers

maintainers:
  - Herve Codina <herve.codina@bootlin.com>

description: |
  The Renesas RZ/N1 SoCs timers block controller is composed of 8 independent
  timers.
    - 6 are 16-bit timers
    - 2 are 32-bit timers

  Each timer has its own interrupt line and can work in either one-shot or
  periodic mode.

properties:
  compatible:
    items:
      - const: renesas,r9a06g032-timer   # RZ/N1D
      - const: renesas,rzn1-timer

  reg:
    maxItems: 1

  clocks:
    items:
      - description: APB internal bus clock

  clock-names:
    items:
      - const: pclk

  power-domains:
    maxItems: 1

  interrupts:
    maxItems: 8

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - power-domains
  - interrupts

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/r9a06g032-sysctrl.h>

    timer@51001000 {
        compatible = "renesas,r9a06g032-timer", "renesas,rzn1-timer";
        reg = <0x51001000 0x200>;
        clocks = <&sysctrl R9A06G032_HCLK_TIMER0>;
        clock-names = "pclk";
        power-domains = <&sysctrl>;
        interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
    };
...