| # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-wm8962.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: NVIDIA Tegra audio complex with WM8962 CODEC |
| |
| maintainers: |
| - Svyatoslav Ryhel <clamor95@gmail.com> |
| |
| allOf: |
| - $ref: nvidia,tegra-audio-common.yaml# |
| |
| properties: |
| compatible: |
| items: |
| - pattern: '^[a-z0-9]+,tegra-audio-wm8962(-[a-z0-9]+)+$' |
| - const: nvidia,tegra-audio-wm8962 |
| |
| nvidia,audio-routing: |
| $ref: /schemas/types.yaml#/definitions/non-unique-string-array |
| description: |
| A list of the connections between audio components. Each entry is a |
| pair of strings, the first being the connection's sink, the second |
| being the connection's source. Valid names for sources and sinks are |
| the pins (documented in the binding document), and the jacks on the |
| board. |
| minItems: 2 |
| items: |
| enum: |
| # Board Connectors |
| - Speakers |
| - Int Spk |
| - Earpiece |
| - Int Mic |
| - Headset Mic |
| - Internal Mic 1 |
| - Internal Mic 2 |
| - Headphone |
| - Headphones |
| - Headphone Jack |
| - Mic Jack |
| |
| # CODEC Pins |
| - IN1L |
| - IN1R |
| - IN2L |
| - IN2R |
| - IN3L |
| - IN3R |
| - IN4L |
| - IN4R |
| - DMICDAT |
| - HPOUTL |
| - HPOUTR |
| - SPKOUT |
| - SPKOUTL |
| - SPKOUTR |
| |
| required: |
| - nvidia,i2s-controller |
| |
| unevaluatedProperties: false |
| |
| examples: |
| - | |
| #include <dt-bindings/clock/tegra30-car.h> |
| #include <dt-bindings/soc/tegra-pmc.h> |
| sound { |
| compatible = "microsoft,tegra-audio-wm8962-surface-rt", |
| "nvidia,tegra-audio-wm8962"; |
| nvidia,model = "Microsoft Surface RT WM8962"; |
| |
| nvidia,audio-routing = |
| "Headphone Jack", "HPOUTR", |
| "Headphone Jack", "HPOUTL", |
| "Int Spk", "SPKOUTR", |
| "Int Spk", "SPKOUTL"; |
| |
| nvidia,i2s-controller = <&tegra_i2s1>; |
| nvidia,audio-codec = <&wm8962>; |
| |
| clocks = <&tegra_car TEGRA30_CLK_PLL_A>, |
| <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, |
| <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; |
| clock-names = "pll_a", "pll_a_out0", "mclk"; |
| }; |
