| # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-cpcap.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: NVIDIA Tegra audio complex with CPCAP CODEC |
| |
| maintainers: |
| - Svyatoslav Ryhel <clamor95@gmail.com> |
| |
| allOf: |
| - $ref: nvidia,tegra-audio-common.yaml# |
| |
| properties: |
| compatible: |
| items: |
| - pattern: '^motorola,tegra-audio-cpcap(-[a-z0-9]+)+$' |
| - const: nvidia,tegra-audio-cpcap |
| |
| nvidia,audio-routing: |
| $ref: /schemas/types.yaml#/definitions/non-unique-string-array |
| description: |
| A list of the connections between audio components. Each entry is a |
| pair of strings, the first being the connection's sink, the second |
| being the connection's source. Valid names for sources and sinks are |
| the pins (documented in the binding document), and the jacks on the |
| board. |
| minItems: 2 |
| items: |
| enum: |
| # Board Connectors |
| - Speakers |
| - Int Spk |
| - Earpiece |
| - Int Mic |
| - Headset Mic |
| - Internal Mic 1 |
| - Internal Mic 2 |
| - Headphone |
| - Headphones |
| - Headphone Jack |
| - Mic Jack |
| |
| # CODEC Pins |
| - MICR |
| - HSMIC |
| - EMUMIC |
| - MICL |
| - EXTR |
| - EXTL |
| - EP |
| - SPKR |
| - SPKL |
| - LINER |
| - LINEL |
| - HSR |
| - HSL |
| - EMUR |
| - EMUL |
| |
| unevaluatedProperties: false |
| |
| examples: |
| - | |
| #include <dt-bindings/clock/tegra20-car.h> |
| #include <dt-bindings/soc/tegra-pmc.h> |
| sound { |
| compatible = "motorola,tegra-audio-cpcap-olympus", |
| "nvidia,tegra-audio-cpcap"; |
| nvidia,model = "Motorola Atrix 4G (MB860) CPCAP"; |
| |
| nvidia,audio-routing = |
| "Headphones", "HSR", |
| "Headphones", "HSL", |
| "Int Spk", "SPKR", |
| "Int Spk", "SPKL", |
| "Earpiece", "EP", |
| "HSMIC", "Mic Jack", |
| "MICR", "Internal Mic 1", |
| "MICL", "Internal Mic 2"; |
| |
| nvidia,i2s-controller = <&tegra_i2s1>; |
| nvidia,audio-codec = <&cpcap_audio>; |
| |
| clocks = <&tegra_car TEGRA20_CLK_PLL_A>, |
| <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, |
| <&tegra_car TEGRA20_CLK_CDEV1>; |
| clock-names = "pll_a", "pll_a_out0", "mclk"; |
| }; |
