Documentation/devicetree/bindings/pinctrl/qcom,hawi-tlmm.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,hawi-tlmm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies, Inc. Hawi TLMM block

maintainers:
  - Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>

description:
  Top Level Mode Multiplexer pin controller in Qualcomm Hawi SoC.

allOf:
  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

properties:
  compatible:
    const: qcom,hawi-tlmm

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  gpio-reserved-ranges:
    minItems: 1
    maxItems: 113

  gpio-line-names:
    maxItems: 226

patternProperties:
  "-state$":
    oneOf:
      - $ref: "#/$defs/qcom-hawi-tlmm-state"
      - patternProperties:
          "-pins$":
            $ref: "#/$defs/qcom-hawi-tlmm-state"
        additionalProperties: false

$defs:
  qcom-hawi-tlmm-state:
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.
    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
    unevaluatedProperties: false

    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in this
          subnode.
        items:
          oneOf:
            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9]|21[0-9]|22[0-5])$"
            - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
        minItems: 1
        maxItems: 36

      function:
        description:
          Specify the alternative function to be configured for the specified
          pins.
        enum: [ gpio, aoss_cti, atest_char, atest_usb, audio_ext_mclk,
                audio_ref_clk, cam_mclk, cci_async_in, cci_i2c0, cci_i2c1,
                cci_i2c2, cci_i2c3, cci_i2c4, cci_i2c5, cci_timer, coex_espmi,
                coex_uart1_rx, coex_uart1_tx, dbg_out_clk, ddr_bist, ddr_pxi,
                dp_hot, egpio, gcc_gp, gnss_adc, host_rst, i2chub0_se0,
                i2chub0_se1, i2chub0_se2, i2chub0_se3, i2chub0_se4, i2s0, i2s1,
                ibi_i3c, jitter_bist, mdp_esync0, mdp_esync1, mdp_esync2,
                mdp_vsync, mdp_vsync_e, mdp_vsync_p, mdp_vsync0_out,
                mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out, mdp_vsync5_out,
                modem_pps_in, modem_pps_out, nav_gpio, nav_gpio0, nav_gpio3,
                nav_rffe, pcie0_clk_req_n, pcie0_rst_n, pcie1_clk_req_n,
                phase_flag, pll_bist_sync, pll_clk_aux, qdss_cti, qlink,
                qspi, qspi_clk, qspi_cs, qup1_se0, qup1_se1, qup1_se2,
                qup1_se3, qup1_se4, qup1_se5, qup1_se6, qup1_se7, qup2_se0,
                qup2_se1, qup2_se2, qup2_se3, qup2_se4_01, qup2_se4_23,
                qup3_se0_01, qup3_se0_23, qup3_se1, qup3_se2, qup3_se3,
                qup3_se4, qup3_se5, qup4_se0, qup4_se1, qup4_se2, qup4_se3_01,
                qup4_se3_23, qup4_se3_l3, qup4_se4_01, qup4_se4_23, qup4_se4_l3,
                rng_rosc, sd_write_protect, sdc4_clk, sdc4_cmd, sdc4_data,
                sys_throttle, tb_trig_sdc, tmess_rng, tsense_clm, tsense_pwm,
                uim0, uim1, usb0_hs, usb_phy, vfr, vsense_trigger_mirnat,
                wcn_sw_ctrl ]

    required:
      - pins

required:
  - compatible
  - reg

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    tlmm: pinctrl@f100000 {
        compatible = "qcom,hawi-tlmm";
        reg = <0x0f100000 0x300000>;
        interrupts = <GIC_ESPI 272 IRQ_TYPE_LEVEL_HIGH>;
        gpio-controller;
        #gpio-cells = <2>;
        gpio-ranges = <&tlmm 0 0 227>;
        interrupt-controller;
        #interrupt-cells = <2>;

        qup-uart7-state {
          pins = "gpio62", "gpio63";
          function = "qup1_se7";
        };
    };
...