Documentation/devicetree/bindings/phy/spacemit,k1-combo-phy.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/spacemit,k1-combo-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: SpacemiT K1 PCIe/USB3 Combo PHY

maintainers:
  - Alex Elder <elder@riscstar.com>

description: >
  Of the three PHYs on the SpacemiT K1 SoC capable of being used for
  PCIe, one is a combo PHY that can also be configured for use by a
  USB 3 controller.  Using PCIe or USB 3 is a board design decision.

  The combo PHY is also the only PCIe PHY that is able to determine
  PCIe calibration values to use, and this must be determined before
  the other two PCIe PHYs can be used.  This calibration must be
  performed with the combo PHY in PCIe mode, and is this is done
  when the combo PHY is probed.

  The combo PHY uses an external oscillator as a reference clock.
  During normal operation, the PCIe or USB port driver is responsible
  for ensuring all other clocks needed by a PHY are enabled, and all
  resets affecting the PHY are deasserted.  However, for the combo
  PHY to perform calibration independent of whether it's later used
  for PCIe or USB, all PCIe mode clocks and resets must be defined.

properties:
  compatible:
    const: spacemit,k1-combo-phy

  reg:
    items:
      - description: PHY control registers

  clocks:
    items:
      - description: External oscillator used by the PHY PLL
      - description: DWC PCIe Data Bus Interface (DBI) clock
      - description: DWC PCIe application AXI-bus Master interface clock
      - description: DWC PCIe application AXI-bus slave interface clock

  clock-names:
    items:
      - const: refclk
      - const: dbi
      - const: mstr
      - const: slv

  resets:
    items:
      - description: PHY reset; remains deasserted after initialization
      - description: DWC PCIe Data Bus Interface (DBI) reset
      - description: DWC PCIe application AXI-bus Master interface reset
      - description: DWC PCIe application AXI-bus slave interface reset

  reset-names:
    items:
      - const: phy
      - const: dbi
      - const: mstr
      - const: slv

  spacemit,apmu:
    description:
      A phandle that refers to the APMU system controller, whose
      regmap is used in setting the mode
    $ref: /schemas/types.yaml#/definitions/phandle

  "#phy-cells":
    const: 1
    description:
      The argument value (PHY_TYPE_PCIE or PHY_TYPE_USB3) determines
      whether the PHY operates in PCIe or USB3 mode.

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - resets
  - reset-names
  - spacemit,apmu
  - "#phy-cells"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/spacemit,k1-syscon.h>
    phy@c0b10000 {
        compatible = "spacemit,k1-combo-phy";
        reg = <0xc0b10000 0x1000>;
        clocks = <&vctcxo_24m>,
                 <&syscon_apmu CLK_PCIE0_DBI>,
                 <&syscon_apmu CLK_PCIE0_MASTER>,
                 <&syscon_apmu CLK_PCIE0_SLAVE>;
        clock-names = "refclk",
                      "dbi",
                      "mstr",
                      "slv";
        resets = <&syscon_apmu RESET_PCIE0_GLOBAL>,
                 <&syscon_apmu RESET_PCIE0_DBI>,
                 <&syscon_apmu RESET_PCIE0_MASTER>,
                 <&syscon_apmu RESET_PCIE0_SLAVE>;
        reset-names = "phy",
                      "dbi",
                      "mstr",
                      "slv";
        spacemit,apmu = <&syscon_apmu>;
        #phy-cells = <1>;
    };