Documentation/devicetree/bindings/pci/qcom,pcie-sdm845.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/qcom,pcie-sdm845.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SDM845 PCI Express Root Complex

maintainers:
  - Bjorn Andersson <andersson@kernel.org>
  - Manivannan Sadhasivam <mani@kernel.org>

properties:
  compatible:
    enum:
      - qcom,pcie-sdm845

  reg:
    minItems: 4
    maxItems: 5

  reg-names:
    minItems: 4
    items:
      - const: parf
      - const: dbi
      - const: elbi
      - const: config
      - const: mhi

  clocks:
    minItems: 7
    maxItems: 8

  clock-names:
    minItems: 7
    items:
      - const: pipe
      - const: aux
      - const: cfg
      - const: bus_master # Master AXI clock
      - const: bus_slave # Slave AXI clock
      - const: slave_q2a
      - enum: [ ref, tbu ]
      - const: tbu

  interrupts:
    minItems: 8
    maxItems: 9

  interrupt-names:
    minItems: 8
    items:
      - const: msi0
      - const: msi1
      - const: msi2
      - const: msi3
      - const: msi4
      - const: msi5
      - const: msi6
      - const: msi7
      - const: global

  resets:
    maxItems: 1

  reset-names:
    items:
      - const: pci

required:
  - power-domains
  - resets
  - reset-names

allOf:
  - $ref: qcom,pcie-common.yaml#

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        pcie@1c00000 {
            compatible = "qcom,pcie-sdm845";
            reg = <0x0 0x01c00000 0x0 0x2000>,
                  <0x0 0x60000000 0x0 0xf1d>,
                  <0x0 0x60000f20 0x0 0xa8>,
                  <0x0 0x60100000 0x0 0x100000>,
                  <0x0 0x01c07000 0x0 0x1000>;
            reg-names = "parf", "dbi", "elbi", "config", "mhi";
            ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
                     <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0xd00000>;

            device_type = "pci";
            linux,pci-domain = <0>;
            bus-range = <0x00 0xff>;
            num-lanes = <1>;

            #address-cells = <3>;
            #size-cells = <2>;

            clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
                     <&gcc GCC_PCIE_0_AUX_CLK>,
                     <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
                     <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
                     <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
                     <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
                     <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
            clock-names = "pipe",
                          "aux",
                          "cfg",
                          "bus_master",
                          "bus_slave",
                          "slave_q2a",
                          "tbu";

            interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
            interrupt-names = "msi0",
                              "msi1",
                              "msi2",
                              "msi3",
                              "msi4",
                              "msi5",
                              "msi6",
                              "msi7",
                              "global";
            #interrupt-cells = <1>;
            interrupt-map-mask = <0 0 0 0x7>;
            interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
                            <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
                            <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
                            <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */

            iommu-map = <0x0 &apps_smmu 0x1c10 0x1>,
                        <0x100 &apps_smmu 0x1c11 0x1>,
                        <0x200 &apps_smmu 0x1c12 0x1>,
                        <0x300 &apps_smmu 0x1c13 0x1>,
                        <0x400 &apps_smmu 0x1c14 0x1>,
                        <0x500 &apps_smmu 0x1c15 0x1>,
                        <0x600 &apps_smmu 0x1c16 0x1>,
                        <0x700 &apps_smmu 0x1c17 0x1>,
                        <0x800 &apps_smmu 0x1c18 0x1>,
                        <0x900 &apps_smmu 0x1c19 0x1>,
                        <0xa00 &apps_smmu 0x1c1a 0x1>,
                        <0xb00 &apps_smmu 0x1c1b 0x1>,
                        <0xc00 &apps_smmu 0x1c1c 0x1>,
                        <0xd00 &apps_smmu 0x1c1d 0x1>,
                        <0xe00 &apps_smmu 0x1c1e 0x1>,
                        <0xf00 &apps_smmu 0x1c1f 0x1>;

            power-domains = <&gcc PCIE_0_GDSC>;

            phys = <&pcie0_phy>;
            phy-names = "pciephy";

            resets = <&gcc GCC_PCIE_0_BCR>;
            reset-names = "pci";

            perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
            wake-gpios = <&tlmm 134 GPIO_ACTIVE_HIGH>;

            vddpe-3v3-supply = <&pcie0_3p3v_dual>;

            pcie@0 {
                device_type = "pci";
                reg = <0x0 0x0 0x0 0x0 0x0>;
                bus-range = <0x01 0xff>;

                #address-cells = <3>;
                #size-cells = <2>;
                ranges;
            };
        };
    };