Documentation/devicetree/bindings/pci/qcom,pcie-ipq4019.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/qcom,pcie-ipq4019.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm IPQ4019 PCI Express Root Complex

maintainers:
  - Bjorn Andersson <andersson@kernel.org>
  - Manivannan Sadhasivam <mani@kernel.org>

properties:
  compatible:
    enum:
      - qcom,pcie-ipq4019

  reg:
    maxItems: 4

  reg-names:
    items:
      - const: dbi
      - const: elbi
      - const: parf
      - const: config

  clocks:
    maxItems: 3

  clock-names:
    items:
      - const: aux
      - const: master_bus # Master AXI clock
      - const: slave_bus # Slave AXI clock

  interrupts:
    maxItems: 1

  interrupt-names:
    items:
      - const: msi

  resets:
    maxItems: 12

  reset-names:
    items:
      - const: axi_m # AXI master reset
      - const: axi_s # AXI slave reset
      - const: pipe
      - const: axi_m_vmid
      - const: axi_s_xpu
      - const: parf
      - const: phy
      - const: axi_m_sticky # AXI master sticky reset
      - const: pipe_sticky
      - const: pwr
      - const: ahb
      - const: phy_ahb

required:
  - resets
  - reset-names

allOf:
  - $ref: qcom,pcie-common.yaml#

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    pcie@40000000 {
        compatible = "qcom,pcie-ipq4019";
        reg = <0x40000000 0xf1d>,
              <0x40000f20 0xa8>,
              <0x80000 0x2000>,
              <0x40100000 0x1000>;
        reg-names = "dbi", "elbi", "parf", "config";
        ranges = <0x81000000 0x0 0x00000000 0x40200000 0x0 0x00100000>,
                 <0x82000000 0x0 0x40300000 0x40300000 0x0 0x00d00000>;

        device_type = "pci";
        linux,pci-domain = <0>;
        bus-range = <0x00 0xff>;
        num-lanes = <1>;
        #address-cells = <3>;
        #size-cells = <2>;

        clocks = <&gcc GCC_PCIE_AHB_CLK>,
                 <&gcc GCC_PCIE_AXI_M_CLK>,
                 <&gcc GCC_PCIE_AXI_S_CLK>;
        clock-names = "aux",
                      "master_bus",
                      "slave_bus";

        interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-names = "msi";
        #interrupt-cells = <1>;
        interrupt-map-mask = <0 0 0 0x7>;
        interrupt-map = <0 0 0 1 &intc GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
                        <0 0 0 2 &intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
                        <0 0 0 3 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
                        <0 0 0 4 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */

        resets = <&gcc PCIE_AXI_M_ARES>,
                 <&gcc PCIE_AXI_S_ARES>,
                 <&gcc PCIE_PIPE_ARES>,
                 <&gcc PCIE_AXI_M_VMIDMT_ARES>,
                 <&gcc PCIE_AXI_S_XPU_ARES>,
                 <&gcc PCIE_PARF_XPU_ARES>,
                 <&gcc PCIE_PHY_ARES>,
                 <&gcc PCIE_AXI_M_STICKY_ARES>,
                 <&gcc PCIE_PIPE_STICKY_ARES>,
                 <&gcc PCIE_PWR_ARES>,
                 <&gcc PCIE_AHB_ARES>,
                 <&gcc PCIE_PHY_AHB_ARES>;
        reset-names = "axi_m",
                      "axi_s",
                      "pipe",
                      "axi_m_vmid",
                      "axi_s_xpu",
                      "parf",
                      "phy",
                      "axi_m_sticky",
                      "pipe_sticky",
                      "pwr",
                      "ahb",
                      "phy_ahb";

        perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;

        pcie@0 {
            device_type = "pci";
            reg = <0x0 0x0 0x0 0x0 0x0>;
            bus-range = <0x01 0xff>;

            #address-cells = <3>;
            #size-cells = <2>;
            ranges;
        };
    };