Documentation/devicetree/bindings/mmc/cdns,sd6hc.yaml

# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/cdns,sd6hc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Cadence SD6HC SD/SDIO/eMMC Host Controller

maintainers:
  - Tanmay Kathpalia <tanmay.kathpalia@altera.com>

description:
  Cadence SD6HC is a sixth-generation SD/SDIO/eMMC host controller with an
  interface to a Cadence Combo PHY. The controller has separate card interface
  and bus interface clock domains.

properties:
  compatible:
    items:
      - const: altr,agilex5-sd6hc
      - const: cdns,sd6hc

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: card interface unit (CIU / SDMCLK) clock
      - description: bus interface unit (BIU) clock

  clock-names:
    items:
      - const: ciu
      - const: biu

  resets:
    items:
      - description: SDHC controller reset
      - description: Combo PHY reset
      - description: SDMMC OCP/AXI reset

  reset-names:
    items:
      - const: sdhc-reset
      - const: combophy
      - const: sdmmc-ocp

  iommus:
    maxItems: 1

  dma-coherent: true

  cdns,iocell-input-delay-ps:
    description:
      Input delay across the IO cells, used for SD6HC PHY timing calculations.
    minimum: 0
    maximum: 20000
    default: 2500

  cdns,iocell-output-delay-ps:
    description:
      Output delay across the IO cells, used for SD6HC PHY timing calculations.
    minimum: 0
    maximum: 20000
    default: 2500

  cdns,delay-element-ps:
    description:
      DLL delay element size, used for SD6HC PHY timing calculations.
    minimum: 1
    maximum: 1000
    default: 24

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - resets
  - reset-names

allOf:
  - $ref: sdhci-common.yaml#

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    mmc@10808000 {
        compatible = "altr,agilex5-sd6hc", "cdns,sd6hc";
        reg = <0x10808000 0x1000>;
        interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&clkmgr 0>, <&clkmgr 1>;
        clock-names = "ciu", "biu";
        resets = <&rst 0>, <&rst 1>, <&rst 2>;
        reset-names = "sdhc-reset", "combophy", "sdmmc-ocp";
        iommus = <&smmu 5>;
        dma-coherent;
    };