Documentation/devicetree/bindings/media/snps,dw-hdmi-rx.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Device Tree bindings for Synopsys DesignWare HDMI RX Controller

---
$id: http://devicetree.org/schemas/media/snps,dw-hdmi-rx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Synopsys DesignWare HDMI RX Controller

maintainers:
  - Dmitry Osipenko <dmitry.osipenko@collabora.com>

description:
  Synopsys DesignWare HDMI Input Controller preset on RK3588 SoCs
  allowing devices to receive and decode high-resolution video streams
  from external sources like media players, cameras, laptops, etc.

properties:
  compatible:
    items:
      - const: rockchip,rk3588-hdmirx-ctrler
      - const: snps,dw-hdmi-rx

  reg:
    maxItems: 1

  interrupts:
    maxItems: 3

  interrupt-names:
    items:
      - const: cec
      - const: hdmi
      - const: dma

  clocks:
    maxItems: 7

  clock-names:
    items:
      - const: aclk
      - const: audio
      - const: cr_para
      - const: pclk
      - const: ref
      - const: hclk_s_hdmirx
      - const: hclk_vo1

  power-domains:
    maxItems: 1

  resets:
    maxItems: 4

  reset-names:
    items:
      - const: axi
      - const: apb
      - const: ref
      - const: biu

  memory-region:
    maxItems: 1

  hpd-gpios:
    description: GPIO specifier for HPD.
    maxItems: 1

  rockchip,grf:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      The phandle of the syscon node for the general register file
      containing HDMIRX PHY status bits.

  rockchip,vo1-grf:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      The phandle of the syscon node for the Video Output GRF register
      to enable EDID transfer through SDAIN and SCLIN.

required:
  - compatible
  - reg
  - interrupts
  - interrupt-names
  - clocks
  - clock-names
  - power-domains
  - resets
  - pinctrl-0
  - hpd-gpios

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/rockchip,rk3588-cru.h>
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/power/rk3588-power.h>
    #include <dt-bindings/reset/rockchip,rk3588-cru.h>
    hdmi_receiver: hdmi-receiver@fdee0000 {
      compatible = "rockchip,rk3588-hdmirx-ctrler", "snps,dw-hdmi-rx";
      reg = <0xfdee0000 0x6000>;
      interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH 0>,
                   <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH 0>,
                   <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH 0>;
      interrupt-names = "cec", "hdmi", "dma";
      clocks = <&cru ACLK_HDMIRX>,
               <&cru CLK_HDMIRX_AUD>,
               <&cru CLK_CR_PARA>,
               <&cru PCLK_HDMIRX>,
               <&cru CLK_HDMIRX_REF>,
               <&cru PCLK_S_HDMIRX>,
               <&cru HCLK_VO1>;
      clock-names = "aclk",
                    "audio",
                    "cr_para",
                    "pclk",
                    "ref",
                    "hclk_s_hdmirx",
                    "hclk_vo1";
      power-domains = <&power RK3588_PD_VO1>;
      resets = <&cru SRST_A_HDMIRX>, <&cru SRST_P_HDMIRX>,
               <&cru SRST_HDMIRX_REF>, <&cru SRST_A_HDMIRX_BIU>;
      reset-names = "axi", "apb", "ref", "biu";
      memory-region = <&hdmi_receiver_cma>;
      pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_5v_detection>;
      pinctrl-names = "default";
      hpd-gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;
    };