| # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/media/qcom,sm6350-camss.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: Qualcomm SM6350 Camera Subsystem (CAMSS) |
| |
| maintainers: |
| - Luca Weiss <luca.weiss@fairphone.com> |
| |
| description: |
| The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. |
| |
| properties: |
| compatible: |
| const: qcom,sm6350-camss |
| |
| reg: |
| maxItems: 24 |
| |
| reg-names: |
| items: |
| - const: csid0 |
| - const: csid1 |
| - const: csid2 |
| - const: csid_lite |
| - const: csiphy0 |
| - const: csiphy1 |
| - const: csiphy2 |
| - const: csiphy3 |
| - const: vfe0 |
| - const: vfe1 |
| - const: vfe2 |
| - const: vfe_lite |
| - const: a5_csr |
| - const: a5_qgic |
| - const: a5_sierra |
| - const: bps |
| - const: camnoc |
| - const: core_top_csr_tcsr |
| - const: cpas_cdm |
| - const: cpas_top |
| - const: ipe |
| - const: jpeg_dma |
| - const: jpeg_enc |
| - const: lrme |
| |
| clocks: |
| maxItems: 39 |
| |
| clock-names: |
| items: |
| - const: cam_axi |
| - const: soc_ahb |
| - const: camnoc_axi |
| - const: core_ahb |
| - const: cpas_ahb |
| - const: csiphy0 |
| - const: csiphy0_timer |
| - const: csiphy1 |
| - const: csiphy1_timer |
| - const: csiphy2 |
| - const: csiphy2_timer |
| - const: csiphy3 |
| - const: csiphy3_timer |
| - const: vfe0_axi |
| - const: vfe0 |
| - const: vfe0_cphy_rx |
| - const: vfe0_csid |
| - const: vfe1_axi |
| - const: vfe1 |
| - const: vfe1_cphy_rx |
| - const: vfe1_csid |
| - const: vfe2_axi |
| - const: vfe2 |
| - const: vfe2_cphy_rx |
| - const: vfe2_csid |
| - const: vfe_lite |
| - const: vfe_lite_cphy_rx |
| - const: vfe_lite_csid |
| - const: bps |
| - const: bps_ahb |
| - const: bps_areg |
| - const: bps_axi |
| - const: icp |
| - const: ipe0 |
| - const: ipe0_ahb |
| - const: ipe0_areg |
| - const: ipe0_axi |
| - const: jpeg |
| - const: lrme |
| |
| interrupts: |
| maxItems: 18 |
| |
| interrupt-names: |
| items: |
| - const: csid0 |
| - const: csid1 |
| - const: csid2 |
| - const: csid_lite |
| - const: csiphy0 |
| - const: csiphy1 |
| - const: csiphy2 |
| - const: csiphy3 |
| - const: vfe0 |
| - const: vfe1 |
| - const: vfe2 |
| - const: vfe_lite |
| - const: a5 |
| - const: cpas |
| - const: cpas_cdm |
| - const: jpeg_dma |
| - const: jpeg_enc |
| - const: lrme |
| |
| interconnects: |
| maxItems: 4 |
| |
| interconnect-names: |
| items: |
| - const: ahb |
| - const: hf_mnoc |
| - const: sf_mnoc |
| - const: sf_icp_mnoc |
| |
| iommus: |
| maxItems: 14 |
| |
| power-domains: |
| maxItems: 6 |
| |
| power-domain-names: |
| items: |
| - const: ife0 |
| - const: ife1 |
| - const: ife2 |
| - const: top |
| - const: bps |
| - const: ipe |
| |
| vdd-csiphy0-0p9-supply: |
| description: |
| Phandle to a 0.9V regulator supply to CSIPHY0. |
| |
| vdd-csiphy0-1p25-supply: |
| description: |
| Phandle to a 1.25V regulator supply to CSIPHY0. |
| |
| vdd-csiphy1-0p9-supply: |
| description: |
| Phandle to a 0.9V regulator supply to CSIPHY1. |
| |
| vdd-csiphy1-1p25-supply: |
| description: |
| Phandle to a 1.25V regulator supply to CSIPHY1. |
| |
| vdd-csiphy2-0p9-supply: |
| description: |
| Phandle to a 0.9V regulator supply to CSIPHY2. |
| |
| vdd-csiphy2-1p25-supply: |
| description: |
| Phandle to a 1.25V regulator supply to CSIPHY2. |
| |
| vdd-csiphy3-0p9-supply: |
| description: |
| Phandle to a 0.9V regulator supply to CSIPHY3. |
| |
| vdd-csiphy3-1p25-supply: |
| description: |
| Phandle to a 1.25V regulator supply to CSIPHY3. |
| |
| ports: |
| $ref: /schemas/graph.yaml#/properties/ports |
| |
| description: |
| CSI input ports. |
| |
| patternProperties: |
| "^port@[0-3]$": |
| $ref: /schemas/graph.yaml#/$defs/port-base |
| unevaluatedProperties: false |
| |
| description: |
| Input port for receiving CSI data from a CSIPHY. |
| |
| properties: |
| endpoint: |
| $ref: video-interfaces.yaml# |
| unevaluatedProperties: false |
| |
| properties: |
| data-lanes: |
| minItems: 1 |
| maxItems: 4 |
| |
| bus-type: |
| enum: |
| - 1 # MEDIA_BUS_TYPE_CSI2_CPHY |
| - 4 # MEDIA_BUS_TYPE_CSI2_DPHY |
| |
| required: |
| - data-lanes |
| |
| required: |
| - compatible |
| - reg |
| - reg-names |
| - clocks |
| - clock-names |
| - interrupts |
| - interrupt-names |
| - interconnects |
| - interconnect-names |
| - iommus |
| - power-domains |
| - power-domain-names |
| - ports |
| |
| additionalProperties: false |
| |
| examples: |
| - | |
| #include <dt-bindings/clock/qcom,gcc-sm6350.h> |
| #include <dt-bindings/clock/qcom,sm6350-camcc.h> |
| #include <dt-bindings/interconnect/qcom,icc.h> |
| #include <dt-bindings/interconnect/qcom,sm6350.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/media/video-interfaces.h> |
| #include <dt-bindings/power/qcom-rpmpd.h> |
| |
| soc { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| isp@acb3000 { |
| compatible = "qcom,sm6350-camss"; |
| |
| reg = <0x0 0x0acb3000 0x0 0x1000>, |
| <0x0 0x0acba000 0x0 0x1000>, |
| <0x0 0x0acc1000 0x0 0x1000>, |
| <0x0 0x0acc8000 0x0 0x1000>, |
| <0x0 0x0ac65000 0x0 0x1000>, |
| <0x0 0x0ac66000 0x0 0x1000>, |
| <0x0 0x0ac67000 0x0 0x1000>, |
| <0x0 0x0ac68000 0x0 0x1000>, |
| <0x0 0x0acaf000 0x0 0x4000>, |
| <0x0 0x0acb6000 0x0 0x4000>, |
| <0x0 0x0acbd000 0x0 0x4000>, |
| <0x0 0x0acc4000 0x0 0x4000>, |
| <0x0 0x0ac18000 0x0 0x3000>, |
| <0x0 0x0ac00000 0x0 0x6000>, |
| <0x0 0x0ac10000 0x0 0x8000>, |
| <0x0 0x0ac6f000 0x0 0x8000>, |
| <0x0 0x0ac42000 0x0 0x4600>, |
| <0x0 0x01fc0000 0x0 0x40000>, |
| <0x0 0x0ac48000 0x0 0x1000>, |
| <0x0 0x0ac40000 0x0 0x1000>, |
| <0x0 0x0ac87000 0x0 0xa000>, |
| <0x0 0x0ac52000 0x0 0x4000>, |
| <0x0 0x0ac4e000 0x0 0x4000>, |
| <0x0 0x0ac6b000 0x0 0xa00>; |
| reg-names = "csid0", |
| "csid1", |
| "csid2", |
| "csid_lite", |
| "csiphy0", |
| "csiphy1", |
| "csiphy2", |
| "csiphy3", |
| "vfe0", |
| "vfe1", |
| "vfe2", |
| "vfe_lite", |
| "a5_csr", |
| "a5_qgic", |
| "a5_sierra", |
| "bps", |
| "camnoc", |
| "core_top_csr_tcsr", |
| "cpas_cdm", |
| "cpas_top", |
| "ipe", |
| "jpeg_dma", |
| "jpeg_enc", |
| "lrme"; |
| |
| clocks = <&gcc GCC_CAMERA_AXI_CLK>, |
| <&camcc CAMCC_SOC_AHB_CLK>, |
| <&camcc CAMCC_CAMNOC_AXI_CLK>, |
| <&camcc CAMCC_CORE_AHB_CLK>, |
| <&camcc CAMCC_CPAS_AHB_CLK>, |
| <&camcc CAMCC_CSIPHY0_CLK>, |
| <&camcc CAMCC_CSI0PHYTIMER_CLK>, |
| <&camcc CAMCC_CSIPHY1_CLK>, |
| <&camcc CAMCC_CSI1PHYTIMER_CLK>, |
| <&camcc CAMCC_CSIPHY2_CLK>, |
| <&camcc CAMCC_CSI2PHYTIMER_CLK>, |
| <&camcc CAMCC_CSIPHY3_CLK>, |
| <&camcc CAMCC_CSI3PHYTIMER_CLK>, |
| <&camcc CAMCC_IFE_0_AXI_CLK>, |
| <&camcc CAMCC_IFE_0_CLK>, |
| <&camcc CAMCC_IFE_0_CPHY_RX_CLK>, |
| <&camcc CAMCC_IFE_0_CSID_CLK>, |
| <&camcc CAMCC_IFE_1_AXI_CLK>, |
| <&camcc CAMCC_IFE_1_CLK>, |
| <&camcc CAMCC_IFE_1_CPHY_RX_CLK>, |
| <&camcc CAMCC_IFE_1_CSID_CLK>, |
| <&camcc CAMCC_IFE_2_AXI_CLK>, |
| <&camcc CAMCC_IFE_2_CLK>, |
| <&camcc CAMCC_IFE_2_CPHY_RX_CLK>, |
| <&camcc CAMCC_IFE_2_CSID_CLK>, |
| <&camcc CAMCC_IFE_LITE_CLK>, |
| <&camcc CAMCC_IFE_LITE_CPHY_RX_CLK>, |
| <&camcc CAMCC_IFE_LITE_CSID_CLK>, |
| <&camcc CAMCC_BPS_CLK>, |
| <&camcc CAMCC_BPS_AHB_CLK>, |
| <&camcc CAMCC_BPS_AREG_CLK>, |
| <&camcc CAMCC_BPS_AXI_CLK>, |
| <&camcc CAMCC_ICP_CLK>, |
| <&camcc CAMCC_IPE_0_CLK>, |
| <&camcc CAMCC_IPE_0_AHB_CLK>, |
| <&camcc CAMCC_IPE_0_AREG_CLK>, |
| <&camcc CAMCC_IPE_0_AXI_CLK>, |
| <&camcc CAMCC_JPEG_CLK>, |
| <&camcc CAMCC_LRME_CLK>; |
| clock-names = "cam_axi", |
| "soc_ahb", |
| "camnoc_axi", |
| "core_ahb", |
| "cpas_ahb", |
| "csiphy0", |
| "csiphy0_timer", |
| "csiphy1", |
| "csiphy1_timer", |
| "csiphy2", |
| "csiphy2_timer", |
| "csiphy3", |
| "csiphy3_timer", |
| "vfe0_axi", |
| "vfe0", |
| "vfe0_cphy_rx", |
| "vfe0_csid", |
| "vfe1_axi", |
| "vfe1", |
| "vfe1_cphy_rx", |
| "vfe1_csid", |
| "vfe2_axi", |
| "vfe2", |
| "vfe2_cphy_rx", |
| "vfe2_csid", |
| "vfe_lite", |
| "vfe_lite_cphy_rx", |
| "vfe_lite_csid", |
| "bps", |
| "bps_ahb", |
| "bps_areg", |
| "bps_axi", |
| "icp", |
| "ipe0", |
| "ipe0_ahb", |
| "ipe0_areg", |
| "ipe0_axi", |
| "jpeg", |
| "lrme"; |
| |
| interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 717 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 473 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 461 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 718 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 472 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 459 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 475 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 474 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 476 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "csid0", |
| "csid1", |
| "csid2", |
| "csid_lite", |
| "csiphy0", |
| "csiphy1", |
| "csiphy2", |
| "csiphy3", |
| "vfe0", |
| "vfe1", |
| "vfe2", |
| "vfe_lite", |
| "a5", |
| "cpas", |
| "cpas_cdm", |
| "jpeg_dma", |
| "jpeg_enc", |
| "lrme"; |
| |
| interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY |
| &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, |
| <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS |
| &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, |
| <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS |
| &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, |
| <&mmss_noc MASTER_CAMNOC_ICP QCOM_ICC_TAG_ALWAYS |
| &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; |
| interconnect-names = "ahb", |
| "hf_mnoc", |
| "sf_mnoc", |
| "sf_icp_mnoc"; |
| |
| iommus = <&apps_smmu 0x820 0xc0>, |
| <&apps_smmu 0x840 0x0>, |
| <&apps_smmu 0x860 0xc0>, |
| <&apps_smmu 0x880 0x0>, |
| <&apps_smmu 0xc40 0x20>, |
| <&apps_smmu 0xc60 0x20>, |
| <&apps_smmu 0xc80 0x0>, |
| <&apps_smmu 0xca2 0x0>, |
| <&apps_smmu 0xcc0 0x20>, |
| <&apps_smmu 0xce0 0x20>, |
| <&apps_smmu 0xd00 0x20>, |
| <&apps_smmu 0xd20 0x20>, |
| <&apps_smmu 0xd40 0x20>, |
| <&apps_smmu 0xd60 0x20>; |
| |
| power-domains = <&camcc IFE_0_GDSC>, |
| <&camcc IFE_1_GDSC>, |
| <&camcc IFE_2_GDSC>, |
| <&camcc TITAN_TOP_GDSC>, |
| <&camcc BPS_GDSC>, |
| <&camcc IPE_0_GDSC>; |
| power-domain-names = "ife0", |
| "ife1", |
| "ife2", |
| "top", |
| "bps", |
| "ipe"; |
| |
| vdd-csiphy0-0p9-supply = <&vreg_l18a>; |
| vdd-csiphy0-1p25-supply = <&vreg_l22a>; |
| vdd-csiphy1-0p9-supply = <&vreg_l18a>; |
| vdd-csiphy1-1p25-supply = <&vreg_l22a>; |
| vdd-csiphy2-0p9-supply = <&vreg_l18a>; |
| vdd-csiphy2-1p25-supply = <&vreg_l22a>; |
| vdd-csiphy3-0p9-supply = <&vreg_l18a>; |
| vdd-csiphy3-1p25-supply = <&vreg_l22a>; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| |
| csiphy0_ep: endpoint { |
| data-lanes = <0 1 2 3>; |
| bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>; |
| remote-endpoint = <&sensor_ep>; |
| }; |
| }; |
| }; |
| }; |
| }; |
