| # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-pixel-engine.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: Freescale i.MX8qxp Display Controller Pixel Engine |
| |
| description: |
| All Processing Units that operate in the AXI bus clock domain. Pixel |
| pipelines have the ability to stall when a destination is busy. Implements |
| all communication to memory resources and most of the image processing |
| functions. Interconnection of Processing Units is re-configurable. |
| |
| maintainers: |
| - Liu Ying <victor.liu@nxp.com> |
| |
| properties: |
| compatible: |
| const: fsl,imx8qxp-dc-pixel-engine |
| |
| reg: |
| maxItems: 1 |
| |
| clocks: |
| maxItems: 1 |
| |
| "#address-cells": |
| const: 1 |
| |
| "#size-cells": |
| const: 1 |
| |
| ranges: true |
| |
| patternProperties: |
| "^blit-engine@[0-9a-f]+$": |
| type: object |
| additionalProperties: true |
| |
| properties: |
| compatible: |
| const: fsl,imx8qxp-dc-blit-engine |
| |
| "^constframe@[0-9a-f]+$": |
| type: object |
| additionalProperties: true |
| |
| properties: |
| compatible: |
| const: fsl,imx8qxp-dc-constframe |
| |
| "^extdst@[0-9a-f]+$": |
| type: object |
| additionalProperties: true |
| |
| properties: |
| compatible: |
| const: fsl,imx8qxp-dc-extdst |
| |
| "^fetchdecode@[0-9a-f]+$": |
| type: object |
| additionalProperties: true |
| |
| properties: |
| compatible: |
| const: fsl,imx8qxp-dc-fetchdecode |
| |
| "^fetcheco@[0-9a-f]+$": |
| type: object |
| additionalProperties: true |
| |
| properties: |
| compatible: |
| const: fsl,imx8qxp-dc-fetcheco |
| |
| "^fetchlayer@[0-9a-f]+$": |
| type: object |
| additionalProperties: true |
| |
| properties: |
| compatible: |
| const: fsl,imx8qxp-dc-fetchlayer |
| |
| "^fetchwarp@[0-9a-f]+$": |
| type: object |
| additionalProperties: true |
| |
| properties: |
| compatible: |
| const: fsl,imx8qxp-dc-fetchwarp |
| |
| "^hscaler@[0-9a-f]+$": |
| type: object |
| additionalProperties: true |
| |
| properties: |
| compatible: |
| const: fsl,imx8qxp-dc-hscaler |
| |
| "^layerblend@[0-9a-f]+$": |
| type: object |
| additionalProperties: true |
| |
| properties: |
| compatible: |
| const: fsl,imx8qxp-dc-layerblend |
| |
| "^matrix@[0-9a-f]+$": |
| type: object |
| additionalProperties: true |
| |
| properties: |
| compatible: |
| const: fsl,imx8qxp-dc-matrix |
| |
| "^safety@[0-9a-f]+$": |
| type: object |
| additionalProperties: true |
| |
| properties: |
| compatible: |
| const: fsl,imx8qxp-dc-safety |
| |
| "^vscaler@[0-9a-f]+$": |
| type: object |
| additionalProperties: true |
| |
| properties: |
| compatible: |
| const: fsl,imx8qxp-dc-vscaler |
| |
| required: |
| - compatible |
| - reg |
| - clocks |
| - "#address-cells" |
| - "#size-cells" |
| - ranges |
| |
| additionalProperties: false |
| |
| examples: |
| - | |
| #include <dt-bindings/clock/imx8-lpcg.h> |
| |
| pixel-engine@56180800 { |
| compatible = "fsl,imx8qxp-dc-pixel-engine"; |
| reg = <0x56180800 0xac00>; |
| clocks = <&dc0_lpcg IMX_LPCG_CLK_5>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| constframe@56180960 { |
| compatible = "fsl,imx8qxp-dc-constframe"; |
| reg = <0x56180960 0xc>, <0x56184400 0x20>; |
| reg-names = "pec", "cfg"; |
| }; |
| |
| extdst@56180980 { |
| compatible = "fsl,imx8qxp-dc-extdst"; |
| reg = <0x56180980 0x1c>, <0x56184800 0x28>; |
| reg-names = "pec", "cfg"; |
| interrupt-parent = <&dc0_intc>; |
| interrupts = <3>, <4>, <5>; |
| interrupt-names = "shdload", "framecomplete", "seqcomplete"; |
| }; |
| |
| constframe@561809a0 { |
| compatible = "fsl,imx8qxp-dc-constframe"; |
| reg = <0x561809a0 0xc>, <0x56184c00 0x20>; |
| reg-names = "pec", "cfg"; |
| }; |
| |
| extdst@561809c0 { |
| compatible = "fsl,imx8qxp-dc-extdst"; |
| reg = <0x561809c0 0x1c>, <0x56185000 0x28>; |
| reg-names = "pec", "cfg"; |
| interrupt-parent = <&dc0_intc>; |
| interrupts = <6>, <7>, <8>; |
| interrupt-names = "shdload", "framecomplete", "seqcomplete"; |
| }; |
| |
| constframe@561809e0 { |
| compatible = "fsl,imx8qxp-dc-constframe"; |
| reg = <0x561809e0 0xc>, <0x56185400 0x20>; |
| reg-names = "pec", "cfg"; |
| }; |
| |
| extdst@56180a00 { |
| compatible = "fsl,imx8qxp-dc-extdst"; |
| reg = <0x56180a00 0x1c>, <0x56185800 0x28>; |
| reg-names = "pec", "cfg"; |
| interrupt-parent = <&dc0_intc>; |
| interrupts = <9>, <10>, <11>; |
| interrupt-names = "shdload", "framecomplete", "seqcomplete"; |
| }; |
| |
| constframe@56180a20 { |
| compatible = "fsl,imx8qxp-dc-constframe"; |
| reg = <0x56180a20 0xc>, <0x56185c00 0x20>; |
| reg-names = "pec", "cfg"; |
| }; |
| |
| extdst@56180a40 { |
| compatible = "fsl,imx8qxp-dc-extdst"; |
| reg = <0x56180a40 0x1c>, <0x56186000 0x28>; |
| reg-names = "pec", "cfg"; |
| interrupt-parent = <&dc0_intc>; |
| interrupts = <12>, <13>, <14>; |
| interrupt-names = "shdload", "framecomplete", "seqcomplete"; |
| }; |
| |
| fetchwarp@56180a60 { |
| compatible = "fsl,imx8qxp-dc-fetchwarp"; |
| reg = <0x56180a60 0x10>, <0x56186400 0x190>; |
| reg-names = "pec", "cfg"; |
| }; |
| |
| fetchlayer@56180ac0 { |
| compatible = "fsl,imx8qxp-dc-fetchlayer"; |
| reg = <0x56180ac0 0xc>, <0x56188400 0x404>; |
| reg-names = "pec", "cfg"; |
| }; |
| |
| layerblend@56180ba0 { |
| compatible = "fsl,imx8qxp-dc-layerblend"; |
| reg = <0x56180ba0 0x10>, <0x5618a400 0x20>; |
| reg-names = "pec", "cfg"; |
| }; |
| |
| layerblend@56180bc0 { |
| compatible = "fsl,imx8qxp-dc-layerblend"; |
| reg = <0x56180bc0 0x10>, <0x5618a800 0x20>; |
| reg-names = "pec", "cfg"; |
| }; |
| |
| layerblend@56180be0 { |
| compatible = "fsl,imx8qxp-dc-layerblend"; |
| reg = <0x56180be0 0x10>, <0x5618ac00 0x20>; |
| reg-names = "pec", "cfg"; |
| }; |
| |
| layerblend@56180c00 { |
| compatible = "fsl,imx8qxp-dc-layerblend"; |
| reg = <0x56180c00 0x10>, <0x5618b000 0x20>; |
| reg-names = "pec", "cfg"; |
| }; |
| }; |
