Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-command-sequencer.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-command-sequencer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale i.MX8qxp Display Controller Command Sequencer

description: |
  The Command Sequencer is designed to autonomously process command lists.
  By that it can load setups into the DC configuration and synchronize to
  hardware events.  This releases a system's CPU from workload, because it
  does not need to wait for certain events.  Also it simplifies SW architecture,
  because no interrupt handlers are required.  Setups are read via AXI bus,
  while write access to configuration registers occurs directly via an internal
  bus.  This saves bandwidth for the AXI interconnect and improves the system
  architecture in terms of safety aspects.

maintainers:
  - Liu Ying <victor.liu@nxp.com>

properties:
  compatible:
    const: fsl,imx8qxp-dc-command-sequencer

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  interrupts:
    maxItems: 5

  interrupt-names:
    items:
      - const: error
      - const: sw0
      - const: sw1
      - const: sw2
      - const: sw3

  sram:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: phandle pointing to the mmio-sram device node

required:
  - compatible
  - reg
  - clocks
  - interrupts
  - interrupt-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx8-lpcg.h>

    command-sequencer@56180400 {
        compatible = "fsl,imx8qxp-dc-command-sequencer";
        reg = <0x56180400 0x1a4>;
        clocks = <&dc0_lpcg IMX_LPCG_CLK_5>;
        interrupt-parent = <&dc0_intc>;
        interrupts = <36>, <37>, <38>, <39>, <40>;
        interrupt-names = "error", "sw0", "sw1", "sw2", "sw3";
    };