arch/arm64/boot/dts/ti/k3-am64-ti-ipc-firmware.dtsi

// SPDX-License-Identifier: GPL-2.0-only OR MIT
/**
 * Device Tree Source for enabling IPC using TI SDK firmware on AM64 SoCs
 *
 * Copyright (C) 2024-2025 Texas Instruments Incorporated - https://www.ti.com/
 */

&reserved_memory {
	main_r5fss0_core1_dma_memory_region: memory@a1000000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xa1000000 0x00 0x100000>;
		no-map;
	};

	main_r5fss0_core1_memory_region: memory@a1100000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xa1100000 0x00 0xf00000>;
		no-map;
	};

	main_r5fss1_core0_dma_memory_region: memory@a2000000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xa2000000 0x00 0x100000>;
		no-map;
	};

	main_r5fss1_core0_memory_region: memory@a2100000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xa2100000 0x00 0xf00000>;
		no-map;
	};

	main_r5fss1_core1_dma_memory_region: memory@a3000000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xa3000000 0x00 0x100000>;
		no-map;
	};

	main_r5fss1_core1_memory_region: memory@a3100000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xa3100000 0x00 0xf00000>;
		no-map;
	};

	mcu_m4fss_dma_memory_region: memory@a4000000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xa4000000 0x00 0x100000>;
		no-map;
	};

	mcu_m4fss_memory_region: memory@a4100000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xa4100000 0x00 0xf00000>;
		no-map;
	};

	rtos_ipc_memory_region: memory@a5000000 {
		reg = <0x00 0xa5000000 0x00 0x00800000>;
		alignment = <0x1000>;
		no-map;
	};
};

&mailbox0_cluster2 {
	status = "okay";

	mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
		ti,mbox-rx = <0 0 2>;
		ti,mbox-tx = <1 0 2>;
	};

	mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
		ti,mbox-rx = <2 0 2>;
		ti,mbox-tx = <3 0 2>;
	};
};

&mailbox0_cluster4 {
	status = "okay";

	mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
		ti,mbox-rx = <0 0 2>;
		ti,mbox-tx = <1 0 2>;
	};

	mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
		ti,mbox-rx = <2 0 2>;
		ti,mbox-tx = <3 0 2>;
	};
};

&mailbox0_cluster6 {
	status = "okay";

	mbox_m4_0: mbox-m4-0 {
		ti,mbox-rx = <0 0 2>;
		ti,mbox-tx = <1 0 2>;
	};
};

/* main_timer8 is used by r5f0-0 */
&main_timer8 {
	status = "reserved";
};

/* main_timer9 is used by r5f0-1 */
&main_timer9 {
	status = "reserved";
};

/* main_timer10 is used by r5f1-0 */
&main_timer10 {
	status = "reserved";
};

/* main_timer11 is used by r5f1-1 */
&main_timer11 {
	status = "reserved";
};

&main_r5fss0 {
	status = "okay";
};

&main_r5fss0_core0 {
	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
	memory-region = <&main_r5fss0_core0_dma_memory_region>,
			<&main_r5fss0_core0_memory_region>;
	status = "okay";
};

&main_r5fss0_core1 {
	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
	memory-region = <&main_r5fss0_core1_dma_memory_region>,
			<&main_r5fss0_core1_memory_region>;
	status = "okay";
};

&main_r5fss1 {
	status = "okay";
};

&main_r5fss1_core0 {
	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
	memory-region = <&main_r5fss1_core0_dma_memory_region>,
			<&main_r5fss1_core0_memory_region>;
	status = "okay";
};

&main_r5fss1_core1 {
	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
	memory-region = <&main_r5fss1_core1_dma_memory_region>,
			<&main_r5fss1_core1_memory_region>;
	status = "okay";
};

&mcu_m4fss {
	mboxes = <&mailbox0_cluster6 &mbox_m4_0>;
	memory-region = <&mcu_m4fss_dma_memory_region>,
			<&mcu_m4fss_memory_region>;
	status = "okay";
};