| // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| /* |
| * Device Tree Source for the RZ/G3E SoC |
| * |
| * Copyright (C) 2024 Renesas Electronics Corp. |
| */ |
| |
| #include <dt-bindings/clock/renesas,r9a09g047-cpg.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| |
| / { |
| compatible = "renesas,r9a09g047"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| interrupt-parent = <&gic>; |
| |
| audio_extal_clk: audio-clk { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| /* This value must be overridden by the board */ |
| clock-frequency = <0>; |
| }; |
| |
| /* |
| * The default cluster table is based on the assumption that the PLLCA55 clock |
| * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to |
| * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be |
| * clocked to 1.8GHz as well). The table below should be overridden in the board |
| * DTS based on the PLLCA55 clock frequency. |
| */ |
| cluster0_opp: opp-table-0 { |
| compatible = "operating-points-v2"; |
| |
| opp-1700000000 { |
| opp-hz = /bits/ 64 <1700000000>; |
| opp-microvolt = <900000>; |
| clock-latency-ns = <300000>; |
| }; |
| opp-850000000 { |
| opp-hz = /bits/ 64 <850000000>; |
| opp-microvolt = <800000>; |
| clock-latency-ns = <300000>; |
| }; |
| opp-425000000 { |
| opp-hz = /bits/ 64 <425000000>; |
| opp-microvolt = <800000>; |
| clock-latency-ns = <300000>; |
| }; |
| opp-212500000 { |
| opp-hz = /bits/ 64 <212500000>; |
| opp-microvolt = <800000>; |
| clock-latency-ns = <300000>; |
| opp-suspend; |
| }; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu0: cpu@0 { |
| compatible = "arm,cortex-a55"; |
| reg = <0>; |
| device_type = "cpu"; |
| next-level-cache = <&L3_CA55>; |
| enable-method = "psci"; |
| clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK0>; |
| #cooling-cells = <2>; |
| operating-points-v2 = <&cluster0_opp>; |
| }; |
| |
| cpu1: cpu@100 { |
| compatible = "arm,cortex-a55"; |
| reg = <0x100>; |
| device_type = "cpu"; |
| next-level-cache = <&L3_CA55>; |
| enable-method = "psci"; |
| clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK1>; |
| #cooling-cells = <2>; |
| operating-points-v2 = <&cluster0_opp>; |
| }; |
| |
| cpu2: cpu@200 { |
| compatible = "arm,cortex-a55"; |
| reg = <0x200>; |
| device_type = "cpu"; |
| next-level-cache = <&L3_CA55>; |
| enable-method = "psci"; |
| clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK2>; |
| #cooling-cells = <2>; |
| operating-points-v2 = <&cluster0_opp>; |
| }; |
| |
| cpu3: cpu@300 { |
| compatible = "arm,cortex-a55"; |
| reg = <0x300>; |
| device_type = "cpu"; |
| next-level-cache = <&L3_CA55>; |
| enable-method = "psci"; |
| clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK3>; |
| #cooling-cells = <2>; |
| operating-points-v2 = <&cluster0_opp>; |
| }; |
| |
| L3_CA55: cache-controller-0 { |
| compatible = "cache"; |
| cache-unified; |
| cache-size = <0x100000>; |
| cache-level = <3>; |
| }; |
| }; |
| |
| gpu_opp_table: opp-table-1 { |
| compatible = "operating-points-v2"; |
| |
| opp-630000000 { |
| opp-hz = /bits/ 64 <630000000>; |
| opp-microvolt = <800000>; |
| }; |
| |
| opp-315000000 { |
| opp-hz = /bits/ 64 <315000000>; |
| opp-microvolt = <800000>; |
| }; |
| |
| opp-157500000 { |
| opp-hz = /bits/ 64 <157500000>; |
| opp-microvolt = <800000>; |
| }; |
| |
| opp-78750000 { |
| opp-hz = /bits/ 64 <78750000>; |
| opp-microvolt = <800000>; |
| }; |
| |
| opp-19687500 { |
| opp-hz = /bits/ 64 <19687500>; |
| opp-microvolt = <800000>; |
| }; |
| }; |
| |
| psci { |
| compatible = "arm,psci-1.0", "arm,psci-0.2"; |
| method = "smc"; |
| }; |
| |
| qextal_clk: qextal-clk { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| /* This value must be overridden by the board */ |
| clock-frequency = <0>; |
| }; |
| |
| rtxin_clk: rtxin-clk { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| /* This value must be overridden by the board */ |
| clock-frequency = <0>; |
| }; |
| |
| soc: soc { |
| compatible = "simple-bus"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| icu: interrupt-controller@10400000 { |
| compatible = "renesas,r9a09g047-icu"; |
| reg = <0 0x10400000 0 0x10000>; |
| #interrupt-cells = <2>; |
| #address-cells = <0>; |
| interrupt-controller; |
| interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "nmi", |
| "port_irq0", "port_irq1", "port_irq2", |
| "port_irq3", "port_irq4", "port_irq5", |
| "port_irq6", "port_irq7", "port_irq8", |
| "port_irq9", "port_irq10", "port_irq11", |
| "port_irq12", "port_irq13", "port_irq14", |
| "port_irq15", |
| "tint0", "tint1", "tint2", "tint3", |
| "tint4", "tint5", "tint6", "tint7", |
| "tint8", "tint9", "tint10", "tint11", |
| "tint12", "tint13", "tint14", "tint15", |
| "tint16", "tint17", "tint18", "tint19", |
| "tint20", "tint21", "tint22", "tint23", |
| "tint24", "tint25", "tint26", "tint27", |
| "tint28", "tint29", "tint30", "tint31", |
| "int-ca55-0", "int-ca55-1", |
| "int-ca55-2", "int-ca55-3", |
| "icu-error-ca55", |
| "gpt-u0-gtciada", "gpt-u0-gtciadb", |
| "gpt-u1-gtciada", "gpt-u1-gtciadb"; |
| clocks = <&cpg CPG_MOD 0x5>; |
| power-domains = <&cpg>; |
| resets = <&cpg 0x36>; |
| }; |
| |
| pinctrl: pinctrl@10410000 { |
| compatible = "renesas,r9a09g047-pinctrl"; |
| reg = <0 0x10410000 0 0x10000>; |
| clocks = <&cpg CPG_CORE R9A09G047_IOTOP_0_SHCLK>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pinctrl 0 0 232>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| interrupt-parent = <&icu>; |
| power-domains = <&cpg>; |
| resets = <&cpg 0xa5>, <&cpg 0xa6>; |
| }; |
| |
| cpg: clock-controller@10420000 { |
| compatible = "renesas,r9a09g047-cpg"; |
| reg = <0 0x10420000 0 0x10000>; |
| clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; |
| clock-names = "audio_extal", "rtxin", "qextal"; |
| #clock-cells = <2>; |
| #reset-cells = <1>; |
| #power-domain-cells = <0>; |
| }; |
| |
| sys: system-controller@10430000 { |
| compatible = "renesas,r9a09g047-sys"; |
| reg = <0 0x10430000 0 0x10000>; |
| clocks = <&cpg CPG_CORE R9A09G047_SYS_0_PCLK>; |
| resets = <&cpg 0x30>; |
| }; |
| |
| xspi: spi@11030000 { |
| compatible = "renesas,r9a09g047-xspi"; |
| reg = <0 0x11030000 0 0x10000>, |
| <0 0x20000000 0 0x10000000>; |
| reg-names = "regs", "dirmap"; |
| interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "pulse", "err_pulse"; |
| clocks = <&cpg CPG_MOD 0x9f>, |
| <&cpg CPG_MOD 0xa0>, |
| <&cpg CPG_CORE R9A09G047_SPI_CLK_SPI>, |
| <&cpg CPG_MOD 0xa1>; |
| clock-names = "ahb", "axi", "spi", "spix2"; |
| resets = <&cpg 0xa3>, <&cpg 0xa4>; |
| reset-names = "hresetn", "aresetn"; |
| power-domains = <&cpg>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| dmac0: dma-controller@11400000 { |
| compatible = "renesas,r9a09g047-dmac", |
| "renesas,r9a09g057-dmac"; |
| reg = <0 0x11400000 0 0x10000>; |
| interrupts = <GIC_SPI 499 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 91 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 92 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 94 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 95 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 96 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 98 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 101 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 104 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "error", |
| "ch0", "ch1", "ch2", "ch3", |
| "ch4", "ch5", "ch6", "ch7", |
| "ch8", "ch9", "ch10", "ch11", |
| "ch12", "ch13", "ch14", "ch15"; |
| clocks = <&cpg CPG_MOD 0x0>; |
| power-domains = <&cpg>; |
| resets = <&cpg 0x31>; |
| #dma-cells = <1>; |
| dma-channels = <16>; |
| renesas,icu = <&icu 4>; |
| }; |
| |
| dmac1: dma-controller@14830000 { |
| compatible = "renesas,r9a09g047-dmac", |
| "renesas,r9a09g057-dmac"; |
| reg = <0 0x14830000 0 0x10000>; |
| interrupts = <GIC_SPI 495 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "error", |
| "ch0", "ch1", "ch2", "ch3", |
| "ch4", "ch5", "ch6", "ch7", |
| "ch8", "ch9", "ch10", "ch11", |
| "ch12", "ch13", "ch14", "ch15"; |
| clocks = <&cpg CPG_MOD 0x1>; |
| power-domains = <&cpg>; |
| resets = <&cpg 0x32>; |
| #dma-cells = <1>; |
| dma-channels = <16>; |
| renesas,icu = <&icu 0>; |
| }; |
| |
| dmac2: dma-controller@14840000 { |
| compatible = "renesas,r9a09g047-dmac", |
| "renesas,r9a09g057-dmac"; |
| reg = <0 0x14840000 0 0x10000>; |
| interrupts = <GIC_SPI 496 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "error", |
| "ch0", "ch1", "ch2", "ch3", |
| "ch4", "ch5", "ch6", "ch7", |
| "ch8", "ch9", "ch10", "ch11", |
| "ch12", "ch13", "ch14", "ch15"; |
| clocks = <&cpg CPG_MOD 0x2>; |
| power-domains = <&cpg>; |
| resets = <&cpg 0x33>; |
| #dma-cells = <1>; |
| dma-channels = <16>; |
| renesas,icu = <&icu 1>; |
| }; |
| |
| dmac3: dma-controller@12000000 { |
| compatible = "renesas,r9a09g047-dmac", |
| "renesas,r9a09g057-dmac"; |
| reg = <0 0x12000000 0 0x10000>; |
| interrupts = <GIC_SPI 497 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 64 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 65 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 69 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 71 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "error", |
| "ch0", "ch1", "ch2", "ch3", |
| "ch4", "ch5", "ch6", "ch7", |
| "ch8", "ch9", "ch10", "ch11", |
| "ch12", "ch13", "ch14", "ch15"; |
| clocks = <&cpg CPG_MOD 0x3>; |
| power-domains = <&cpg>; |
| resets = <&cpg 0x34>; |
| #dma-cells = <1>; |
| dma-channels = <16>; |
| renesas,icu = <&icu 2>; |
| }; |
| |
| dmac4: dma-controller@12010000 { |
| compatible = "renesas,r9a09g047-dmac", |
| "renesas,r9a09g057-dmac"; |
| reg = <0 0x12010000 0 0x10000>; |
| interrupts = <GIC_SPI 498 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 81 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "error", |
| "ch0", "ch1", "ch2", "ch3", |
| "ch4", "ch5", "ch6", "ch7", |
| "ch8", "ch9", "ch10", "ch11", |
| "ch12", "ch13", "ch14", "ch15"; |
| clocks = <&cpg CPG_MOD 0x4>; |
| power-domains = <&cpg>; |
| resets = <&cpg 0x35>; |
| #dma-cells = <1>; |
| dma-channels = <16>; |
| renesas,icu = <&icu 3>; |
| }; |
| |
| scif0: serial@11c01400 { |
| compatible = "renesas,scif-r9a09g047", "renesas,scif-r9a09g057"; |
| reg = <0 0x11c01400 0 0x400>; |
| interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 536 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 537 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "eri", "rxi", "txi", "bri", "dri", |
| "tei", "tei-dri", "rxi-edge", "txi-edge"; |
| clocks = <&cpg CPG_MOD 0x8f>; |
| clock-names = "fck"; |
| power-domains = <&cpg>; |
| resets = <&cpg 0x95>; |
| status = "disabled"; |
| }; |
| |
| i3c: i3c@12400000 { |
| compatible = "renesas,r9a09g047-i3c"; |
| reg = <0 0x12400000 0 0x10000>; |
| clocks = <&cpg CPG_MOD 0x91>, |
| <&cpg CPG_MOD 0x92>, |
| <&cpg CPG_MOD 0x90>; |
| clock-names = "pclk", "tclk", "pclkrw"; |
| interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 677 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 678 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 679 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 680 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 681 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 682 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "ierr", "terr", "abort", "resp", |
| "cmd", "ibi", "rx", "tx", "rcv", |
| "st", "sp", "tend", "nack", "al", |
| "tmo", "wu"; |
| resets = <&cpg 0x96>, <&cpg 0x97>; |
| reset-names = "presetn", "tresetn"; |
| power-domains = <&cpg>; |
| #address-cells = <3>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| canfd: can@12440000 { |
| compatible = "renesas,r9a09g047-canfd"; |
| reg = <0 0x12440000 0 0x40000>; |
| interrupts = <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 698 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 705 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 701 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "g_err", "g_recc", |
| "ch0_err", "ch0_rec", "ch0_trx", |
| "ch1_err", "ch1_rec", "ch1_trx", |
| "ch2_err", "ch2_rec", "ch2_trx", |
| "ch3_err", "ch3_rec", "ch3_trx", |
| "ch4_err", "ch4_rec", "ch4_trx", |
| "ch5_err", "ch5_rec", "ch5_trx"; |
| clocks = <&cpg CPG_MOD 0x9c>, <&cpg CPG_MOD 0x9d>, |
| <&cpg CPG_MOD 0x9e>; |
| clock-names = "fck", "ram_clk", "can_clk"; |
| assigned-clocks = <&cpg CPG_MOD 0x9e>; |
| assigned-clock-rates = <80000000>; |
| resets = <&cpg 0xa1>, <&cpg 0xa2>; |
| reset-names = "rstp_n", "rstc_n"; |
| power-domains = <&cpg>; |
| status = "disabled"; |
| |
| channel0 { |
| status = "disabled"; |
| }; |
| channel1 { |
| status = "disabled"; |
| }; |
| channel2 { |
| status = "disabled"; |
| }; |
| channel3 { |
| status = "disabled"; |
| }; |
| channel4 { |
| status = "disabled"; |
| }; |
| channel5 { |
| status = "disabled"; |
| }; |
| }; |
| |
| rsci0: serial@12800c00 { |
| compatible = "renesas,r9a09g047-rsci"; |
| reg = <0 0x12800c00 0 0x400>; |
| interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 115 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 118 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "eri", "rxi", "txi", "tei", |
| "aed", "bfd"; |
| clocks = <&cpg CPG_MOD 0x5d>, <&cpg CPG_MOD 0x5e>, |
| <&cpg CPG_MOD 0x61>, <&cpg CPG_MOD 0x60>, |
| <&cpg CPG_MOD 0x5f>; |
| clock-names = "pclk", "tclk", "tclk_div4", |
| "tclk_div16", "tclk_div64"; |
| power-domains = <&cpg>; |
| resets = <&cpg 0x81>, <&cpg 0x82>; |
| reset-names = "presetn", "tresetn"; |
| status = "disabled"; |
| }; |
| |
| rsci1: serial@12801000 { |
| compatible = "renesas,r9a09g047-rsci"; |
| reg = <0 0x12801000 0 0x400>; |
| interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 124 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "eri", "rxi", "txi", "tei", |
| "aed", "bfd"; |
| clocks = <&cpg CPG_MOD 0x62>, <&cpg CPG_MOD 0x63>, |
| <&cpg CPG_MOD 0x66>, <&cpg CPG_MOD 0x65>, |
| <&cpg CPG_MOD 0x64>; |
| clock-names = "pclk", "tclk", "tclk_div4", |
| "tclk_div16", "tclk_div64"; |
| power-domains = <&cpg>; |
| resets = <&cpg 0x83>, <&cpg 0x84>; |
| reset-names = "presetn", "tresetn"; |
| status = "disabled"; |
| }; |
| |
| rsci2: serial@12801400 { |
| compatible = "renesas,r9a09g047-rsci"; |
| reg = <0 0x12801400 0 0x400>; |
| interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "eri", "rxi", "txi", "tei", |
| "aed", "bfd"; |
| clocks = <&cpg CPG_MOD 0x67>, <&cpg CPG_MOD 0x68>, |
| <&cpg CPG_MOD 0x6b>, <&cpg CPG_MOD 0x6a>, |
| <&cpg CPG_MOD 0x69>; |
| clock-names = "pclk", "tclk", "tclk_div4", |
| "tclk_div16", "tclk_div64"; |
| power-domains = <&cpg>; |
| resets = <&cpg 0x85>, <&cpg 0x86>; |
| reset-names = "presetn", "tresetn"; |
| status = "disabled"; |
| }; |
| |
| rsci3: serial@12801800 { |
| compatible = "renesas,r9a09g047-rsci"; |
| reg = <0 0x12801800 0 0x400>; |
| interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "eri", "rxi", "txi", "tei", |
| "aed", "bfd"; |
| clocks = <&cpg CPG_MOD 0x6c>, <&cpg CPG_MOD 0x6d>, |
| <&cpg CPG_MOD 0x70>, <&cpg CPG_MOD 0x6f>, |
| <&cpg CPG_MOD 0x6e>; |
| clock-names = "pclk", "tclk", "tclk_div4", |
| "tclk_div16", "tclk_div64"; |
| power-domains = <&cpg>; |
| resets = <&cpg 0x87>, <&cpg 0x88>; |
| reset-names = "presetn", "tresetn"; |
| status = "disabled"; |
| }; |
| |
| rsci4: serial@12801c00 { |
| compatible = "renesas,r9a09g047-rsci"; |
| reg = <0 0x12801c00 0 0x400>; |
| interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "eri", "rxi", "txi", "tei", |
| "aed", "bfd"; |
| clocks = <&cpg CPG_MOD 0x71>, <&cpg CPG_MOD 0x72>, |
| <&cpg CPG_MOD 0x75>, <&cpg CPG_MOD 0x74>, |
| <&cpg CPG_MOD 0x73>; |
| clock-names = "pclk", "tclk", "tclk_div4", |
| "tclk_div16", "tclk_div64"; |
| power-domains = <&cpg>; |
| resets = <&cpg 0x89>, <&cpg 0x8a>; |
| reset-names = "presetn", "tresetn"; |
| status = "disabled"; |
| }; |
| |
| rsci5: serial@12802000 { |
| compatible = "renesas,r9a09g047-rsci"; |
| reg = <0 0x12802000 0 0x400>; |
| interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "eri", "rxi", "txi", "tei", |
| "aed", "bfd"; |
| clocks = <&cpg CPG_MOD 0x76>, <&cpg CPG_MOD 0x77>, |
| <&cpg CPG_MOD 0x7a>, <&cpg CPG_MOD 0x79>, |
| <&cpg CPG_MOD 0x78>; |
| clock-names = "pclk", "tclk", "tclk_div4", |
| "tclk_div16", "tclk_div64"; |
| power-domains = <&cpg>; |
| resets = <&cpg 0x8b>, <&cpg 0x8c>; |
| reset-names = "presetn", "tresetn"; |
| status = "disabled"; |
| }; |
| |
| rsci6: serial@12802400 { |
| compatible = "renesas,r9a09g047-rsci"; |
| reg = <0 0x12802400 0 0x400>; |
| interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 154 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "eri", "rxi", "txi", "tei", |
| "aed", "bfd"; |
| clocks = <&cpg CPG_MOD 0x7b>, <&cpg CPG_MOD 0x7c>, |
| <&cpg CPG_MOD 0x7f>, <&cpg CPG_MOD 0x7e>, |
| <&cpg CPG_MOD 0x7d>; |
| clock-names = "pclk", "tclk", "tclk_div4", |
| "tclk_div16", "tclk_div64"; |
| power-domains = <&cpg>; |
| resets = <&cpg 0x8d>, <&cpg 0x8e>; |
| reset-names = "presetn", "tresetn"; |
| status = "disabled"; |
| }; |
| |
| rsci7: serial@12802800 { |
| compatible = "renesas,r9a09g047-rsci"; |
| reg = <0 0x12802800 0 0x400>; |
| interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 160 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "eri", "rxi", "txi", "tei", |
| "aed", "bfd"; |
| clocks = <&cpg CPG_MOD 0x80>, <&cpg CPG_MOD 0x81>, |
| <&cpg CPG_MOD 0x84>, <&cpg CPG_MOD 0x83>, |
| <&cpg CPG_MOD 0x82>; |
| clock-names = "pclk", "tclk", "tclk_div4", |
| "tclk_div16", "tclk_div64"; |
| power-domains = <&cpg>; |
| resets = <&cpg 0x8f>, <&cpg 0x90>; |
| reset-names = "presetn", "tresetn"; |
| status = "disabled"; |
| }; |
| |
| rsci8: serial@12802c00 { |
| compatible = "renesas,r9a09g047-rsci"; |
| reg = <0 0x12802c00 0 0x400>; |
| interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 164 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "eri", "rxi", "txi", "tei", |
| "aed", "bfd"; |
| clocks = <&cpg CPG_MOD 0x85>, <&cpg CPG_MOD 0x86>, |
| <&cpg CPG_MOD 0x89>, <&cpg CPG_MOD 0x88>, |
| <&cpg CPG_MOD 0x87>; |
| clock-names = "pclk", "tclk", "tclk_div4", |
| "tclk_div16", "tclk_div64"; |
| power-domains = <&cpg>; |
| resets = <&cpg 0x91>, <&cpg 0x92>; |
| reset-names = "presetn", "tresetn"; |
| status = "disabled"; |
| }; |
| |
| rsci9: serial@12803000 { |
| compatible = "renesas,r9a09g047-rsci"; |
| reg = <0 0x12803000 0 0x400>; |
| interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "eri", "rxi", "txi", "tei", |
| "aed", "bfd"; |
| clocks = <&cpg CPG_MOD 0x8a>, <&cpg CPG_MOD 0x8b>, |
| <&cpg CPG_MOD 0x8e>, <&cpg CPG_MOD 0x8d>, |
| <&cpg CPG_MOD 0x8c>; |
| clock-names = "pclk", "tclk", "tclk_div4", |
| "tclk_div16", "tclk_div64"; |
| power-domains = <&cpg>; |
| resets = <&cpg 0x93>, <&cpg 0x94>; |
| reset-names = "presetn", "tresetn"; |
| status = "disabled"; |
| }; |
| |
| wdt1: watchdog@14400000 { |
| compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt"; |
| reg = <0 0x14400000 0 0x400>; |
| clocks = <&cpg CPG_MOD 0x4d>, <&cpg CPG_MOD 0x4e>; |
| clock-names = "pclk", "oscclk"; |
| resets = <&cpg 0x76>; |
| power-domains = <&cpg>; |
| status = "disabled"; |
| }; |
| |
| wdt2: watchdog@13000000 { |
| compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt"; |
| reg = <0 0x13000000 0 0x400>; |
| clocks = <&cpg CPG_MOD 0x4f>, <&cpg CPG_MOD 0x50>; |
| clock-names = "pclk", "oscclk"; |
| resets = <&cpg 0x77>; |
| power-domains = <&cpg>; |
| status = "disabled"; |
| }; |
| |
| wdt3: watchdog@13000400 { |
| compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt"; |
| reg = <0 0x13000400 0 0x400>; |
| clocks = <&cpg CPG_MOD 0x51>, <&cpg CPG_MOD 0x52>; |
| clock-names = "pclk", "oscclk"; |
| resets = <&cpg 0x78>; |
| power-domains = <&cpg>; |
| status = "disabled"; |
| }; |
| |
| tsu: thermal@14002000 { |
| compatible = "renesas,r9a09g047-tsu"; |
| reg = <0 0x14002000 0 0x1000>; |
| interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "adi", "adcmpi"; |
| clocks = <&cpg CPG_MOD 0x10a>; |
| resets = <&cpg 0xf8>; |
| power-domains = <&cpg>; |
| #thermal-sensor-cells = <0>; |
| renesas,tsu-trim = <&sys 0x330>; |
| }; |
| |
| i2c0: i2c@14400400 { |
| compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; |
| reg = <0 0x14400400 0 0x400>; |
| interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 507 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 506 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "tei", "ri", "ti", "spi", "sti", |
| "naki", "ali", "tmoi"; |
| clocks = <&cpg CPG_MOD 0x94>; |
| resets = <&cpg 0x98>; |
| power-domains = <&cpg>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@14400800 { |
| compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; |
| reg = <0 0x14400800 0 0x400>; |
| interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 509 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 508 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "tei", "ri", "ti", "spi", "sti", |
| "naki", "ali", "tmoi"; |
| clocks = <&cpg CPG_MOD 0x95>; |
| resets = <&cpg 0x99>; |
| power-domains = <&cpg>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@14400c00 { |
| compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; |
| reg = <0 0x14400c00 0 0x400>; |
| interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 511 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 510 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "tei", "ri", "ti", "spi", "sti", |
| "naki", "ali", "tmoi"; |
| clocks = <&cpg CPG_MOD 0x96>; |
| resets = <&cpg 0x9a>; |
| power-domains = <&cpg>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@14401000 { |
| compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; |
| reg = <0 0x14401000 0 0x400>; |
| interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 513 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 512 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "tei", "ri", "ti", "spi", "sti", |
| "naki", "ali", "tmoi"; |
| clocks = <&cpg CPG_MOD 0x97>; |
| resets = <&cpg 0x9b>; |
| power-domains = <&cpg>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c4: i2c@14401400 { |
| compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; |
| reg = <0 0x14401400 0 0x400>; |
| interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 515 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 514 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "tei", "ri", "ti", "spi", "sti", |
| "naki", "ali", "tmoi"; |
| clocks = <&cpg CPG_MOD 0x98>; |
| resets = <&cpg 0x9c>; |
| power-domains = <&cpg>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c5: i2c@14401800 { |
| compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; |
| reg = <0 0x14401800 0 0x400>; |
| interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 517 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 516 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "tei", "ri", "ti", "spi", "sti", |
| "naki", "ali", "tmoi"; |
| clocks = <&cpg CPG_MOD 0x99>; |
| resets = <&cpg 0x9d>; |
| power-domains = <&cpg>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c6: i2c@14401c00 { |
| compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; |
| reg = <0 0x14401c00 0 0x400>; |
| interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 519 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 518 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "tei", "ri", "ti", "spi", "sti", |
| "naki", "ali", "tmoi"; |
| clocks = <&cpg CPG_MOD 0x9a>; |
| resets = <&cpg 0x9e>; |
| power-domains = <&cpg>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c7: i2c@14402000 { |
| compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; |
| reg = <0 0x14402000 0 0x400>; |
| interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 521 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 520 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "tei", "ri", "ti", "spi", "sti", |
| "naki", "ali", "tmoi"; |
| clocks = <&cpg CPG_MOD 0x9b>; |
| resets = <&cpg 0x9f>; |
| power-domains = <&cpg>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c8: i2c@11c01000 { |
| compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; |
| reg = <0 0x11c01000 0 0x400>; |
| interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 523 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 522 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "tei", "ri", "ti", "spi", "sti", |
| "naki", "ali", "tmoi"; |
| clocks = <&cpg CPG_MOD 0x93>; |
| resets = <&cpg 0xa0>; |
| power-domains = <&cpg>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| gpu: gpu@14850000 { |
| compatible = "renesas,r9a09g047-mali", |
| "arm,mali-bifrost"; |
| reg = <0x0 0x14850000 0x0 0x10000>; |
| interrupts = <GIC_SPI 884 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 883 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "job", "mmu", "gpu", "event"; |
| clocks = <&cpg CPG_MOD 0xf0>, |
| <&cpg CPG_MOD 0xf1>, |
| <&cpg CPG_MOD 0xf2>; |
| clock-names = "gpu", "bus", "bus_ace"; |
| power-domains = <&cpg>; |
| resets = <&cpg 0xdd>, <&cpg 0xde>, <&cpg 0xdf>; |
| reset-names = "rst", "axi_rst", "ace_rst"; |
| operating-points-v2 = <&gpu_opp_table>; |
| status = "disabled"; |
| }; |
| |
| gic: interrupt-controller@14900000 { |
| compatible = "arm,gic-v3"; |
| reg = <0x0 0x14900000 0 0x20000>, |
| <0x0 0x14940000 0 0x80000>; |
| #interrupt-cells = <3>; |
| #address-cells = <0>; |
| interrupt-controller; |
| interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; |
| }; |
| |
| xhci: usb@15850000 { |
| compatible = "renesas,r9a09g047-xhci"; |
| reg = <0 0x15850000 0 0x10000>; |
| interrupts = <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "all", "smi", "hse", "pme", "xhc"; |
| clocks = <&cpg CPG_MOD 0xaf>; |
| power-domains = <&cpg>; |
| resets = <&cpg 0xaa>; |
| phys = <&usb3_phy>, <&usb3_phy>; |
| phy-names = "usb2-phy", "usb3-phy"; |
| status = "disabled"; |
| }; |
| |
| usb3_phy: usb-phy@15870000 { |
| compatible = "renesas,r9a09g047-usb3-phy"; |
| reg = <0 0x15870000 0 0x10000>; |
| clocks = <&cpg CPG_MOD 0xb0>, |
| <&cpg CPG_CORE R9A09G047_USB3_0_CLKCORE>, |
| <&cpg CPG_CORE R9A09G047_USB3_0_REF_ALT_CLK_P>; |
| clock-names = "pclk", "core", "ref_alt_clk_p"; |
| power-domains = <&cpg>; |
| resets = <&cpg 0xaa>; |
| #phy-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| sdhi0: mmc@15c00000 { |
| compatible = "renesas,sdhi-r9a09g047", "renesas,sdhi-r9a09g057"; |
| reg = <0x0 0x15c00000 0 0x10000>; |
| interrupts = <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 0xa3>, <&cpg CPG_MOD 0xa5>, |
| <&cpg CPG_MOD 0xa4>, <&cpg CPG_MOD 0xa6>; |
| clock-names = "core", "clkh", "cd", "aclk"; |
| resets = <&cpg 0xa7>; |
| power-domains = <&cpg>; |
| status = "disabled"; |
| |
| sdhi0_vqmmc: vqmmc-regulator { |
| regulator-name = "SDHI0-VQMMC"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| status = "disabled"; |
| }; |
| }; |
| |
| sdhi1: mmc@15c10000 { |
| compatible = "renesas,sdhi-r9a09g047", "renesas,sdhi-r9a09g057"; |
| reg = <0x0 0x15c10000 0 0x10000>; |
| interrupts = <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 0xa7>, <&cpg CPG_MOD 0xa9>, |
| <&cpg CPG_MOD 0xa8>, <&cpg CPG_MOD 0xaa>; |
| clock-names = "core", "clkh", "cd", "aclk"; |
| resets = <&cpg 0xa8>; |
| power-domains = <&cpg>; |
| status = "disabled"; |
| |
| sdhi1_vqmmc: vqmmc-regulator { |
| regulator-name = "SDHI1-VQMMC"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| status = "disabled"; |
| }; |
| }; |
| |
| sdhi2: mmc@15c20000 { |
| compatible = "renesas,sdhi-r9a09g047", "renesas,sdhi-r9a09g057"; |
| reg = <0x0 0x15c20000 0 0x10000>; |
| interrupts = <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 0xab>, <&cpg CPG_MOD 0xad>, |
| <&cpg CPG_MOD 0xac>, <&cpg CPG_MOD 0xae>; |
| clock-names = "core", "clkh", "cd", "aclk"; |
| resets = <&cpg 0xa9>; |
| power-domains = <&cpg>; |
| status = "disabled"; |
| |
| sdhi2_vqmmc: vqmmc-regulator { |
| regulator-name = "SDHI2-VQMMC"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| status = "disabled"; |
| }; |
| }; |
| |
| eth0: ethernet@15c30000 { |
| compatible = "renesas,r9a09g047-gbeth", "renesas,rzv2h-gbeth", |
| "snps,dwmac-5.20"; |
| reg = <0 0x15c30000 0 0x10000>; |
| clocks = <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>, |
| <&cpg CPG_CORE R9A09G047_GBETH_0_CLK_PTP_REF_I>, |
| <&cpg CPG_MOD 0xb8>, <&cpg CPG_MOD 0xb9>, |
| <&cpg CPG_MOD 0xba>, <&cpg CPG_MOD 0xbb>; |
| clock-names = "stmmaceth", "pclk", "ptp_ref", |
| "tx", "rx", "tx-180", "rx-180"; |
| interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", |
| "rx-queue-0", "rx-queue-1", "rx-queue-2", |
| "rx-queue-3", "tx-queue-0", "tx-queue-1", |
| "tx-queue-2", "tx-queue-3"; |
| resets = <&cpg 0xb0>; |
| power-domains = <&cpg>; |
| snps,multicast-filter-bins = <256>; |
| snps,perfect-filter-entries = <128>; |
| rx-fifo-depth = <8192>; |
| tx-fifo-depth = <8192>; |
| snps,mixed-burst; |
| snps,force_sf_dma_mode; |
| snps,axi-config = <&stmmac_axi_setup>; |
| snps,mtl-rx-config = <&mtl_rx_setup0>; |
| snps,mtl-tx-config = <&mtl_tx_setup0>; |
| snps,txpbl = <32>; |
| snps,rxpbl = <32>; |
| status = "disabled"; |
| |
| mdio0: mdio { |
| compatible = "snps,dwmac-mdio"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| mtl_rx_setup0: rx-queues-config { |
| snps,rx-queues-to-use = <4>; |
| snps,rx-sched-sp; |
| |
| queue0 { |
| snps,dcb-algorithm; |
| snps,priority = <0x1>; |
| snps,map-to-dma-channel = <0>; |
| }; |
| |
| queue1 { |
| snps,dcb-algorithm; |
| snps,priority = <0x2>; |
| snps,map-to-dma-channel = <1>; |
| }; |
| |
| queue2 { |
| snps,dcb-algorithm; |
| snps,priority = <0x4>; |
| snps,map-to-dma-channel = <2>; |
| }; |
| |
| queue3 { |
| snps,dcb-algorithm; |
| snps,priority = <0x8>; |
| snps,map-to-dma-channel = <3>; |
| }; |
| }; |
| |
| mtl_tx_setup0: tx-queues-config { |
| snps,tx-queues-to-use = <4>; |
| |
| queue0 { |
| snps,dcb-algorithm; |
| snps,priority = <0x1>; |
| }; |
| |
| queue1 { |
| snps,dcb-algorithm; |
| snps,priority = <0x2>; |
| }; |
| |
| queue2 { |
| snps,dcb-algorithm; |
| snps,priority = <0x4>; |
| }; |
| |
| queue3 { |
| snps,dcb-algorithm; |
| snps,priority = <0x8>; |
| }; |
| }; |
| }; |
| |
| eth1: ethernet@15c40000 { |
| compatible = "renesas,r9a09g047-gbeth", "renesas,rzv2h-gbeth", |
| "snps,dwmac-5.20"; |
| reg = <0 0x15c40000 0 0x10000>; |
| clocks = <&cpg CPG_MOD 0xc3>, <&cpg CPG_MOD 0xc2>, |
| <&cpg CPG_CORE R9A09G047_GBETH_1_CLK_PTP_REF_I>, |
| <&cpg CPG_MOD 0xbe>, <&cpg CPG_MOD 0xbf>, |
| <&cpg CPG_MOD 0xc0>, <&cpg CPG_MOD 0xc1>; |
| clock-names = "stmmaceth", "pclk", "ptp_ref", |
| "tx", "rx", "tx-180", "rx-180"; |
| interrupts = <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", |
| "rx-queue-0", "rx-queue-1", "rx-queue-2", |
| "rx-queue-3", "tx-queue-0", "tx-queue-1", |
| "tx-queue-2", "tx-queue-3"; |
| resets = <&cpg 0xb1>; |
| power-domains = <&cpg>; |
| snps,multicast-filter-bins = <256>; |
| snps,perfect-filter-entries = <128>; |
| rx-fifo-depth = <8192>; |
| tx-fifo-depth = <8192>; |
| snps,mixed-burst; |
| snps,force_sf_dma_mode; |
| snps,axi-config = <&stmmac_axi_setup>; |
| snps,mtl-rx-config = <&mtl_rx_setup1>; |
| snps,mtl-tx-config = <&mtl_tx_setup1>; |
| snps,txpbl = <32>; |
| snps,rxpbl = <32>; |
| status = "disabled"; |
| |
| mdio1: mdio { |
| compatible = "snps,dwmac-mdio"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| mtl_rx_setup1: rx-queues-config { |
| snps,rx-queues-to-use = <4>; |
| snps,rx-sched-sp; |
| |
| queue0 { |
| snps,dcb-algorithm; |
| snps,priority = <0x1>; |
| snps,map-to-dma-channel = <0>; |
| }; |
| |
| queue1 { |
| snps,dcb-algorithm; |
| snps,priority = <0x2>; |
| snps,map-to-dma-channel = <1>; |
| }; |
| |
| queue2 { |
| snps,dcb-algorithm; |
| snps,priority = <0x4>; |
| snps,map-to-dma-channel = <2>; |
| }; |
| |
| queue3 { |
| snps,dcb-algorithm; |
| snps,priority = <0x8>; |
| snps,map-to-dma-channel = <3>; |
| }; |
| }; |
| |
| mtl_tx_setup1: tx-queues-config { |
| snps,tx-queues-to-use = <4>; |
| |
| queue0 { |
| snps,dcb-algorithm; |
| snps,priority = <0x1>; |
| }; |
| |
| queue1 { |
| snps,dcb-algorithm; |
| snps,priority = <0x2>; |
| }; |
| |
| queue2 { |
| snps,dcb-algorithm; |
| snps,priority = <0x4>; |
| }; |
| |
| queue3 { |
| snps,dcb-algorithm; |
| snps,priority = <0x8>; |
| }; |
| }; |
| }; |
| |
| cru: video@16000000 { |
| compatible = "renesas,r9a09g047-cru"; |
| reg = <0 0x16000000 0 0x400>; |
| clocks = <&cpg CPG_MOD 0xd3>, |
| <&cpg CPG_MOD 0xd4>, |
| <&cpg CPG_MOD 0xd2>; |
| clock-names = "video", "apb", "axi"; |
| interrupts = <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 840 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 841 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "image_conv", "axi_mst_err", |
| "vd_addr_wend", "sd_addr_wend", |
| "vsd_addr_wend"; |
| resets = <&cpg 0xc5>, <&cpg 0xc6>; |
| reset-names = "presetn", "aresetn"; |
| power-domains = <&cpg>; |
| status = "disabled"; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@1 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| reg = <1>; |
| crucsi2: endpoint@0 { |
| reg = <0>; |
| remote-endpoint = <&csi2cru>; |
| }; |
| }; |
| }; |
| }; |
| |
| csi2: csi2@16000400 { |
| compatible = "renesas,r9a09g047-csi2", "renesas,r9a09g057-csi2"; |
| reg = <0 0x16000400 0 0xc00>; |
| interrupts = <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 0xd3>, <&cpg CPG_MOD 0xd4>; |
| clock-names = "video", "apb"; |
| resets = <&cpg 0xc5>, <&cpg 0xc7>; |
| reset-names = "presetn", "cmn-rstb"; |
| power-domains = <&cpg>; |
| status = "disabled"; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| }; |
| |
| port@1 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <1>; |
| |
| csi2cru: endpoint@0 { |
| reg = <0>; |
| remote-endpoint = <&crucsi2>; |
| }; |
| }; |
| }; |
| }; |
| }; |
| |
| stmmac_axi_setup: stmmac-axi-config { |
| snps,lpi_en; |
| snps,wr_osr_lmt = <0xf>; |
| snps,rd_osr_lmt = <0xf>; |
| snps,blen = <16 8 4 0 0 0 0>; |
| }; |
| |
| thermal-zones { |
| cpu-thermal { |
| polling-delay = <1000>; |
| polling-delay-passive = <250>; |
| thermal-sensors = <&tsu>; |
| |
| cooling-maps { |
| map0 { |
| trip = <&target>; |
| cooling-device = <&cpu0 0 3>, <&cpu1 0 3>, |
| <&cpu2 0 3>, <&cpu3 0 3>; |
| contribution = <1024>; |
| }; |
| }; |
| |
| trips { |
| target: trip-point { |
| temperature = <95000>; |
| hysteresis = <1000>; |
| type = "passive"; |
| }; |
| |
| sensor_crit: sensor-crit { |
| temperature = <120000>; |
| hysteresis = <1000>; |
| type = "critical"; |
| }; |
| }; |
| }; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; |
| interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; |
| }; |
| }; |
