Google Git
Sign in
zircon-guest/third_party/linux/refs/heads/linux-rolling-stable/./arch/arm64/boot/dts/qcom/sm8750.dtsi
blob: f56b1f889b857a28859910f5c4465c8ce3473b00 [file] [edit]
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sm8750-gcc.h>
#include <dt-bindings/clock/qcom,sm8750-tcsr.h>
#include <dt-bindings/clock/qcom,sm8750-videocc.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/firmware/qcom,scm.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,sm8750-rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,gpr.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
/ {
interrupt-parent = <&intc>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "qcom,oryon";
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&l2_0>;
power-domains = <&cpu_pd0>, <&scmi_dvfs 0>;
power-domain-names = "psci", "perf";
l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
cpu1: cpu@100 {
device_type = "cpu";
compatible = "qcom,oryon";
reg = <0x0 0x100>;
enable-method = "psci";
next-level-cache = <&l2_0>;
power-domains = <&cpu_pd1>, <&scmi_dvfs 0>;
power-domain-names = "psci", "perf";
};
cpu2: cpu@200 {
device_type = "cpu";
compatible = "qcom,oryon";
reg = <0x0 0x200>;
enable-method = "psci";
next-level-cache = <&l2_0>;
power-domains = <&cpu_pd2>, <&scmi_dvfs 0>;
power-domain-names = "psci", "perf";
};
cpu3: cpu@300 {
device_type = "cpu";
compatible = "qcom,oryon";
reg = <0x0 0x300>;
enable-method = "psci";
next-level-cache = <&l2_0>;
power-domains = <&cpu_pd3>, <&scmi_dvfs 0>;
power-domain-names = "psci", "perf";
};
cpu4: cpu@400 {
device_type = "cpu";
compatible = "qcom,oryon";
reg = <0x0 0x400>;
enable-method = "psci";
next-level-cache = <&l2_0>;
power-domains = <&cpu_pd4>, <&scmi_dvfs 0>;
power-domain-names = "psci", "perf";
};
cpu5: cpu@500 {
device_type = "cpu";
compatible = "qcom,oryon";
reg = <0x0 0x500>;
enable-method = "psci";
next-level-cache = <&l2_0>;
power-domains = <&cpu_pd5>, <&scmi_dvfs 0>;
power-domain-names = "psci", "perf";
};
cpu6: cpu@10000 {
device_type = "cpu";
compatible = "qcom,oryon";
reg = <0x0 0x10000>;
enable-method = "psci";
next-level-cache = <&l2_1>;
power-domains = <&cpu_pd6>, <&scmi_dvfs 1>;
power-domain-names = "psci", "perf";
l2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
cpu7: cpu@10100 {
device_type = "cpu";
compatible = "qcom,oryon";
reg = <0x0 0x10100>;
enable-method = "psci";
next-level-cache = <&l2_1>;
power-domains = <&cpu_pd7>, <&scmi_dvfs 1>;
power-domain-names = "psci", "perf";
};
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
core4 {
cpu = <&cpu4>;
};
core5 {
cpu = <&cpu5>;
};
};
cluster1 {
core0 {
cpu = <&cpu6>;
};
core1 {
cpu = <&cpu7>;
};
};
};
idle-states {
entry-method = "psci";
cluster0_c4: cpu-sleep-0 {
compatible = "arm,idle-state";
idle-state-name = "ret";
arm,psci-suspend-param = <0x00000004>;
entry-latency-us = <93>;
exit-latency-us = <129>;
min-residency-us = <560>;
};
cluster1_c4: cpu-sleep-1 {
compatible = "arm,idle-state";
idle-state-name = "ret";
arm,psci-suspend-param = <0x00000004>;
entry-latency-us = <172>;
exit-latency-us = <130>;
min-residency-us = <686>;
};
};
domain-idle-states {
cluster_cl5: cluster-sleep-0 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x01000054>;
entry-latency-us = <2150>;
exit-latency-us = <1983>;
min-residency-us = <9144>;
};
domain_ss3: domain-sleep-0 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x0200c354>;
entry-latency-us = <2800>;
exit-latency-us = <4400>;
min-residency-us = <10150>;
};
};
};
firmware {
scm: scm {
compatible = "qcom,scm-sm8750", "qcom,scm";
interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
};
scmi {
compatible = "arm,scmi";
mboxes = <&cpucp_mbox 0>, <&cpucp_mbox 2>;
mbox-names = "tx", "rx";
shmem = <&cpu_scp_lpri0>, <&cpu_scp_lpri1>;
#address-cells = <1>;
#size-cells = <0>;
scmi_dvfs: protocol@13 {
reg = <0x13>;
#power-domain-cells = <1>;
};
};
};
clk_virt: interconnect-0 {
compatible = "qcom,sm8750-clk-virt";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
mc_virt: interconnect-1 {
compatible = "qcom,sm8750-mc-virt";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
memory@a0000000 {
device_type = "memory";
/* We expect the bootloader to fill in the size */
reg = <0x0 0xa0000000 0x0 0x0>;
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
cpu_pd0: power-domain-cpu0 {
#power-domain-cells = <0>;
power-domains = <&cluster0_pd>;
domain-idle-states = <&cluster0_c4>;
};
cpu_pd1: power-domain-cpu1 {
#power-domain-cells = <0>;
power-domains = <&cluster0_pd>;
domain-idle-states = <&cluster0_c4>;
};
cpu_pd2: power-domain-cpu2 {
#power-domain-cells = <0>;
power-domains = <&cluster0_pd>;
domain-idle-states = <&cluster0_c4>;
};
cpu_pd3: power-domain-cpu3 {
#power-domain-cells = <0>;
power-domains = <&cluster0_pd>;
domain-idle-states = <&cluster0_c4>;
};
cpu_pd4: power-domain-cpu4 {
#power-domain-cells = <0>;
power-domains = <&cluster0_pd>;
domain-idle-states = <&cluster0_c4>;
};
cpu_pd5: power-domain-cpu5 {
#power-domain-cells = <0>;
power-domains = <&cluster0_pd>;
domain-idle-states = <&cluster0_c4>;
};
cpu_pd6: power-domain-cpu6 {
#power-domain-cells = <0>;
power-domains = <&cluster1_pd>;
domain-idle-states = <&cluster1_c4>;
};
cpu_pd7: power-domain-cpu7 {
#power-domain-cells = <0>;
power-domains = <&cluster1_pd>;
domain-idle-states = <&cluster1_c4>;
};
cluster0_pd: power-domain-cluster0 {
#power-domain-cells = <0>;
domain-idle-states = <&cluster_cl5>;
power-domains = <&system_pd>;
};
cluster1_pd: power-domain-cluster1 {
#power-domain-cells = <0>;
domain-idle-states = <&cluster_cl5>;
power-domains = <&system_pd>;
};
system_pd: power-domain-system {
#power-domain-cells = <0>;
domain-idle-states = <&domain_ss3>;
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
gunyah_hyp_mem: gunyah-hyp@80000000 {
reg = <0x0 0x80000000 0x0 0xe00000>;
no-map;
};
cpusys_vm_mem: cpusys-vm-mem@80e00000 {
reg = <0x0 0x80e00000 0x0 0x40000>;
no-map;
};
cpucp_mem: cpucp@81200000 {
reg = <0x0 0x81200000 0x0 0x200000>;
no-map;
};
xbl_dtlog_mem: xbl-dtlog@81a00000 {
reg = <0x0 0x81a00000 0x0 0x40000>;
no-map;
};
aop_image_mem: aop-image@81c00000 {
reg = <0x0 0x81c00000 0x0 0x60000>;
no-map;
};
aop_cmd_db_mem: aop-cmd-db@81c60000 {
compatible = "qcom,cmd-db";
reg = <0x0 0x81c60000 0x0 0x20000>;
no-map;
};
/* Merged aop_config, tme_crash_dump, tme_log and uefi_log regions */
aop_tme_uefi_merged_mem: aop-tme-uefi-merged@81c80000 {
reg = <0x0 0x81c80000 0x0 0x74000>;
no-map;
};
/* Secdata region can be reused by apps */
smem_mem: smem@81d00000 {
compatible = "qcom,smem";
reg = <0x0 0x81d00000 0x0 0x200000>;
hwlocks = <&tcsr_mutex 3>;
no-map;
};
pdp_ns_shared_mem: pdp-ns-shared@81f00000 {
reg = <0x0 0x81f00000 0x0 0x100000>;
no-map;
};
cpucp_scandump_mem: cpucp-scandump@82000000 {
reg = <0x0 0x82000000 0x0 0x380000>;
no-map;
};
adsp_mhi_mem: adsp-mhi@82380000 {
reg = <0x0 0x82380000 0x0 0x20000>;
no-map;
};
soccp_sdi_mem: soccp-sdi@823a0000 {
reg = <0x0 0x823a0000 0x0 0x40000>;
no-map;
};
pmic_minii_dump_mem: pmic-minii-dump@823e0000 {
reg = <0x0 0x823e0000 0x0 0x80000>;
no-map;
};
pvmfw_mem: pvmfw@824a0000 {
reg = <0x0 0x824a0000 0x0 0x100000>;
no-map;
};
global_sync_mem: global-sync@82600000 {
reg = <0x0 0x82600000 0x0 0x100000>;
no-map;
};
tz_stat_mem: tz-stat@82700000 {
reg = <0x0 0x82700000 0x0 0x100000>;
no-map;
};
qdss_mem: qdss@82800000 {
reg = <0x0 0x82800000 0x0 0x2000000>;
no-map;
};
dsm_partition_1_mem: dsm-partition-1@84a00000 {
reg = <0x0 0x84a00000 0x0 0x4900000>;
no-map;
};
dsm_partition_2_mem: dsm-partition-2@89300000 {
reg = <0x0 0x89300000 0x0 0xa80000>;
no-map;
};
mpss_mem: mpss@8ba00000 {
reg = <0x0 0x8ba00000 0x0 0xf600000>;
no-map;
};
q6_mpss_dtb_mem: q6-mpss-dtb@9b000000 {
reg = <0x0 0x9b000000 0x0 0x80000>;
no-map;
};
ipa_fw_mem: ipa-fw@9b080000 {
reg = <0x0 0x9b080000 0x0 0x10000>;
no-map;
};
ipa_gsi_mem: ipa-gsi@9b090000 {
reg = <0x0 0x9b090000 0x0 0xa000>;
no-map;
};
gpu_micro_code_mem: gpu-micro-code@9b09a000 {
reg = <0x0 0x9b09a000 0x0 0x2000>;
no-map;
};
spss_region_mem: spss@9b0a0000 {
reg = <0x0 0x9b0a0000 0x0 0x1e0000>;
no-map;
};
/* First part of the "SPU secure shared memory" region */
spu_tz_shared_mem: spu-tz-shared@9b280000 {
reg = <0x0 0x9b280000 0x0 0x40000>;
no-map;
};
/* Second part of the "SPU secure shared memory" region */
spu_modem_shared_mem: spu-modem-shared@9b2c0000 {
reg = <0x0 0x9b2c0000 0x0 0x40000>;
no-map;
};
camera_mem: camera@9b300000 {
reg = <0x0 0x9b300000 0x0 0x800000>;
no-map;
};
camera_2_mem: camera-2@9bb00000 {
reg = <0x0 0x9bb00000 0x0 0x800000>;
no-map;
};
video_mem: video@9c300000 {
reg = <0x0 0x9c300000 0x0 0x800000>;
no-map;
};
cvp_mem: cvp@9cb00000 {
reg = <0x0 0x9cb00000 0x0 0x700000>;
no-map;
};
cdsp_mem: cdsp@9d200000 {
reg = <0x0 0x9d200000 0x0 0x1900000>;
no-map;
};
q6_cdsp_dtb_mem: q6-cdsp-dtb@9eb00000 {
reg = <0x0 0x9eb00000 0x0 0x80000>;
no-map;
};
soccp_mem: soccp@9ec00000 {
reg = <0x0 0x9ec00000 0x0 0x180000>;
no-map;
};
q6_adsp_dtb_mem: q6-adsp-dtb@9ed80000 {
reg = <0x0 0x9ed80000 0x0 0x80000>;
no-map;
};
adspslpi_mem: adspslpi@9ee00000 {
reg = <0x0 0x9ee00000 0x0 0x3a80000>;
no-map;
};
xbl_ramdump_mem: xbl-ramdump@b8000000 {
reg = <0x0 0xb8000000 0x0 0x1c0000>;
no-map;
};
hwfence_shbuf: hwfence-shbuf@d4e23000 {
no-map;
reg = <0x0 0xd4e23000 0x0 0x2dd000>;
};
/* Merged tz_reserved, xbl_sc, and qtee regions */
tz_merged_mem: tz-merged@d8000000 {
reg = <0x0 0xd8000000 0x0 0x600000>;
no-map;
};
trust_ui_vm_mem: trust-ui-vm@f3800000 {
reg = <0x0 0xf3800000 0x0 0x4400000>;
no-map;
};
oem_vm_mem: oem-vm@f7c00000 {
reg = <0x0 0xf7c00000 0x0 0x4c00000>;
no-map;
};
llcc_lpi_mem: llcc-lpi@ff800000 {
reg = <0x0 0xff800000 0x0 0x800000>;
no-map;
};
adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
alignment = <0x0 0x400000>;
size = <0x0 0xc00000>;
reusable;
};
};
smp2p-adsp {
compatible = "qcom,smp2p";
interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_SMP2P>;
qcom,smem = <443>, <429>;
qcom,local-pid = <0>;
qcom,remote-pid = <2>;
smp2p_adsp_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
smp2p_adsp_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
smp2p-cdsp {
compatible = "qcom,smp2p";
interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_CDSP
IPCC_MPROC_SIGNAL_SMP2P>;
qcom,smem = <94>, <432>;
qcom,local-pid = <0>;
qcom,remote-pid = <5>;
smp2p_cdsp_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
smp2p_cdsp_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
smp2p-modem {
compatible = "qcom,smp2p";
interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_MPSS
IPCC_MPROC_SIGNAL_SMP2P>;
qcom,smem = <435>, <428>;
qcom,local-pid = <0>;
qcom,remote-pid = <1>;
smp2p_modem_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
smp2p_modem_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
ipa_smp2p_out: ipa-ap-to-modem {
qcom,entry-name = "ipa";
#qcom,smem-state-cells = <1>;
};
ipa_smp2p_in: ipa-modem-to-ap {
qcom,entry-name = "ipa";
interrupt-controller;
#interrupt-cells = <2>;
};
/* TODO: smem mailbox in and out */
};
soc: soc@0 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
dma-ranges = <0 0 0 0 0x10 0>;
ranges = <0 0 0 0 0x10 0>;
gcc: clock-controller@100000 {
compatible = "qcom,sm8750-gcc";
reg = <0x0 0x00100000 0x0 0x1f4200>;
clocks = <&bi_tcxo_div2>,
<0>,
<&sleep_clk>,
<&pcie0_phy>,
<0>,
<0>,
<0>,
<&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
ipcc: mailbox@406000 {
compatible = "qcom,sm8750-ipcc", "qcom,ipcc";
reg = <0x0 0x00406000 0x0 0x1000>;
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
#mbox-cells = <2>;
};
gpi_dma2: dma-controller@800000 {
compatible = "qcom,sm8750-gpi-dma", "qcom,sm6350-gpi-dma";
reg = <0x0 0x00800000 0x0 0x60000>;
interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <12>;
dma-channel-mask = <0x1e>;
#dma-cells = <3>;
iommus = <&apps_smmu 0x436 0x0>;
status = "disabled";
};
qupv3_2: geniqup@8c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x008c0000 0x0 0x2000>;
clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
clock-names = "m-ahb",
"s-ahb";
iommus = <&apps_smmu 0x423 0x0>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
i2c8: i2c@880000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x00880000 0x0 0x4000>;
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
<&gpi_dma2 1 0 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c8_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi8: spi@880000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00880000 0x0 0x4000>;
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
<&gpi_dma2 1 0 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c9: i2c@884000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x00884000 0x0 0x4000>;
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
<&gpi_dma2 1 1 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c9_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi9: spi@884000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00884000 0x0 0x4000>;
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
<&gpi_dma2 1 1 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c10: i2c@888000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x00888000 0x0 0x4000>;
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
<&gpi_dma2 1 2 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c10_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi10: spi@888000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00888000 0x0 0x4000>;
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
<&gpi_dma2 1 2 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c11: i2c@88c000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x0088c000 0x0 0x4000>;
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
<&gpi_dma2 1 3 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c11_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi11: spi@88c000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x0088c000 0x0 0x4000>;
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
<&gpi_dma2 1 3 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c12: i2c@890000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x00890000 0x0 0x4000>;
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
<&gpi_dma2 1 4 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c12_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi12: spi@890000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00890000 0x0 0x4000>;
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
<&gpi_dma2 1 4 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c13: i2c@894000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x00894000 0x0 0x4000>;
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
<&gpi_dma2 1 5 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c13_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi13: spi@894000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00894000 0x0 0x4000>;
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
<&gpi_dma2 1 5 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart14: serial@898000 {
compatible = "qcom,geni-uart";
reg = <0x0 0x00898000 0x0 0x4000>;
interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config";
pinctrl-0 = <&qup_uart14_default>;
pinctrl-names = "default";
status = "disabled";
};
i2c15: i2c@89c000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x0089c000 0x0 0x4000>;
interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>,
<&gpi_dma2 1 7 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c15_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi15: spi@89c000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x0089c000 0x0 0x4000>;
interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>,
<&gpi_dma2 1 7 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
i2c_master_hub_0: geniqup@9c0000 {
compatible = "qcom,geni-se-i2c-master-hub";
reg = <0x0 0x009c0000 0x0 0x2000>;
clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>;
clock-names = "s-ahb";
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
i2c_hub_0: i2c@980000 {
compatible = "qcom,geni-i2c-master-hub";
reg = <0x0 0x00980000 0x0 0x4000>;
interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>,
<&gcc GCC_QUPV3_I2C_CORE_CLK>;
clock-names = "se",
"core";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config";
pinctrl-0 = <&hub_i2c0_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c_hub_1: i2c@984000 {
compatible = "qcom,geni-i2c-master-hub";
reg = <0x0 0x00984000 0x0 0x4000>;
interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>,
<&gcc GCC_QUPV3_I2C_CORE_CLK>;
clock-names = "se",
"core";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config";
pinctrl-0 = <&hub_i2c1_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c_hub_2: i2c@988000 {
compatible = "qcom,geni-i2c-master-hub";
reg = <0x0 0x00988000 0x0 0x4000>;
interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>,
<&gcc GCC_QUPV3_I2C_CORE_CLK>;
clock-names = "se",
"core";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config";
pinctrl-0 = <&hub_i2c2_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c_hub_3: i2c@98c000 {
compatible = "qcom,geni-i2c-master-hub";
reg = <0x0 0x0098c000 0x0 0x4000>;
interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>,
<&gcc GCC_QUPV3_I2C_CORE_CLK>;
clock-names = "se",
"core";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config";
pinctrl-0 = <&hub_i2c3_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c_hub_4: i2c@990000 {
compatible = "qcom,geni-i2c-master-hub";
reg = <0x0 0x00990000 0x0 0x4000>;
interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>,
<&gcc GCC_QUPV3_I2C_CORE_CLK>;
clock-names = "se",
"core";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config";
pinctrl-0 = <&hub_i2c4_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c_hub_5: i2c@994000 {
compatible = "qcom,geni-i2c-master-hub";
reg = <0x0 0x00994000 0x0 0x4000>;
interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>,
<&gcc GCC_QUPV3_I2C_CORE_CLK>;
clock-names = "se",
"core";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config";
pinctrl-0 = <&hub_i2c5_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c_hub_6: i2c@998000 {
compatible = "qcom,geni-i2c-master-hub";
reg = <0x0 0x00998000 0x0 0x4000>;
interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>,
<&gcc GCC_QUPV3_I2C_CORE_CLK>;
clock-names = "se",
"core";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config";
pinctrl-0 = <&hub_i2c6_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c_hub_7: i2c@99c000 {
compatible = "qcom,geni-i2c-master-hub";
reg = <0x0 0x0099c000 0x0 0x4000>;
interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>,
<&gcc GCC_QUPV3_I2C_CORE_CLK>;
clock-names = "se",
"core";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config";
pinctrl-0 = <&hub_i2c7_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c_hub_8: i2c@9a0000 {
compatible = "qcom,geni-i2c-master-hub";
reg = <0x0 0x009a0000 0x0 0x4000>;
interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>,
<&gcc GCC_QUPV3_I2C_CORE_CLK>;
clock-names = "se",
"core";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config";
pinctrl-0 = <&hub_i2c8_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c_hub_9: i2c@9a4000 {
compatible = "qcom,geni-i2c-master-hub";
reg = <0x0 0x009a4000 0x0 0x4000>;
interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>,
<&gcc GCC_QUPV3_I2C_CORE_CLK>;
clock-names = "se",
"core";
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config";
pinctrl-0 = <&hub_i2c9_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
gpi_dma1: dma-controller@a00000 {
compatible = "qcom,sm8750-gpi-dma", "qcom,sm6350-gpi-dma";
reg = <0x0 0x00a00000 0x0 0x60000>;
interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <12>;
dma-channel-mask = <0x1e>;
#dma-cells = <3>;
iommus = <&apps_smmu 0xb6 0x0>;
status = "disabled";
};
qupv3_1: geniqup@ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x00ac0000 0x0 0x2000>;
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
clock-names = "m-ahb",
"s-ahb";
iommus = <&apps_smmu 0xa3 0x0>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
i2c0: i2c@a80000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x00a80000 0x0 0x4000>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
<&gpi_dma1 1 0 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c0_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi0: spi@a80000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00a80000 0x0 0x4000>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
<&gpi_dma1 1 0 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@a84000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x00a84000 0x0 0x4000>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
<&gpi_dma1 1 1 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c1_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi1: spi@a84000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00a84000 0x0 0x4000>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
<&gpi_dma1 1 1 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@a88000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x00a88000 0x0 0x4000>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
<&gpi_dma1 1 2 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c2_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi2: spi@a88000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00a88000 0x0 0x4000>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
<&gpi_dma1 1 2 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c3: i2c@a8c000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x00a8c000 0x0 0x4000>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
<&gpi_dma1 1 3 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c3_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi3: spi@a8c000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00a8c000 0x0 0x4000>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
<&gpi_dma1 1 3 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c4: i2c@a90000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x00a90000 0x0 0x4000>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
<&gpi_dma1 1 4 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c4_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi4: spi@a90000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00a90000 0x0 0x4000>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
<&gpi_dma1 1 4 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c5: i2c@a94000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x00a94000 0x0 0x4000>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
<&gpi_dma1 1 5 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c5_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi5: spi@a94000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00a94000 0x0 0x4000>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
<&gpi_dma1 1 5 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c6: i2c@a98000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x00a98000 0x0 0x4000>;
interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
<&gpi_dma1 1 6 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_i2c6_data_clk>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi6: spi@a98000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00a98000 0x0 0x4000>;
interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
<&gpi_dma1 1 6 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart7: serial@a9c000 {
compatible = "qcom,geni-debug-uart";
reg = <0x0 0x00a9c000 0x0 0x4000>;
interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config";
pinctrl-0 = <&qup_uart7_default>;
pinctrl-names = "default";
status = "disabled";
};
};
rng: rng@10c3000 {
compatible = "qcom,sm8750-trng", "qcom,trng";
reg = <0x0 0x010c3000 0x0 0x1000>;
};
cnoc_main: interconnect@1500000 {
compatible = "qcom,sm8750-cnoc-main";
reg = <0x0 0x01500000 0x0 0x16080>;
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <2>;
};
config_noc: interconnect@1600000 {
compatible = "qcom,sm8750-config-noc";
reg = <0x0 0x01600000 0x0 0x6200>;
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <2>;
};
system_noc: interconnect@1680000 {
compatible = "qcom,sm8750-system-noc";
reg = <0x0 0x01680000 0x0 0x1d080>;
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <2>;
};
pcie_noc: interconnect@16c0000 {
compatible = "qcom,sm8750-pcie-anoc";
reg = <0x0 0x016c0000 0x0 0x11400>;
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <2>;
clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
};
aggre1_noc: interconnect@16e0000 {
compatible = "qcom,sm8750-aggre1-noc";
reg = <0x0 0x016e0000 0x0 0x16400>;
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <2>;
clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
};
aggre2_noc: interconnect@1700000 {
compatible = "qcom,sm8750-aggre2-noc";
reg = <0x0 0x01700000 0x0 0x1f400>;
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <2>;
clocks = <&rpmhcc RPMH_IPA_CLK>;
};
mmss_noc: interconnect@1780000 {
compatible = "qcom,sm8750-mmss-noc";
reg = <0x0 0x01780000 0x0 0x5b800>;
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <2>;
};
ice: crypto@1d88000 {
compatible = "qcom,sm8750-inline-crypto-engine",
"qcom,inline-crypto-engine";
reg = <0x0 0x01d88000 0x0 0x18000>;
clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
};
cryptobam: dma-controller@1dc4000 {
compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
reg = <0x0 0x01dc4000 0x0 0x28000>;
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
iommus = <&apps_smmu 0x480 0>,
<&apps_smmu 0x481 0>;
qcom,ee = <0>;
qcom,num-ees = <4>;
num-channels = <20>;
qcom,controlled-remotely;
};
crypto: crypto@1dfa000 {
compatible = "qcom,sm8750-qce", "qcom,sm8150-qce", "qcom,qce";
reg = <0x0 0x01dfa000 0x0 0x6000>;
interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "memory";
dmas = <&cryptobam 4>, <&cryptobam 5>;
dma-names = "rx", "tx";
iommus = <&apps_smmu 0x480 0>,
<&apps_smmu 0x481 0>;
};
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x0 0x01f40000 0x0 0x20000>;
#hwlock-cells = <1>;
};
remoteproc_mpss: remoteproc@4080000 {
compatible = "qcom,sm8750-mpss-pas";
reg = <0x0 0x04080000 0x0 0x10000>;
interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
<&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
<&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
<&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog",
"fatal",
"ready",
"handover",
"stop-ack",
"shutdown-ack";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
power-domains = <&rpmhpd RPMHPD_CX>,
<&rpmhpd RPMHPD_MSS>;
power-domain-names = "cx",
"mss";
memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>,
<&dsm_partition_1_mem>,
<&dsm_partition_2_mem>;
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&smp2p_modem_out 0>;
qcom,smem-state-names = "stop";
status = "disabled";
glink-edge {
interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_MPSS
IPCC_MPROC_SIGNAL_GLINK_QMP>;
qcom,remote-pid = <1>;
label = "mpss";
};
};
remoteproc_adsp: remoteproc@6800000 {
compatible = "qcom,sm8750-adsp-pas", "qcom,sm8550-adsp-pas";
reg = <0x0 0x06800000 0x0 0x10000>;
interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog",
"fatal",
"ready",
"handover",
"stop-ack",
"shutdown-ack";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
power-domains = <&rpmhpd RPMHPD_LCX>,
<&rpmhpd RPMHPD_LMX>;
power-domain-names = "lcx",
"lmx";
memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&smp2p_adsp_out 0>;
qcom,smem-state-names = "stop";
status = "disabled";
remoteproc_adsp_glink: glink-edge {
interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP>;
qcom,remote-pid = <2>;
label = "lpass";
fastrpc {
compatible = "qcom,fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
label = "adsp";
memory-region = <&adsp_rpc_remote_heap_mem>;
qcom,vmids = <QCOM_SCM_VMID_LPASS
QCOM_SCM_VMID_ADSP_HEAP>;
#address-cells = <1>;
#size-cells = <0>;
compute-cb@3 {
compatible = "qcom,fastrpc-compute-cb";
reg = <3>;
iommus = <&apps_smmu 0x1003 0x80>,
<&apps_smmu 0x1043 0x20>;
dma-coherent;
};
compute-cb@4 {
compatible = "qcom,fastrpc-compute-cb";
reg = <4>;
iommus = <&apps_smmu 0x1004 0x80>,
<&apps_smmu 0x1044 0x20>;
dma-coherent;
};
compute-cb@5 {
compatible = "qcom,fastrpc-compute-cb";
reg = <5>;
iommus = <&apps_smmu 0x1005 0x80>,
<&apps_smmu 0x1045 0x20>;
dma-coherent;
};
compute-cb@6 {
compatible = "qcom,fastrpc-compute-cb";
reg = <6>;
iommus = <&apps_smmu 0x1006 0x80>,
<&apps_smmu 0x1046 0x20>;
dma-coherent;
};
compute-cb@7 {
compatible = "qcom,fastrpc-compute-cb";
reg = <7>;
iommus = <&apps_smmu 0x1007 0x40>,
<&apps_smmu 0x1067 0x0>,
<&apps_smmu 0x1087 0x0>;
dma-coherent;
};
compute-cb@8 {
compatible = "qcom,fastrpc-compute-cb";
reg = <8>;
iommus = <&apps_smmu 0x1008 0x80>,
<&apps_smmu 0x1048 0x20>;
dma-coherent;
};
};
gpr {
compatible = "qcom,gpr";
qcom,glink-channels = "adsp_apps";
qcom,domain = <GPR_DOMAIN_ID_ADSP>;
qcom,intents = <512 20>;
#address-cells = <1>;
#size-cells = <0>;
q6apm: service@1 {
compatible = "qcom,q6apm";
reg = <GPR_APM_MODULE_IID>;
#sound-dai-cells = <0>;
qcom,protection-domain = "avs/audio",
"msm/adsp/audio_pd";
q6apmbedai: bedais {
compatible = "qcom,q6apm-lpass-dais";
#sound-dai-cells = <1>;
};
q6apmdai: dais {
compatible = "qcom,q6apm-dais";
iommus = <&apps_smmu 0x1001 0x80>,
<&apps_smmu 0x1041 0x20>;
};
};
q6prm: service@2 {
compatible = "qcom,q6prm";
reg = <GPR_PRM_MODULE_IID>;
qcom,protection-domain = "avs/audio",
"msm/adsp/audio_pd";
q6prmcc: clock-controller {
compatible = "qcom,q6prm-lpass-clocks";
#clock-cells = <2>;
};
};
};
};
};
lpass_wsa2macro: codec@6aa0000 {
compatible = "qcom,sm8750-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
reg = <0x0 0x06aa0000 0x0 0x1000>;
clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&lpass_vamacro>;
clock-names = "mclk",
"macro",
"dcodec",
"fsgen";
#clock-cells = <0>;
clock-output-names = "wsa2-mclk";
#sound-dai-cells = <1>;
};
swr3: soundwire@6ab0000 {
compatible = "qcom,soundwire-v2.1.0", "qcom,soundwire-v2.0.0";
reg = <0x0 0x06ab0000 0x0 0x10000>;
interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&lpass_wsa2macro>;
clock-names = "iface";
label = "WSA2";
pinctrl-0 = <&wsa2_swr_active>;
pinctrl-names = "default";
qcom,din-ports = <4>;
qcom,dout-ports = <9>;
qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0x18f 0x18f 0x0f 0x0f 0xff 0x31f>;
qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0x00 0x00 0x06 0x0d 0xff 0x00>;
qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0x0e 0x0e 0xff 0xff 0xff 0x0f>;
qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0x0e 0x0e 0xff 0xff 0xff 0x0f>;
qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0x0f 0x0f 0x00 0xff 0xff 0x18>;
qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x01 0x01 0x01 0x01 0x00 0x00>;
qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff>;
qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff>;
#address-cells = <2>;
#size-cells = <0>;
#sound-dai-cells = <1>;
status = "disabled";
};
lpass_rxmacro: codec@6ac0000 {
compatible = "qcom,sm8750-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro";
reg = <0x0 0x06ac0000 0x0 0x1000>;
clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&lpass_vamacro>;
clock-names = "mclk",
"macro",
"dcodec",
"fsgen";
#clock-cells = <0>;
clock-output-names = "mclk";
#sound-dai-cells = <1>;
};
swr1: soundwire@6ad0000 {
compatible = "qcom,soundwire-v2.1.0", "qcom,soundwire-v2.0.0";
reg = <0x0 0x06ad0000 0x0 0x10000>;
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&lpass_rxmacro>;
clock-names = "iface";
label = "RX";
pinctrl-0 = <&rx_swr_active>;
pinctrl-names = "default";
qcom,din-ports = <1>;
qcom,dout-ports = <11>;
qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0x31 0xff 0xff 0xff>;
qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0x00 0xff 0xff 0xff>;
qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0x00 0xff 0xff 0xff>;
qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0x00 0xff 0xff 0xff>;
qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0x0f 0xff 0xff 0xff>;
qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0x18 0xff 0xff 0xff>;
qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0x01 0xff 0xff 0xff>;
qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0x00 0xff 0xff 0xff>;
qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0x01 0xff 0xff 0xff>;
#address-cells = <2>;
#size-cells = <0>;
#sound-dai-cells = <1>;
status = "disabled";
};
lpass_txmacro: codec@6ae0000 {
compatible = "qcom,sm8750-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro";
reg = <0x0 0x06ae0000 0x0 0x1000>;
clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&lpass_vamacro>;
clock-names = "mclk",
"macro",
"dcodec",
"fsgen";
#clock-cells = <0>;
clock-output-names = "mclk";
#sound-dai-cells = <1>;
};
lpass_wsamacro: codec@6b00000 {
compatible = "qcom,sm8750-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
reg = <0x0 0x06b00000 0x0 0x1000>;
clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&lpass_vamacro>;
clock-names = "mclk",
"macro",
"dcodec",
"fsgen";
#clock-cells = <0>;
clock-output-names = "mclk";
#sound-dai-cells = <1>;
};
swr0: soundwire@6b10000 {
compatible = "qcom,soundwire-v2.1.0", "qcom,soundwire-v2.0.0";
reg = <0x0 0x06b10000 0x0 0x10000>;
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&lpass_wsamacro>;
clock-names = "iface";
label = "WSA";
pinctrl-0 = <&wsa_swr_active>;
pinctrl-names = "default";
qcom,din-ports = <4>;
qcom,dout-ports = <9>;
qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0x18f 0x18f 0x0f 0x0f 0xff 0x31f>;
qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0x00 0x00 0x06 0x0d 0xff 0x00>;
qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0x0e 0x0e 0xff 0xff 0xff 0x0f>;
qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0x0e 0x0e 0xff 0xff 0xff 0x0f>;
qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0x0f 0x0f 0x00 0xff 0xff 0x18>;
qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x01 0x01 0x01 0x01 0x00 0x00>;
qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff>;
qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff>;
#address-cells = <2>;
#size-cells = <0>;
#sound-dai-cells = <1>;
status = "disabled";
};
lpass_ag_noc: interconnect@7e40000 {
compatible = "qcom,sm8750-lpass-ag-noc";
reg = <0x0 0x07e40000 0x0 0xe080>;
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <2>;
};
lpass_lpiaon_noc: interconnect@7400000 {
compatible = "qcom,sm8750-lpass-lpiaon-noc";
reg = <0x0 0x07400000 0x0 0x19080>;
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <2>;
};
lpass_lpicx_noc: interconnect@7420000 {
compatible = "qcom,sm8750-lpass-lpicx-noc";
reg = <0x0 0x07420000 0x0 0x44080>;
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <2>;
};
swr2: soundwire@7630000 {
compatible = "qcom,soundwire-v2.1.0", "qcom,soundwire-v2.0.0";
reg = <0x0 0x07630000 0x0 0x10000>;
interrupts = <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "core", "wakeup";
clocks = <&lpass_txmacro>;
clock-names = "iface";
label = "TX";
pinctrl-0 = <&tx_swr_active>;
pinctrl-names = "default";
qcom,din-ports = <4>;
qcom,dout-ports = <0>;
qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
#address-cells = <2>;
#size-cells = <0>;
#sound-dai-cells = <1>;
status = "disabled";
};
lpass_vamacro: codec@7660000 {
compatible = "qcom,sm8750-lpass-va-macro", "qcom,sm8550-lpass-va-macro";
reg = <0x0 0x07660000 0x0 0x2000>;
clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
clock-names = "mclk",
"macro",
"dcodec";
#clock-cells = <0>;
clock-output-names = "fsgen";
#sound-dai-cells = <1>;
};
lpass_tlmm: pinctrl@7760000 {
compatible = "qcom,sm8750-lpass-lpi-pinctrl",
"qcom,sm8650-lpass-lpi-pinctrl";
reg = <0x0 0x07760000 0x0 0x20000>;
clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
clock-names = "core", "audio";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&lpass_tlmm 0 0 23>;
tx_swr_active: tx-swr-active-state {
clk-pins {
pins = "gpio0";
function = "swr_tx_clk";
drive-strength = <2>;
slew-rate = <1>;
bias-disable;
};
data-pins {
pins = "gpio1", "gpio2", "gpio14";
function = "swr_tx_data";
drive-strength = <2>;
slew-rate = <1>;
bias-bus-hold;
};
};
rx_swr_active: rx-swr-active-state {
clk-pins {
pins = "gpio3";
function = "swr_rx_clk";
drive-strength = <2>;
slew-rate = <1>;
bias-disable;
};
data-pins {
pins = "gpio4", "gpio5";
function = "swr_rx_data";
drive-strength = <2>;
slew-rate = <1>;
bias-bus-hold;
};
};
dmic01_default: dmic01-default-state {
clk-pins {
pins = "gpio6";
function = "dmic1_clk";
drive-strength = <8>;
output-high;
};
data-pins {
pins = "gpio7";
function = "dmic1_data";
drive-strength = <8>;
input-enable;
};
};
dmic23_default: dmic23-default-state {
clk-pins {
pins = "gpio8";
function = "dmic2_clk";
drive-strength = <8>;
output-high;
};
data-pins {
pins = "gpio9";
function = "dmic2_data";
drive-strength = <8>;
input-enable;
};
};
wsa_swr_active: wsa-swr-active-state {
clk-pins {
pins = "gpio10";
function = "wsa_swr_clk";
drive-strength = <2>;
slew-rate = <1>;
bias-disable;
};
data-pins {
pins = "gpio11";
function = "wsa_swr_data";
drive-strength = <2>;
slew-rate = <1>;
bias-bus-hold;
};
};
wsa2_swr_active: wsa2-swr-active-state {
clk-pins {
pins = "gpio15";
function = "wsa2_swr_clk";
drive-strength = <2>;
slew-rate = <1>;
bias-disable;
};
data-pins {
pins = "gpio16";
function = "wsa2_swr_data";
drive-strength = <2>;
slew-rate = <1>;
bias-bus-hold;
};
};
};
sdhc_2: mmc@8804000 {
compatible = "qcom,sm8750-sdhci", "qcom,sdhci-msm-v5";
reg = <0x0 0x08804000 0x0 0x1000>;
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq",
"pwr_irq";
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
<&gcc GCC_SDCC2_APPS_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface",
"core",
"xo";
interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
interconnect-names = "sdhc-ddr",
"cpu-sdhc";
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&sdhc2_opp_table>;
qcom,dll-config = <0x0007442c>;
qcom,ddr-config = <0x80040868>;
iommus = <&apps_smmu 0x540 0x0>;
dma-coherent;
bus-width = <4>;
max-sd-hs-hz = <37500000>;
resets = <&gcc GCC_SDCC2_BCR>;
status = "disabled";
sdhc2_opp_table: opp-table {
compatible = "operating-points-v2";
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-202000000 {
opp-hz = /bits/ 64 <202000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
};
};
usb_hsphy: phy@88e3000 {
compatible = "qcom,sm8750-m31-eusb2-phy";
reg = <0x0 0x88e3000 0x0 0x29c>;
clocks = <&tcsrcc TCSR_USB2_CLKREF_EN>;
clock-names = "ref";
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
#phy-cells = <0>;
status = "disabled";
};
usb_dp_qmpphy: phy@88e8000 {
compatible = "qcom,sm8750-qmp-usb3-dp-phy";
reg = <0x0 0x088e8000 0x0 0x4000>;
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
<&tcsrcc TCSR_USB3_CLKREF_EN>,
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
clock-names = "aux",
"ref",
"com_aux",
"usb3_pipe";
resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
<&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
reset-names = "phy",
"common";
power-domains = <&gcc GCC_USB3_PHY_GDSC>;
#clock-cells = <1>;
#phy-cells = <1>;
orientation-switch;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usb_dp_qmpphy_out: endpoint {
};
};
port@1 {
reg = <1>;
usb_dp_qmpphy_usb_ss_in: endpoint {
remote-endpoint = <&usb_dwc3_ss>;
};
};
port@2 {
reg = <2>;
usb_dp_qmpphy_dp_in: endpoint {
};
};
};
};
usb: usb@a600000 {
compatible = "qcom,sm8750-dwc3", "qcom,snps-dwc3";
reg = <0x0 0x0a600000 0x0 0xfc100>;
clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
<&gcc GCC_USB30_PRIM_MASTER_CLK>,
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
<&gcc GCC_USB30_PRIM_SLEEP_CLK>,
<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
clock-names = "cfg_noc",
"core",
"iface",
"sleep",
"mock_utmi";
assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>,
<200000000>;
interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 14 IRQ_TYPE_EDGE_BOTH>,
<&pdc 15 IRQ_TYPE_EDGE_BOTH>,
<&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "dwc_usb3",
"pwr_event",
"hs_phy_irq",
"dp_hs_phy_irq",
"dm_hs_phy_irq",
"ss_phy_irq";
power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
resets = <&gcc GCC_USB30_PRIM_BCR>;
interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>;
interconnect-names = "usb-ddr", "apps-usb";
iommus = <&apps_smmu 0x40 0x0>;
phys = <&usb_hsphy>,
<&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy",
"usb3-phy";
snps,hird-threshold = /bits/ 8 <0x0>;
snps,usb2-gadget-lpm-disable;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
snps,is-utmi-l1-suspend;
snps,usb3_lpm_capable;
snps,usb2-lpm-disable;
snps,has-lpm-erratum;
tx-fifo-resize;
dma-coherent;
usb-role-switch;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usb_dwc3_hs: endpoint {
};
};
port@1 {
reg = <1>;
usb_dwc3_ss: endpoint {
remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
};
};
};
};
iris: video-codec@aa00000 {
compatible = "qcom,sm8750-iris";
reg = <0x0 0x0aa00000 0x0 0xf0000>;
clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
<&videocc VIDEO_CC_MVS0C_CLK>,
<&videocc VIDEO_CC_MVS0_CLK>,
<&gcc GCC_VIDEO_AXI1_CLK>,
<&videocc VIDEO_CC_MVS0C_FREERUN_CLK>,
<&videocc VIDEO_CC_MVS0_FREERUN_CLK>;
clock-names = "iface",
"core",
"vcodec0_core",
"iface1",
"core_freerun",
"vcodec0_core_freerun";
dma-coherent;
iommus = <&apps_smmu 0x1940 0>,
<&apps_smmu 0x1947 0>;
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
<&mmss_noc MASTER_VIDEO_MVP QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "cpu-cfg",
"video-mem";
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
memory-region = <&video_mem>;
operating-points-v2 = <&iris_opp_table>;
power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>,
<&videocc VIDEO_CC_MVS0_GDSC>,
<&rpmhpd RPMHPD_MXC>,
<&rpmhpd RPMHPD_MMCX>;
power-domain-names = "venus",
"vcodec0",
"mxc",
"mmcx";
resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
<&gcc GCC_VIDEO_AXI1_CLK_ARES>,
<&videocc VIDEO_CC_MVS0C_FREERUN_CLK_ARES>,
<&videocc VIDEO_CC_MVS0_FREERUN_CLK_ARES>;
reset-names = "bus0",
"bus1",
"core",
"vcodec0_core";
/*
* IRIS firmware is signed by vendors, only
* enable in boards where the proper signed firmware
* is available.
*/
status = "disabled";
iris_opp_table: opp-table {
compatible = "operating-points-v2";
opp-240000000 {
opp-hz = /bits/ 64 <240000000>;
required-opps = <&rpmhpd_opp_low_svs_d1>,
<&rpmhpd_opp_low_svs_d1>;
};
opp-338000000 {
opp-hz = /bits/ 64 <338000000>;
required-opps = <&rpmhpd_opp_low_svs>,
<&rpmhpd_opp_low_svs>;
};
opp-420000000 {
opp-hz = /bits/ 64 <420000000>;
required-opps = <&rpmhpd_opp_svs>,
<&rpmhpd_opp_svs>;
};
opp-444000000 {
opp-hz = /bits/ 64 <444000000>;
required-opps = <&rpmhpd_opp_svs_l1>,
<&rpmhpd_opp_svs_l1>;
};
opp-533333334 {
opp-hz = /bits/ 64 <533333334>;
required-opps = <&rpmhpd_opp_nom>,
<&rpmhpd_opp_nom>;
};
opp-570000000 {
opp-hz = /bits/ 64 <570000000>;
required-opps = <&rpmhpd_opp_nom_l1>,
<&rpmhpd_opp_nom_l1>;
};
opp-630000000 {
opp-hz = /bits/ 64 <630000000>;
required-opps = <&rpmhpd_opp_turbo>,
<&rpmhpd_opp_turbo>;
};
};
};
videocc: clock-controller@aaf0000 {
compatible = "qcom,sm8750-videocc";
reg = <0x0 0x0aaf0000 0x0 0x10000>;
clocks = <&bi_tcxo_div2>,
<&gcc GCC_VIDEO_AHB_CLK>;
power-domains = <&rpmhpd RPMHPD_MMCX>,
<&rpmhpd RPMHPD_MXC>;
required-opps = <&rpmhpd_opp_low_svs>,
<&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
pdc: interrupt-controller@b220000 {
compatible = "qcom,sm8750-pdc", "qcom,pdc";
reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>;
qcom,pdc-ranges = <0 745 51>, <51 527 47>,
<98 609 32>, <130 717 12>,
<142 251 5>, <147 796 16>;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupt-controller;
};
aoss_qmp: power-management@c300000 {
compatible = "qcom,sm8750-aoss-qmp", "qcom,aoss-qmp";
reg = <0x0 0x0c300000 0x0 0x400>;
interrupt-parent = <&ipcc>;
interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
#clock-cells = <0>;
};
sram@c3f0000 {
compatible = "qcom,rpmh-stats";
reg = <0x0 0x0c3f0000 0x0 0x400>;
qcom,qmp = <&aoss_qmp>;
};
spmi_bus: spmi@c400000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x0 0x0c400000 0x0 0x3000>,
<0x0 0x0c500000 0x0 0x400000>,
<0x0 0x0c440000 0x0 0x80000>,
<0x0 0x0c4c0000 0x0 0x10000>,
<0x0 0x0c42d000 0x0 0x4000>;
reg-names = "core",
"chnls",
"obsrvr",
"intr",
"cnfg";
interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "periph_irq";
qcom,ee = <0>;
qcom,channel = <0>;
qcom,bus-id = <0>;
interrupt-controller;
#interrupt-cells = <4>;
#address-cells = <2>;
#size-cells = <0>;
};
tlmm: pinctrl@f100000 {
compatible = "qcom,sm8750-tlmm";
reg = <0x0 0x0f100000 0x0 0x102000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 216>;
wakeup-parent = <&pdc>;
hub_i2c0_data_clk: hub-i2c0-data-clk-state {
/* SDA, SCL */
pins = "gpio64", "gpio65";
function = "i2chub0_se0";
drive-strength = <2>;
bias-pull-up;
};
hub_i2c1_data_clk: hub-i2c1-data-clk-state {
/* SDA, SCL */
pins = "gpio66", "gpio67";
function = "i2chub0_se1";
drive-strength = <2>;
bias-pull-up;
};
hub_i2c2_data_clk: hub-i2c2-data-clk-state {
/* SDA, SCL */
pins = "gpio68", "gpio69";
function = "i2chub0_se2";
drive-strength = <2>;
bias-pull-up;
};
hub_i2c3_data_clk: hub-i2c3-data-clk-state {
/* SDA, SCL */
pins = "gpio70", "gpio71";
function = "i2chub0_se3";
drive-strength = <2>;
bias-pull-up;
};
hub_i2c4_data_clk: hub-i2c4-data-clk-state {
/* SDA, SCL */
pins = "gpio72", "gpio73";
function = "i2chub0_se4";
drive-strength = <2>;
bias-pull-up;
};
hub_i2c5_data_clk: hub-i2c5-data-clk-state {
/* SDA, SCL */
pins = "gpio74", "gpio75";
function = "i2chub0_se5";
drive-strength = <2>;
bias-pull-up;
};
hub_i2c6_data_clk: hub-i2c6-data-clk-state {
/* SDA, SCL */
pins = "gpio76", "gpio77";
function = "i2chub0_se6";
drive-strength = <2>;
bias-pull-up;
};
hub_i2c7_data_clk: hub-i2c7-data-clk-state {
/* SDA, SCL */
pins = "gpio82", "gpio83";
function = "i2chub0_se7";
drive-strength = <2>;
bias-pull-up;
};
hub_i2c8_data_clk: hub-i2c8-data-clk-state {
/* SDA, SCL */
pins = "gpio206", "gpio207";
function = "i2chub0_se8";
drive-strength = <2>;
bias-pull-up;
};
hub_i2c9_data_clk: hub-i2c9-data-clk-state {
/* SDA, SCL */
pins = "gpio80", "gpio81";
function = "i2chub0_se9";
drive-strength = <2>;
bias-pull-up;
};
pcie0_default_state: pcie0-default-state {
perst-pins {
pins = "gpio102";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
clkreq-pins {
pins = "gpio103";
function = "pcie0_clk_req_n";
drive-strength = <2>;
bias-pull-up;
};
wake-pins {
pins = "gpio104";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
qup_i2c0_data_clk: qup-i2c0-data-clk-state {
/* SDA, SCL */
pins = "gpio32", "gpio33";
function = "qup1_se0";
drive-strength = <2>;
bias-pull-up;
};
qup_i2c1_data_clk: qup-i2c1-data-clk-state {
/* SDA, SCL */
pins = "gpio36", "gpio37";
function = "qup1_se1";
drive-strength = <2>;
bias-pull-up;
};
qup_i2c2_data_clk: qup-i2c2-data-clk-state {
/* SDA, SCL */
pins = "gpio40", "gpio41";
function = "qup1_se2";
drive-strength = <2>;
bias-pull-up;
};
qup_i2c3_data_clk: qup-i2c3-data-clk-state {
/* SDA, SCL */
pins = "gpio44", "gpio45";
function = "qup1_se3";
drive-strength = <2>;
bias-pull-up;
};
qup_i2c4_data_clk: qup-i2c4-data-clk-state {
/* SDA, SCL */
pins = "gpio48", "gpio49";
function = "qup1_se4";
drive-strength = <2>;
bias-pull-up;
};
qup_i2c5_data_clk: qup-i2c5-data-clk-state {
/* SDA, SCL */
pins = "gpio52", "gpio53";
function = "qup1_se5";
drive-strength = <2>;
bias-pull-up;
};
qup_i2c6_data_clk: qup-i2c6-data-clk-state {
/* SDA, SCL */
pins = "gpio56", "gpio57";
function = "qup1_se6";
drive-strength = <2>;
bias-pull-up;
};
qup_i2c8_data_clk: qup-i2c8-data-clk-state {
/* SDA, SCL */
pins = "gpio0", "gpio1";
function = "qup2_se0";
drive-strength = <2>;
bias-pull-up;
};
qup_i2c9_data_clk: qup-i2c9-data-clk-state {
/* SDA, SCL */
pins = "gpio4", "gpio5";
function = "qup2_se1";
drive-strength = <2>;
bias-pull-up;
};
qup_i2c10_data_clk: qup-i2c10-data-clk-state {
/* SDA, SCL */
pins = "gpio8", "gpio9";
function = "qup2_se2";
drive-strength = <2>;
bias-pull-up;
};
qup_i2c11_data_clk: qup-i2c11-data-clk-state {
/* SDA, SCL */
pins = "gpio12", "gpio13";
function = "qup2_se3";
drive-strength = <2>;
bias-pull-up;
};
qup_i2c12_data_clk: qup-i2c12-data-clk-state {
/* SDA, SCL */
pins = "gpio16", "gpio17";
function = "qup2_se4";
drive-strength = <2>;
bias-pull-up;
};
qup_i2c13_data_clk: qup-i2c13-data-clk-state {
/* SDA, SCL */
pins = "gpio20", "gpio21";
function = "qup2_se5";
drive-strength = <2>;
bias-pull-up;
};
qup_i2c15_data_clk: qup-i2c15-data-clk-state {
/* SDA, SCL */
pins = "gpio28", "gpio29";
function = "qup2_se7";
drive-strength = <2>;
bias-pull-up;
};
qup_spi0_cs: qup-spi0-cs-state {
pins = "gpio35";
function = "qup1_se0";
drive-strength = <6>;
bias-disable;
};
qup_spi0_data_clk: qup-spi0-data-clk-state {
/* MISO, MOSI, CLK */
pins = "gpio32", "gpio33", "gpio34";
function = "qup1_se0";
drive-strength = <6>;
bias-disable;
};
qup_spi1_cs: qup-spi1-cs-state {
pins = "gpio39";
function = "qup1_se1";
drive-strength = <6>;
bias-disable;
};
qup_spi1_data_clk: qup-spi1-data-clk-state {
/* MISO, MOSI, CLK */
pins = "gpio36", "gpio37", "gpio38";
function = "qup1_se1";
drive-strength = <6>;
bias-disable;
};
qup_spi2_cs: qup-spi2-cs-state {
pins = "gpio43";
function = "qup1_se2";
drive-strength = <6>;
bias-disable;
};
qup_spi2_data_clk: qup-spi2-data-clk-state {
/* MISO, MOSI, CLK */
pins = "gpio40", "gpio41", "gpio42";
function = "qup1_se2";
drive-strength = <6>;
bias-disable;
};
qup_spi3_cs: qup-spi3-cs-state {
pins = "gpio47";
function = "qup1_se3";
drive-strength = <6>;
bias-disable;
};
qup_spi3_data_clk: qup-spi3-data-clk-state {
/* MISO, MOSI, CLK */
pins = "gpio44", "gpio45", "gpio46";
function = "qup1_se3";
drive-strength = <6>;
bias-disable;
};
qup_spi4_cs: qup-spi4-cs-state {
pins = "gpio51";
function = "qup1_se4";
drive-strength = <6>;
bias-disable;
};
qup_spi4_data_clk: qup-spi4-data-clk-state {
/* MISO, MOSI, CLK */
pins = "gpio48", "gpio49", "gpio50";
function = "qup1_se4";
drive-strength = <6>;
bias-disable;
};
qup_spi5_cs: qup-spi5-cs-state {
pins = "gpio55";
function = "qup1_se5";
drive-strength = <6>;
bias-disable;
};
qup_spi5_data_clk: qup-spi5-data-clk-state {
/* MISO, MOSI, CLK */
pins = "gpio52", "gpio53", "gpio54";
function = "qup1_se5";
drive-strength = <6>;
bias-disable;
};
qup_spi6_cs: qup-spi6-cs-state {
pins = "gpio59";
function = "qup1_se6";
drive-strength = <6>;
bias-disable;
};
qup_spi6_data_clk: qup-spi6-data-clk-state {
/* MISO, MOSI, CLK */
pins = "gpio56", "gpio57", "gpio58";
function = "qup1_se6";
drive-strength = <6>;
bias-disable;
};
qup_spi8_cs: qup-spi8-cs-state {
pins = "gpio3";
function = "qup2_se0";
drive-strength = <6>;
bias-disable;
};
qup_spi8_data_clk: qup-spi8-data-clk-state {
/* MISO, MOSI, CLK */
pins = "gpio0", "gpio1", "gpio2";
function = "qup2_se0";
drive-strength = <6>;
bias-disable;
};
qup_spi9_cs: qup-spi9-cs-state {
pins = "gpio7";
function = "qup2_se1";
drive-strength = <6>;
bias-disable;
};
qup_spi9_data_clk: qup-spi9-data-clk-state {
/* MISO, MOSI, CLK */
pins = "gpio4", "gpio5", "gpio6";
function = "qup2_se1";
drive-strength = <6>;
bias-disable;
};
qup_spi10_cs: qup-spi10-cs-state {
pins = "gpio11";
function = "qup2_se2";
drive-strength = <6>;
bias-disable;
};
qup_spi10_data_clk: qup-spi10-data-clk-state {
/* MISO, MOSI, CLK */
pins = "gpio8", "gpio9", "gpio10";
function = "qup2_se2";
drive-strength = <6>;
bias-disable;
};
qup_spi11_cs: qup-spi11-cs-state {
pins = "gpio15";
function = "qup2_se3";
drive-strength = <6>;
bias-disable;
};
qup_spi11_data_clk: qup-spi11-data-clk-state {
/* MISO, MOSI, CLK */
pins = "gpio12", "gpio13", "gpio14";
function = "qup2_se3";
drive-strength = <6>;
bias-disable;
};
qup_spi12_cs: qup-spi12-cs-state {
pins = "gpio19";
function = "qup2_se4";
drive-strength = <6>;
bias-disable;
};
qup_spi12_data_clk: qup-spi12-data-clk-state {
/* MISO, MOSI, CLK */
pins = "gpio16", "gpio17", "gpio18";
function = "qup2_se4";
drive-strength = <6>;
bias-disable;
};
qup_spi13_cs: qup-spi13-cs-state {
pins = "gpio23";
function = "qup2_se5";
drive-strength = <6>;
bias-pull-up;
};
qup_spi13_data_clk: qup-spi13-data-clk-state {
/* MISO, MOSI, CLK */
pins = "gpio20", "gpio21", "gpio22";
function = "qup2_se5";
drive-strength = <6>;
bias-disable;
};
qup_spi15_cs: qup-spi15-cs-state {
pins = "gpio31";
function = "qup2_se7";
drive-strength = <6>;
bias-disable;
};
qup_spi15_data_clk: qup-spi15-data-clk-state {
/* MISO, MOSI, CLK */
pins = "gpio28", "gpio29", "gpio30";
function = "qup2_se7";
drive-strength = <6>;
bias-disable;
};
qup_uart7_default: qup-uart7-default-state {
/* TX, RX */
pins = "gpio62", "gpio63";
function = "qup1_se7";
drive-strength = <2>;
bias-disable;
};
qup_uart14_default: qup-uart14-default-state {
/* TX, RX */
pins = "gpio26", "gpio27";
function = "qup2_se6";
drive-strength = <2>;
bias-pull-up;
};
qup_uart14_cts_rts: qup-uart14-cts-rts-state {
/* CTS, RTS */
pins = "gpio24", "gpio25";
function = "qup2_se6";
drive-strength = <2>;
bias-pull-down;
};
sdc2_sleep: sdc2-sleep-state {
clk-pins {
pins = "sdc2_clk";
drive-strength = <2>;
bias-disable;
};
cmd-pins {
pins = "sdc2_cmd";
drive-strength = <2>;
bias-pull-up;
};
data-pins {
pins = "sdc2_data";
drive-strength = <2>;
bias-pull-up;
};
};
sdc2_default: sdc2-default-state {
clk-pins {
pins = "sdc2_clk";
drive-strength = <16>;
bias-disable;
};
cmd-pins {
pins = "sdc2_cmd";
drive-strength = <10>;
bias-pull-up;
};
data-pins {
pins = "sdc2_data";
drive-strength = <10>;
bias-pull-up;
};
};
};
tcsrcc: clock-controller@f204008 {
compatible = "qcom,sm8750-tcsr", "syscon";
reg = <0x0 0x0f204008 0x0 0x3004>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
#clock-cells = <1>;
#reset-cells = <1>;
};
stm@10002000 {
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0x0 0x10002000 0x0 0x1000>,
<0x0 0x37280000 0x0 0x180000>;
reg-names = "stm-base",
"stm-stimulus-base";
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
out-ports {
port {
stm_out: endpoint {
remote-endpoint = <&funnel_in0_in7>;
};
};
};
};
tpda@10004000 {
compatible = "qcom,coresight-tpda", "arm,primecell";
reg = <0x0 0x10004000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
tpda_qdss_in1: endpoint {
remote-endpoint = <&tpdm_spdm_out>;
};
};
};
out-ports {
port {
tpda_qdss_out: endpoint {
remote-endpoint = <&funnel_in0_in6>;
};
};
};
};
tpdm@1000f000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x1000f000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
out-ports {
port {
tpdm_spdm_out: endpoint {
remote-endpoint = <&tpda_qdss_in1>;
};
};
};
};
funnel@10041000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x0 0x10041000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
funnel_in0_in0: endpoint {
remote-endpoint = <&tn_ag_out>;
};
};
port@6 {
reg = <6>;
funnel_in0_in6: endpoint {
remote-endpoint = <&tpda_qdss_out>;
};
};
port@7 {
reg = <7>;
funnel_in0_in7: endpoint {
remote-endpoint = <&stm_out>;
};
};
};
out-ports {
port {
funnel_in0_out: endpoint {
remote-endpoint = <&funnel_aoss_in7>;
};
};
};
};
tpdm@10800000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x10800000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
out-ports {
port {
tpdm_modem0_out: endpoint {
remote-endpoint = <&tpda_modem_in0>;
};
};
};
};
tpda@10803000 {
compatible = "qcom,coresight-tpda", "arm,primecell";
reg = <0x0 0x10803000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
tpda_modem_in0: endpoint {
remote-endpoint = <&tpdm_modem0_out>;
};
};
port@1 {
reg = <1>;
tpda_modem_in1: endpoint {
remote-endpoint = <&tpdm_modem1_out>;
};
};
};
out-ports {
port {
tpda_modem_out: endpoint {
remote-endpoint = <&funnel_modem_dl_in0>;
};
};
};
};
funnel@10804000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x0 0x10804000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
port {
funnel_modem_dl_in0: endpoint {
remote-endpoint = <&tpda_modem_out>;
};
};
};
out-ports {
port {
funnel_modem_dl_out: endpoint {
remote-endpoint = <&tn_ag_in13>;
};
};
};
};
cti@1080b000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x1080b000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
};
tpdm@1082c000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x1082c000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
qcom,dsb-msrs-num = <32>;
out-ports {
port {
tpdm_gcc_out: endpoint {
remote-endpoint = <&tn_ag_in17>;
};
};
};
};
tpdm@10841000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x10841000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
qcom,cmb-msrs-num = <32>;
out-ports {
port {
tpdm_prng_out: endpoint {
remote-endpoint = <&tn_ag_in18>;
};
};
};
};
tpdm@1084e000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x1084e000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
out-ports {
port {
tpdm_mm_bcv_out: endpoint {
remote-endpoint = <&tpda_mm_in0>;
};
};
};
};
tpdm@1084f000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x1084f000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
out-ports {
port {
tpdm_mm_lmh_out: endpoint {
remote-endpoint = <&tpda_mm_in1>;
};
};
};
};
tpdm@10850000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x10850000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
out-ports {
port {
tpdm_mm_dpm_out: endpoint {
remote-endpoint = <&tpda_mm_in2>;
};
};
};
};
tpda@10851000 {
compatible = "qcom,coresight-tpda", "arm,primecell";
reg = <0x0 0x10851000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
tpda_mm_in0: endpoint {
remote-endpoint = <&tpdm_mm_bcv_out>;
};
};
port@1 {
reg = <1>;
tpda_mm_in1: endpoint {
remote-endpoint = <&tpdm_mm_lmh_out>;
};
};
port@2 {
reg = <2>;
tpda_mm_in2: endpoint {
remote-endpoint = <&tpdm_mm_dpm_out>;
};
};
};
out-ports {
port {
tpda_mm_out: endpoint {
remote-endpoint = <&tn_ag_in4>;
};
};
};
};
tpdm@10980000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x10980000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
out-ports {
port {
tpdm_cdsp_out: endpoint {
remote-endpoint = <&tpda_cdsp_in0>;
};
};
};
};
tpda@10986000 {
compatible = "qcom,coresight-tpda", "arm,primecell";
reg = <0x0 0x10986000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
tpda_cdsp_in0: endpoint {
remote-endpoint = <&tpdm_cdsp_out>;
};
};
port@1 {
reg = <1>;
tpda_cdsp_in1: endpoint {
remote-endpoint = <&tpdm_cdsp_llm_out>;
};
};
port@2 {
reg = <2>;
tpda_cdsp_in2: endpoint {
remote-endpoint = <&tpdm_cdsp_llm2_out>;
};
};
};
out-ports {
port {
tpda_cdsp_out: endpoint {
remote-endpoint = <&funnel_cdsp_in0>;
};
};
};
};
funnel@10987000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x0 0x10987000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
port {
funnel_cdsp_in0: endpoint {
remote-endpoint = <&tpda_cdsp_out>;
};
};
};
out-ports {
port {
funnel_cdsp_out: endpoint {
remote-endpoint = <&tn_ag_in16>;
};
};
};
};
cti@1098b000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x1098b000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
};
tpdm@109a3000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x109a3000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
qcom,cmb-msrs-num = <32>;
qcom,dsb-msrs-num = <32>;
out-ports {
port {
tpdm_pmu_out: endpoint {
remote-endpoint = <&tn_ag_in29>;
};
};
};
};
tpdm@109a4000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x109a4000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
qcom,cmb-msrs-num = <32>;
out-ports {
port {
tpdm_ipcc_cmb_out: endpoint {
remote-endpoint = <&tn_ag_in28>;
};
};
};
};
tpdm@109a5000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x109a5000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
qcom,dsb-msrs-num = <32>;
out-ports {
port {
tpdm_dl_mm_out: endpoint {
remote-endpoint = <&tn_ag_in25>;
};
};
};
};
tpdm@109a6000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x109a6000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
qcom,dsb-msrs-num = <32>;
out-ports {
port {
tpdm_north_dsb_out: endpoint {
remote-endpoint = <&tn_ag_in26>;
};
};
};
};
tpdm@109a7000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x109a7000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
qcom,dsb-msrs-num = <32>;
out-ports {
port {
tpdm_south_dsb_out: endpoint {
remote-endpoint = <&tn_ag_in27>;
};
};
};
};
tpdm@109a8000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x109a8000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
qcom,cmb-msrs-num = <32>;
out-ports {
port {
tpdm_rdpm_cmb0_out: endpoint {
remote-endpoint = <&tn_ag_in30>;
};
};
};
};
tpdm@109a9000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x109a9000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
qcom,cmb-msrs-num = <32>;
out-ports {
port {
tpdm_rdpm_cmb1_out: endpoint {
remote-endpoint = <&tn_ag_in31>;
};
};
};
};
tpdm@109aa000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x109aa000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
qcom,cmb-msrs-num = <32>;
out-ports {
port {
tpdm_rdpm_cmb2_out: endpoint {
remote-endpoint = <&tn_ag_in32>;
};
};
};
};
tn@109ab000 {
compatible = "qcom,coresight-tnoc", "arm,primecell";
reg = <0x0 0x109ab000 0x0 0x4200>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@4 {
reg = <4>;
tn_ag_in4: endpoint {
remote-endpoint = <&tpda_mm_out>;
};
};
port@d {
reg = <0xd>;
tn_ag_in13: endpoint {
remote-endpoint = <&funnel_modem_dl_out>;
};
};
port@10 {
reg = <0x10>;
tn_ag_in16: endpoint {
remote-endpoint = <&funnel_cdsp_out>;
};
};
port@11 {
reg = <0x11>;
tn_ag_in17: endpoint {
remote-endpoint = <&tpdm_gcc_out>;
};
};
port@12 {
reg = <0x12>;
tn_ag_in18: endpoint {
remote-endpoint = <&tpdm_prng_out>;
};
};
port@13 {
reg = <0x13>;
tn_ag_in19: endpoint {
remote-endpoint = <&tpdm_qm_out>;
};
};
port@19 {
reg = <0x19>;
tn_ag_in25: endpoint {
remote-endpoint = <&tpdm_dl_mm_out>;
};
};
port@1a {
reg = <0x1a>;
tn_ag_in26: endpoint {
remote-endpoint = <&tpdm_north_dsb_out>;
};
};
port@1b {
reg = <0x1b>;
tn_ag_in27: endpoint {
remote-endpoint = <&tpdm_south_dsb_out>;
};
};
port@1c {
reg = <0x1c>;
tn_ag_in28: endpoint {
remote-endpoint = <&tpdm_ipcc_cmb_out>;
};
};
port@1d {
reg = <0x1d>;
tn_ag_in29: endpoint {
remote-endpoint = <&tpdm_pmu_out>;
};
};
port@1e {
reg = <0x1e>;
tn_ag_in30: endpoint {
remote-endpoint = <&tpdm_rdpm_cmb0_out>;
};
};
port@1f {
reg = <0x1f>;
tn_ag_in31: endpoint {
remote-endpoint = <&tpdm_rdpm_cmb1_out>;
};
};
port@20 {
reg = <0x20>;
tn_ag_in32: endpoint {
remote-endpoint = <&tpdm_rdpm_cmb2_out>;
};
};
};
out-ports {
port {
tn_ag_out: endpoint {
remote-endpoint = <&funnel_in0_in0>;
};
};
};
};
tpdm@109d0000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x109d0000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
qcom,dsb-msrs-num = <32>;
out-ports {
port {
tpdm_qm_out: endpoint {
remote-endpoint = <&tn_ag_in19>;
};
};
};
};
funnel@10b04000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x0 0x10b04000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@6 {
reg = <6>;
funnel_aoss_in6: endpoint {
remote-endpoint = <&tpda_aoss_out>;
};
};
port@7 {
reg = <7>;
funnel_aoss_in7: endpoint {
remote-endpoint = <&funnel_in0_out>;
};
};
};
out-ports {
port {
funnel_aoss_out: endpoint {
remote-endpoint = <&tmc_etf_in>;
};
};
};
};
tmc@10b05000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0x0 0x10b05000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
port {
tmc_etf_in: endpoint {
remote-endpoint = <&funnel_aoss_out>;
};
};
};
};
tpda@10b08000 {
compatible = "qcom,coresight-tpda", "arm,primecell";
reg = <0x0 0x10b08000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
tpda_aoss_in0: endpoint {
remote-endpoint = <&tpdm_swao_prio0_out>;
};
};
port@1 {
reg = <1>;
tpda_aoss_in1: endpoint {
remote-endpoint = <&tpdm_swao_prio1_out>;
};
};
port@2 {
reg = <2>;
tpda_aoss_in2: endpoint {
remote-endpoint = <&tpdm_swao_prio2_out>;
};
};
port@3 {
reg = <3>;
tpda_aoss_in3: endpoint {
remote-endpoint = <&tpdm_swao_prio3_out>;
};
};
port@4 {
reg = <4>;
tpda_aoss_in4: endpoint {
remote-endpoint =<&tpdm_swao_out>;
};
};
};
out-ports {
port {
tpda_aoss_out: endpoint {
remote-endpoint = <&funnel_aoss_in6>;
};
};
};
};
tpdm@10b09000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x10b09000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
out-ports {
port {
tpdm_swao_prio0_out: endpoint {
remote-endpoint = <&tpda_aoss_in0>;
};
};
};
};
tpdm@10b0a000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x10b0a000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
out-ports {
port {
tpdm_swao_prio1_out: endpoint {
remote-endpoint = <&tpda_aoss_in1>;
};
};
};
};
tpdm@10b0b000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x10b0b000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
out-ports {
port {
tpdm_swao_prio2_out: endpoint {
remote-endpoint = <&tpda_aoss_in2>;
};
};
};
};
tpdm@10b0c000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x10b0c000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
out-ports {
port {
tpdm_swao_prio3_out: endpoint {
remote-endpoint = <&tpda_aoss_in3>;
};
};
};
};
tpdm@10b0d000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x10b0d000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
out-ports {
port {
tpdm_swao_out: endpoint {
remote-endpoint = <&tpda_aoss_in4>;
};
};
};
};
apps_smmu: iommu@15000000 {
compatible = "qcom,sm8750-smmu-500", "qcom,smmu-500", "arm,mmu-500";
reg = <0x0 0x15000000 0x0 0x100000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <2>;
#global-interrupts = <1>;
dma-coherent;
};
intc: interrupt-controller@16000000 {
compatible = "arm,gic-v3";
reg = <0x0 0x16000000 0x0 0x10000>,
<0x0 0x16080000 0x0 0x200000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <3>;
interrupt-controller;
#redistributor-regions = <1>;
redistributor-stride = <0x0 0x40000>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
gic_its: msi-controller@16040000 {
compatible = "arm,gic-v3-its";
reg = <0x0 0x16040000 0x0 0x20000>;
msi-controller;
#msi-cells = <1>;
};
};
pcie0: pcie@1c00000 {
device_type = "pci";
compatible = "qcom,pcie-sm8750", "qcom,pcie-sm8550";
reg = <0x0 0x01c00000 0x0 0x3000>,
<0x0 0x40000000 0x0 0xf1d>,
<0x0 0x40000f20 0x0 0xa8>,
<0x0 0x40001000 0x0 0x1000>,
<0x0 0x40100000 0x0 0x100000>,
<0x0 0x01c03000 0x0 0x1000>;
reg-names = "parf",
"dbi",
"elbi",
"atu",
"config",
"mhi";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x23d00000>,
<0x03000000 0x4 0x00000000 0x4 0x00000000 0x3 0x00000000>;
bus-range = <0x00 0xff>;
dma-coherent;
linux,pci-domain = <0>;
msi-map = <0x0 &gic_its 0x1400 0x1>,
<0x100 &gic_its 0x1401 0x1>;
msi-map-mask = <0xff00>;
num-lanes = <2>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0",
"msi1",
"msi2",
"msi3",
"msi4",
"msi5",
"msi6",
"msi7",
"global";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
<&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
<&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
<&gcc GCC_CNOC_PCIE_SF_AXI_CLK>;
clock-names = "aux",
"cfg",
"bus_master",
"bus_slave",
"slave_q2a",
"ddrss_sf_tbu",
"noc_aggr",
"cnoc_sf_axi";
interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "pcie-mem",
"cpu-pcie";
iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
<0x100 &apps_smmu 0x1401 0x1>;
resets = <&gcc GCC_PCIE_0_BCR>;
reset-names = "pci";
power-domains = <&gcc GCC_PCIE_0_GDSC>;
operating-points-v2 = <&pcie0_opp_table>;
status = "disabled";
pcie0_opp_table: opp-table {
compatible = "operating-points-v2";
/* GEN 1 x1 */
opp-2500000 {
opp-hz = /bits/ 64 <2500000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <250000 1>;
};
/* GEN 1 x2 and GEN 2 x1 */
opp-5000000 {
opp-hz = /bits/ 64 <5000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <500000 1>;
};
/* GEN 2 x2 */
opp-10000000 {
opp-hz = /bits/ 64 <10000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <1000000 1>;
};
/* GEN 3 x1 */
opp-8000000 {
opp-hz = /bits/ 64 <8000000>;
required-opps = <&rpmhpd_opp_nom>;
opp-peak-kBps = <984500 1>;
};
/* GEN 3 x2 */
opp-16000000 {
opp-hz = /bits/ 64 <16000000>;
required-opps = <&rpmhpd_opp_nom>;
opp-peak-kBps = <1969000 1>;
};
};
pcieport0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
phys = <&pcie0_phy>;
};
};
pcie0_phy: phy@1c06000 {
compatible = "qcom,sm8750-qmp-gen3x2-pcie-phy";
reg = <0 0x01c06000 0 0x2000>;
clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
<&tcsrcc TCSR_PCIE_0_CLKREF_EN>,
<&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
<&gcc GCC_PCIE_0_PIPE_CLK>;
clock-names = "aux",
"cfg_ahb",
"ref",
"rchng",
"pipe";
assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
assigned-clock-rates = <100000000>;
resets = <&gcc GCC_PCIE_0_PHY_BCR>;
reset-names = "phy";
power-domains = <&gcc GCC_PCIE_0_PHY_GDSC>;
#clock-cells = <0>;
clock-output-names = "pcie0_pipe_clk";
#phy-cells = <0>;
status = "disabled";
};
ufs_mem_phy: phy@1d80000 {
compatible = "qcom,sm8750-qmp-ufs-phy";
reg = <0x0 0x01d80000 0x0 0x2000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
<&tcsrcc TCSR_UFS_CLKREF_EN>;
clock-names = "ref",
"ref_aux",
"qref";
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
power-domains = <&gcc GCC_UFS_MEM_PHY_GDSC>;
#clock-cells = <1>;
#phy-cells = <0>;
status = "disabled";
};
ufs_mem_hc: ufs@1d84000 {
compatible = "qcom,sm8750-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
reg = <0x0 0x01d84000 0x0 0x3000>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_UFS_PHY_AHB_CLK>,
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
<&rpmhcc RPMH_LN_BB_CLK3>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
clock-names = "core_clk",
"bus_aggr_clk",
"iface_clk",
"core_clk_unipro",
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk",
"rx_lane1_sync_clk";
operating-points-v2 = <&ufs_opp_table>;
resets = <&gcc GCC_UFS_PHY_BCR>;
reset-names = "rst";
interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
interconnect-names = "ufs-ddr",
"cpu-ufs";
power-domains = <&gcc GCC_UFS_PHY_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
iommus = <&apps_smmu 0x60 0>;
dma-coherent;
lanes-per-direction = <2>;
phys = <&ufs_mem_phy>;
phy-names = "ufsphy";
#reset-cells = <1>;
status = "disabled";
ufs_opp_table: opp-table {
compatible = "operating-points-v2";
opp-100000000 {
opp-hz = /bits/ 64 <100000000>,
/bits/ 64 <0>,
/bits/ 64 <0>,
/bits/ 64 <100000000>,
/bits/ 64 <0>,
/bits/ 64 <0>,
/bits/ 64 <0>,
/bits/ 64 <0>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-403000000 {
opp-hz = /bits/ 64 <403000000>,
/bits/ 64 <0>,
/bits/ 64 <0>,
/bits/ 64 <403000000>,
/bits/ 64 <0>,
/bits/ 64 <0>,
/bits/ 64 <0>,
/bits/ 64 <0>;
required-opps = <&rpmhpd_opp_nom>;
};
};
};
cpucp_mbox: mailbox@16430000 {
compatible = "qcom,sm8750-cpucp-mbox", "qcom,x1e80100-cpucp-mbox";
reg = <0x0 0x16430000 0x0 0x8000>, <0x0 0x17830000 0x0 0x8000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <1>;
};
apps_rsc: rsc@16500000 {
compatible = "qcom,rpmh-rsc";
reg = <0x0 0x16500000 0x0 0x10000>,
<0x0 0x16510000 0x0 0x10000>,
<0x0 0x16520000 0x0 0x10000>;
reg-names = "drv-0",
"drv-1",
"drv-2";
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
qcom,tcs-offset = <0xd00>;
qcom,drv-id = <2>;
qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
<WAKE_TCS 2>, <CONTROL_TCS 0>;
label = "apps_rsc";
power-domains = <&system_pd>;
apps_bcm_voter: bcm-voter {
compatible = "qcom,bcm-voter";
};
rpmhcc: clock-controller {
compatible = "qcom,sm8750-rpmh-clk";
clocks = <&xo_board>;
clock-names = "xo";
#clock-cells = <1>;
};
rpmhpd: power-controller {
compatible = "qcom,sm8750-rpmhpd";
operating-points-v2 = <&rpmhpd_opp_table>;
#power-domain-cells = <1>;
rpmhpd_opp_table: opp-table {
compatible = "operating-points-v2";
rpmhpd_opp_ret: opp-16 {
opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
};
rpmhpd_opp_min_svs: opp-48 {
opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
};
rpmhpd_opp_low_svs_d3: opp-50 {
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D3>;
};
rpmhpd_opp_low_svs_d2: opp-52 {
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
};
rpmhpd_opp_low_svs_d1: opp-56 {
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
};
rpmhpd_opp_low_svs_d0: opp-60 {
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
};
rpmhpd_opp_low_svs: opp-64 {
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
};
rpmhpd_opp_low_svs_l1: opp-80 {
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
};
rpmhpd_opp_svs: opp-128 {
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
};
rpmhpd_opp_svs_l0: opp-144 {
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
};
rpmhpd_opp_svs_l1: opp-192 {
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
};
rpmhpd_opp_svs_l2: opp-224 {
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
};
rpmhpd_opp_nom: opp-256 {
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
};
rpmhpd_opp_nom_l1: opp-320 {
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
};
rpmhpd_opp_nom_l2: opp-336 {
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
};
rpmhpd_opp_turbo: opp-384 {
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
};
rpmhpd_opp_turbo_l1: opp-416 {
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
};
rpmhpd_opp_turbo_l2: opp-432 {
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L2>;
};
rpmhpd_opp_turbo_l3: opp-448 {
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
};
rpmhpd_opp_turbo_l4: opp-452 {
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>;
};
rpmhpd_opp_super_turbo_no_cpr: opp-480 {
opp-level =
<RPMH_REGULATOR_LEVEL_SUPER_TURBO_NO_CPR>;
};
};
};
};
timer@16800000 {
compatible = "arm,armv7-timer-mem";
reg = <0x0 0x16800000 0x0 0x1000>;
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0 0 0x20000000>;
frame@16801000 {
reg = <0x0 0x16801000 0x1000>,
<0x0 0x16802000 0x1000>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <0>;
};
frame@16803000 {
reg = <0x0 0x16803000 0x1000>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <1>;
status = "disabled";
};
frame@16805000 {
reg = <0x0 0x16805000 0x1000>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <2>;
status = "disabled";
};
frame@16807000 {
reg = <0x0 0x16807000 0x1000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <3>;
status = "disabled";
};
frame@16809000 {
reg = <0x0 0x16809000 0x1000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <4>;
status = "disabled";
};
frame@1680b000 {
reg = <0x0 0x1680b000 0x1000>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <5>;
status = "disabled";
};
frame@1680d000 {
reg = <0x0 0x1680d000 0x1000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <6>;
status = "disabled";
};
};
sram: sram@17b4e000 {
compatible = "mmio-sram";
reg = <0x0 0x17b4e000 0x0 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x17b4e000 0x400>;
cpu_scp_lpri0: scp-sram-section@0 {
compatible = "arm,scmi-shmem";
reg = <0x0 0x200>;
};
cpu_scp_lpri1: scp-sram-section@200 {
compatible = "arm,scmi-shmem";
reg = <0x200 0x200>;
};
};
/* cluster0 */
pmu@240b3400 {
compatible = "qcom,sm8750-cpu-bwmon", "qcom,sdm845-bwmon";
reg = <0x0 0x240b3400 0x0 0x600>;
interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
operating-points-v2 = <&cpu_bwmon_opp_table>;
nonposted-mmio;
cpu_bwmon_opp_table: opp-table {
compatible = "operating-points-v2";
opp-0 {
opp-peak-kBps = <800000>;
};
opp-1 {
opp-peak-kBps = <2188000>;
};
opp-2 {
opp-peak-kBps = <5414400>;
};
opp-3 {
opp-peak-kBps = <6220800>;
};
opp-4 {
opp-peak-kBps = <6835200>;
};
opp-5 {
opp-peak-kBps = <8371200>;
};
opp-6 {
opp-peak-kBps = <10944000>;
};
opp-7 {
opp-peak-kBps = <12748800>;
};
opp-8 {
opp-peak-kBps = <14745600>;
};
opp-9 {
opp-peak-kBps = <16896000>;
};
opp-10 {
opp-peak-kBps = <19046400>;
};
};
};
/* cluster1 */
pmu@240b7400 {
compatible = "qcom,sm8750-cpu-bwmon", "qcom,sdm845-bwmon";
reg = <0x0 0x240b7400 0x0 0x600>;
interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
operating-points-v2 = <&cpu_bwmon_opp_table>;
};
gem_noc: interconnect@24100000 {
compatible = "qcom,sm8750-gem-noc";
reg = <0x0 0x24100000 0x0 0x14b080>;
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <2>;
};
system-cache-controller@24800000 {
compatible = "qcom,sm8750-llcc";
reg = <0x0 0x24800000 0x0 0x200000>,
<0x0 0x25800000 0x0 0x200000>,
<0x0 0x24c00000 0x0 0x200000>,
<0x0 0x25c00000 0x0 0x200000>,
<0x0 0x26800000 0x0 0x200000>,
<0x0 0x26c00000 0x0 0x200000>;
reg-names = "llcc0_base",
"llcc1_base",
"llcc2_base",
"llcc3_base",
"llcc_broadcast_base",
"llcc_broadcast_and_base";
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
};
nsp_noc: interconnect@320c0000 {
compatible = "qcom,sm8750-nsp-noc";
reg = <0x0 0x320c0000 0x0 0x13080>;
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <2>;
};
remoteproc_cdsp: remoteproc@32300000 {
compatible = "qcom,sm8750-cdsp-pas", "qcom,sm8650-cdsp-pas";
reg = <0x0 0x32300000 0x0 0x10000>;
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 7 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog",
"fatal",
"ready",
"handover",
"stop-ack",
"shutdown-ack";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
power-domains = <&rpmhpd RPMHPD_CX>,
<&rpmhpd RPMHPD_MXC>,
<&rpmhpd RPMHPD_NSP>;
power-domain-names = "cx",
"mxc",
"nsp";
memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>, <&global_sync_mem>;
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&smp2p_cdsp_out 0>;
qcom,smem-state-names = "stop";
status = "disabled";
glink-edge {
interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_CDSP
IPCC_MPROC_SIGNAL_GLINK_QMP>;
qcom,remote-pid = <5>;
label = "cdsp";
fastrpc {
compatible = "qcom,fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
label = "cdsp";
qcom,non-secure-domain;
#address-cells = <1>;
#size-cells = <0>;
compute-cb@1 {
compatible = "qcom,fastrpc-compute-cb";
reg = <1>;
iommus = <&apps_smmu 0x19c1 0x0>,
<&apps_smmu 0x0c21 0x0>,
<&apps_smmu 0x0c01 0x40>;
dma-coherent;
};
compute-cb@2 {
compatible = "qcom,fastrpc-compute-cb";
reg = <2>;
iommus = <&apps_smmu 0x1962 0x0>,
<&apps_smmu 0x0c02 0x20>,
<&apps_smmu 0x0c42 0x0>,
<&apps_smmu 0x19c2 0x0>;
dma-coherent;
};
compute-cb@3 {
compatible = "qcom,fastrpc-compute-cb";
reg = <3>;
iommus = <&apps_smmu 0x1963 0x0>,
<&apps_smmu 0x0c23 0x0>,
<&apps_smmu 0x0c03 0x40>,
<&apps_smmu 0x19c3 0x0>;
dma-coherent;
};
compute-cb@4 {
compatible = "qcom,fastrpc-compute-cb";
reg = <4>;
iommus = <&apps_smmu 0x1964 0x0>,
<&apps_smmu 0x0c24 0x0>,
<&apps_smmu 0x0c04 0x40>,
<&apps_smmu 0x19c4 0x0>;
dma-coherent;
};
compute-cb@5 {
compatible = "qcom,fastrpc-compute-cb";
reg = <5>;
iommus = <&apps_smmu 0x1965 0x0>,
<&apps_smmu 0x0c25 0x0>,
<&apps_smmu 0x0c05 0x40>,
<&apps_smmu 0x19c5 0x0>;
dma-coherent;
};
compute-cb@6 {
compatible = "qcom,fastrpc-compute-cb";
reg = <6>;
iommus = <&apps_smmu 0x1966 0x0>,
<&apps_smmu 0x0c06 0x20>,
<&apps_smmu 0x0c46 0x0>,
<&apps_smmu 0x19c6 0x0>;
dma-coherent;
};
compute-cb@7 {
compatible = "qcom,fastrpc-compute-cb";
reg = <7>;
iommus = <&apps_smmu 0x1967 0x0>,
<&apps_smmu 0x0c27 0x0>,
<&apps_smmu 0x0c07 0x40>,
<&apps_smmu 0x19c7 0x0>;
dma-coherent;
};
compute-cb@8 {
compatible = "qcom,fastrpc-compute-cb";
reg = <8>;
iommus = <&apps_smmu 0x1968 0x0>,
<&apps_smmu 0x0c08 0x20>,
<&apps_smmu 0x0c48 0x0>,
<&apps_smmu 0x19c8 0x0>;
dma-coherent;
};
/* note: secure cb9 in downstream */
compute-cb@12 {
compatible = "qcom,fastrpc-compute-cb";
reg = <12>;
iommus = <&apps_smmu 0x196c 0x0>,
<&apps_smmu 0x0c2c 0x20>,
<&apps_smmu 0x0c0c 0x40>,
<&apps_smmu 0x19cc 0x0>;
dma-coherent;
};
compute-cb@13 {
compatible = "qcom,fastrpc-compute-cb";
reg = <13>;
iommus = <&apps_smmu 0x196d 0x0>,
<&apps_smmu 0x0c0d 0x20>,
<&apps_smmu 0x0c2e 0x0>,
<&apps_smmu 0x0c4d 0x0>,
<&apps_smmu 0x19cd 0x0>;
dma-coherent;
};
compute-cb@14 {
compatible = "qcom,fastrpc-compute-cb";
reg = <14>;
iommus = <&apps_smmu 0x196e 0x0>,
<&apps_smmu 0x0c0e 0x20>,
<&apps_smmu 0x19ce 0x0>;
dma-coherent;
};
};
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
tpdm-cdsp-llm {
compatible = "qcom,coresight-static-tpdm";
qcom,cmb-element-bits = <32>;
out-ports {
port {
tpdm_cdsp_llm_out: endpoint {
remote-endpoint = <&tpda_cdsp_in1>;
};
};
};
};
tpdm-cdsp-llm2 {
compatible = "qcom,coresight-static-tpdm";
qcom,cmb-element-bits = <32>;
out-ports {
port {
tpdm_cdsp_llm2_out: endpoint {
remote-endpoint = <&tpda_cdsp_in2>;
};
};
};
};
tpdm-modem1 {
compatible = "qcom,coresight-static-tpdm";
qcom,dsb-element-bits = <32>;
out-ports {
port {
tpdm_modem1_out: endpoint {
remote-endpoint = <&tpda_modem_in1>;
};
};
};
};
};