| // SPDX-License-Identifier: GPL-2.0-only |
| /* |
| * Copyright (c) 2018, Craig Tatlor. |
| * Copyright (c) 2020, Alexey Minnekhanov <alexey.min@gmail.com> |
| * Copyright (c) 2020, AngeloGioacchino Del Regno <kholk11@gmail.com> |
| * Copyright (c) 2020, Konrad Dybcio <konradybcio@gmail.com> |
| * Copyright (c) 2020, Martin Botka <martin.botka1@gmail.com> |
| */ |
| |
| #include "sdm630.dtsi" |
| |
| /delete-node/ &buffer_mem; |
| |
| / { |
| smp2p-cdsp { |
| compatible = "qcom,smp2p"; |
| qcom,smem = <94>, <432>; |
| interrupts = <GIC_SPI 514 IRQ_TYPE_EDGE_RISING>; |
| mboxes = <&apcs_glb 30>; |
| qcom,local-pid = <0>; |
| qcom,remote-pid = <5>; |
| |
| cdsp_smp2p_out: master-kernel { |
| qcom,entry-name = "master-kernel"; |
| #qcom,smem-state-cells = <1>; |
| }; |
| |
| cdsp_smp2p_in: slave-kernel { |
| qcom,entry-name = "slave-kernel"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| }; |
| |
| reserved-memory { |
| cdsp_region: cdsp@94a00000 { |
| reg = <0x0 0x94a00000 0x00 0x600000>; |
| no-map; |
| }; |
| }; |
| }; |
| |
| &adreno_gpu { |
| compatible = "qcom,adreno-512.0", "qcom,adreno"; |
| operating-points-v2 = <&gpu_sdm660_opp_table>; |
| |
| gpu_sdm660_opp_table: opp-table { |
| compatible = "operating-points-v2"; |
| |
| /* |
| * 775MHz is only available on the highest speed bin |
| * Though it cannot be used for now due to interconnect |
| * framework not supporting multiple frequencies |
| * at the same opp-level |
| |
| opp-750000000 { |
| opp-hz = /bits/ 64 <750000000>; |
| opp-level = <RPM_SMD_LEVEL_TURBO>; |
| opp-peak-kBps = <5412000>; |
| opp-supported-hw = <0xCHECKME>; |
| }; |
| |
| * These OPPs are correct, but we are lacking support for the |
| * GPU regulator. Hence, disable them for now to prevent the |
| * platform from hanging on high graphics loads. |
| |
| opp-700000000 { |
| opp-hz = /bits/ 64 <700000000>; |
| opp-level = <RPM_SMD_LEVEL_TURBO>; |
| opp-peak-kBps = <5184000>; |
| opp-supported-hw = <0xff>; |
| }; |
| |
| opp-647000000 { |
| opp-hz = /bits/ 64 <647000000>; |
| opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; |
| opp-peak-kBps = <4068000>; |
| opp-supported-hw = <0xff>; |
| }; |
| |
| opp-588000000 { |
| opp-hz = /bits/ 64 <588000000>; |
| opp-level = <RPM_SMD_LEVEL_NOM>; |
| opp-peak-kBps = <3072000>; |
| opp-supported-hw = <0xff>; |
| }; |
| |
| opp-465000000 { |
| opp-hz = /bits/ 64 <465000000>; |
| opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; |
| opp-peak-kBps = <2724000>; |
| opp-supported-hw = <0xff>; |
| }; |
| |
| opp-370000000 { |
| opp-hz = /bits/ 64 <370000000>; |
| opp-level = <RPM_SMD_LEVEL_SVS>; |
| opp-peak-kBps = <2188000>; |
| opp-supported-hw = <0xff>; |
| }; |
| */ |
| |
| opp-266000000 { |
| opp-hz = /bits/ 64 <266000000>; |
| opp-level = <RPM_SMD_LEVEL_LOW_SVS>; |
| opp-peak-kBps = <1648000>; |
| opp-supported-hw = <0xff>; |
| }; |
| |
| opp-160000000 { |
| opp-hz = /bits/ 64 <160000000>; |
| opp-level = <RPM_SMD_LEVEL_MIN_SVS>; |
| opp-peak-kBps = <1200000>; |
| opp-supported-hw = <0xff>; |
| }; |
| }; |
| }; |
| |
| &cpu0 { |
| compatible = "qcom,kryo260"; |
| capacity-dmips-mhz = <1024>; |
| /delete-property/ operating-points-v2; |
| }; |
| |
| &cpu1 { |
| compatible = "qcom,kryo260"; |
| capacity-dmips-mhz = <1024>; |
| /delete-property/ operating-points-v2; |
| }; |
| |
| &cpu2 { |
| compatible = "qcom,kryo260"; |
| capacity-dmips-mhz = <1024>; |
| /delete-property/ operating-points-v2; |
| }; |
| |
| &cpu3 { |
| compatible = "qcom,kryo260"; |
| capacity-dmips-mhz = <1024>; |
| /delete-property/ operating-points-v2; |
| }; |
| |
| &cpu4 { |
| compatible = "qcom,kryo260"; |
| capacity-dmips-mhz = <640>; |
| /delete-property/ operating-points-v2; |
| }; |
| |
| &cpu5 { |
| compatible = "qcom,kryo260"; |
| capacity-dmips-mhz = <640>; |
| /delete-property/ operating-points-v2; |
| }; |
| |
| &cpu6 { |
| compatible = "qcom,kryo260"; |
| capacity-dmips-mhz = <640>; |
| /delete-property/ operating-points-v2; |
| }; |
| |
| &cpu7 { |
| compatible = "qcom,kryo260"; |
| capacity-dmips-mhz = <640>; |
| /delete-property/ operating-points-v2; |
| }; |
| |
| &gcc { |
| compatible = "qcom,gcc-sdm660"; |
| }; |
| |
| &gpucc { |
| compatible = "qcom,gpucc-sdm660"; |
| }; |
| |
| &mdp { |
| compatible = "qcom,sdm660-mdp5", "qcom,mdp5"; |
| |
| ports { |
| port@1 { |
| reg = <1>; |
| mdp5_intf2_out: endpoint { |
| remote-endpoint = <&mdss_dsi1_in>; |
| }; |
| }; |
| }; |
| }; |
| |
| &mdss { |
| mdss_dsi1: dsi@c996000 { |
| compatible = "qcom,sdm660-dsi-ctrl", |
| "qcom,mdss-dsi-ctrl"; |
| reg = <0x0c996000 0x400>; |
| reg-names = "dsi_ctrl"; |
| |
| /* DSI1 shares the OPP table with DSI0 */ |
| operating-points-v2 = <&dsi_opp_table>; |
| power-domains = <&rpmpd RPMPD_VDDCX>; |
| |
| interrupt-parent = <&mdss>; |
| interrupts = <5>; |
| |
| assigned-clocks = <&mmcc BYTE1_CLK_SRC>, |
| <&mmcc PCLK1_CLK_SRC>; |
| assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, |
| <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; |
| |
| clocks = <&mmcc MDSS_MDP_CLK>, |
| <&mmcc MDSS_BYTE1_CLK>, |
| <&mmcc MDSS_BYTE1_INTF_CLK>, |
| <&mmcc MNOC_AHB_CLK>, |
| <&mmcc MDSS_AHB_CLK>, |
| <&mmcc MDSS_AXI_CLK>, |
| <&mmcc MISC_AHB_CLK>, |
| <&mmcc MDSS_PCLK1_CLK>, |
| <&mmcc MDSS_ESC1_CLK>; |
| clock-names = "mdp_core", |
| "byte", |
| "byte_intf", |
| "mnoc", |
| "iface", |
| "bus", |
| "core_mmss", |
| "pixel", |
| "core"; |
| |
| phys = <&mdss_dsi1_phy>; |
| |
| status = "disabled"; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| mdss_dsi1_in: endpoint { |
| remote-endpoint = <&mdp5_intf2_out>; |
| }; |
| }; |
| |
| port@1 { |
| reg = <1>; |
| mdss_dsi1_out: endpoint { |
| }; |
| }; |
| }; |
| }; |
| |
| mdss_dsi1_phy: phy@c996400 { |
| compatible = "qcom,dsi-phy-14nm-660"; |
| reg = <0x0c996400 0x100>, |
| <0x0c996500 0x300>, |
| <0x0c996800 0x188>; |
| reg-names = "dsi_phy", |
| "dsi_phy_lane", |
| "dsi_pll"; |
| |
| #clock-cells = <1>; |
| #phy-cells = <0>; |
| |
| clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; |
| clock-names = "iface", "ref"; |
| status = "disabled"; |
| }; |
| }; |
| |
| &mmcc { |
| compatible = "qcom,mmcc-sdm660"; |
| clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, |
| <&sleep_clk>, |
| <&gcc GCC_MMSS_GPLL0_CLK>, |
| <&gcc GCC_MMSS_GPLL0_DIV_CLK>, |
| <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, |
| <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, |
| <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, |
| <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, |
| <0>, |
| <0>; |
| }; |
| |
| &soc { |
| cdsp_smmu: iommu@5180000 { |
| compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; |
| reg = <0x5180000 0x40000>; |
| #iommu-cells = <1>; |
| |
| #global-interrupts = <2>; |
| interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 537 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 538 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 540 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_HLOS1_VOTE_TURING_ADSP_SMMU_CLK>; |
| clock-names = "bus"; |
| |
| power-domains = <&gcc HLOS1_VOTE_TURING_ADSP_GDSC>; |
| |
| }; |
| |
| remoteproc_cdsp: remoteproc@1a300000 { |
| compatible = "qcom,sdm660-cdsp-pas"; |
| reg = <0x1a300000 0x00100>; |
| interrupts-extended = <&intc GIC_SPI 518 IRQ_TYPE_EDGE_RISING>, |
| <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, |
| <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, |
| <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, |
| <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "wdog", |
| "fatal", |
| "ready", |
| "handover", |
| "stop-ack"; |
| |
| clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; |
| clock-names = "xo"; |
| |
| memory-region = <&cdsp_region>; |
| power-domains = <&rpmpd SDM660_VDDCX>; |
| power-domain-names = "cx"; |
| |
| qcom,smem-states = <&cdsp_smp2p_out 0>; |
| qcom,smem-state-names = "stop"; |
| |
| glink-edge { |
| interrupts = <GIC_SPI 513 IRQ_TYPE_EDGE_RISING>; |
| |
| label = "cdsp"; |
| mboxes = <&apcs_glb 29>; |
| qcom,remote-pid = <5>; |
| |
| fastrpc { |
| compatible = "qcom,fastrpc"; |
| qcom,glink-channels = "fastrpcglink-apps-dsp"; |
| label = "cdsp"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| compute-cb@5 { |
| compatible = "qcom,fastrpc-compute-cb"; |
| reg = <5>; |
| iommus = <&cdsp_smmu 3>; |
| }; |
| |
| compute-cb@6 { |
| compatible = "qcom,fastrpc-compute-cb"; |
| reg = <6>; |
| iommus = <&cdsp_smmu 4>; |
| }; |
| |
| compute-cb@7 { |
| compatible = "qcom,fastrpc-compute-cb"; |
| reg = <7>; |
| iommus = <&cdsp_smmu 5>; |
| }; |
| |
| compute-cb@8 { |
| compatible = "qcom,fastrpc-compute-cb"; |
| reg = <8>; |
| iommus = <&cdsp_smmu 6>; |
| }; |
| |
| compute-cb@9 { |
| compatible = "qcom,fastrpc-compute-cb"; |
| reg = <9>; |
| iommus = <&cdsp_smmu 7>; |
| }; |
| |
| compute-cb@10 { |
| compatible = "qcom,fastrpc-compute-cb"; |
| reg = <10>; |
| iommus = <&cdsp_smmu 8>; |
| }; |
| |
| compute-cb@11 { |
| compatible = "qcom,fastrpc-compute-cb"; |
| reg = <11>; |
| iommus = <&cdsp_smmu 9>; |
| }; |
| |
| compute-cb@12 { |
| compatible = "qcom,fastrpc-compute-cb"; |
| reg = <12>; |
| iommus = <&cdsp_smmu 10>; |
| }; |
| |
| compute-cb@13 { |
| compatible = "qcom,fastrpc-compute-cb"; |
| reg = <13>; |
| iommus = <&cdsp_smmu 11>; |
| }; |
| }; |
| }; |
| }; |
| }; |
| |
| &tlmm { |
| compatible = "qcom,sdm660-pinctrl"; |
| }; |
| |
| &tsens { |
| #qcom,sensors = <14>; |
| }; |
