arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts

// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
 * IPQ5424 RDP466 board device tree source
 *
 * Copyright (c) 2024-2025 The Linux Foundation. All rights reserved.
 */

/dts-v1/;

#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include "ipq5424.dtsi"

/ {
	model = "Qualcomm Technologies, Inc. IPQ5424 RDP466";
	compatible = "qcom,ipq5424-rdp466", "qcom,ipq5424";

	aliases {
		serial0 = &uart1;
	};

	gpio-keys {
		compatible = "gpio-keys";
		pinctrl-0 = <&gpio_keys_default>;
		pinctrl-names = "default";

		button-wps {
			label = "wps";
			linux,code = <KEY_WPS_BUTTON>;
			gpios = <&tlmm 19 GPIO_ACTIVE_LOW>;
			debounce-interval = <60>;
		};
	};

	leds {
		compatible = "gpio-leds";
		pinctrl-0 = <&gpio_leds_default>;
		pinctrl-names = "default";

		led-0 {
			color = <LED_COLOR_ID_GREEN>;
			function = LED_FUNCTION_WLAN;
			gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "phy0tx";
			default-state = "off";
		};
	};

	vreg_misc_3p3: regulator-usb-3p3 {
		compatible = "regulator-fixed";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		regulator-always-on;
		regulator-name = "usb_hs_vdda_3p3";
	};

	vreg_misc_1p8: regulator-usb-1p8 {
		compatible = "regulator-fixed";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-boot-on;
		regulator-always-on;
		regulator-name = "vdda_1p8_usb";
	};

	vreg_misc_0p925: regulator-usb-0p925 {
		compatible = "regulator-fixed";
		regulator-min-microvolt = <925000>;
		regulator-max-microvolt = <925000>;
		regulator-boot-on;
		regulator-always-on;
		regulator-name = "vdd_core_usb";
	};
};

&dwc_0 {
	dr_mode = "host";
};

&dwc_1 {
	dr_mode = "host";
};

&pcie2 {
	pinctrl-0 = <&pcie2_default_state>;
	pinctrl-names = "default";

	perst-gpios = <&tlmm 31 GPIO_ACTIVE_LOW>;

	status = "okay";
};

&pcie2_phy {
	status = "okay";
};

&pcie3 {
	pinctrl-0 = <&pcie3_default_state>;
	pinctrl-names = "default";

	perst-gpios = <&tlmm 34 GPIO_ACTIVE_LOW>;

	status = "okay";
};

&pcie3_phy {
	status = "okay";
};

&qusb_phy_0 {
	vdd-supply = <&vreg_misc_0p925>;
	vdda-pll-supply = <&vreg_misc_1p8>;
	vdda-phy-dpdm-supply = <&vreg_misc_3p3>;

	status = "okay";
};

&qusb_phy_1 {
	vdd-supply = <&vreg_misc_0p925>;
	vdda-pll-supply = <&vreg_misc_1p8>;
	vdda-phy-dpdm-supply = <&vreg_misc_3p3>;

	status = "okay";
};

&sdhc {
	pinctrl-0 = <&sdc_default_state>;
	pinctrl-names = "default";

	status = "okay";
};

&sleep_clk {
	clock-frequency = <32000>;
};

&spi0 {
	pinctrl-0 = <&spi0_default_state>;
	pinctrl-names = "default";
	status = "okay";

	flash@0 {
		compatible = "micron,n25q128a11", "jedec,spi-nor";
		reg = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
		spi-max-frequency = <50000000>;
	};
};

&ssphy_0 {
	vdda-pll-supply = <&vreg_misc_1p8>;
	vdda-phy-supply = <&vreg_misc_0p925>;

	status = "okay";
};

&tlmm {
	gpio_keys_default: gpio-keys-default-state {
		pins = "gpio19";
		function = "gpio";
		drive-strength = <8>;
		bias-pull-up;
	};

	gpio_leds_default: gpio-leds-default-state {
		pins = "gpio42";
		function = "gpio";
		drive-strength = <8>;
		bias-pull-down;
	};

	spi0_default_state: spi0-default-state {
		clk-pins {
			pins = "gpio6";
			function = "spi0_clk";
			drive-strength = <8>;
			bias-pull-down;
		};

		cs-pins {
			pins = "gpio7";
			function = "spi0_cs";
			drive-strength = <8>;
			bias-pull-up;
		};

		miso-pins {
			pins = "gpio8";
			function = "spi0_miso";
			drive-strength = <8>;
			bias-pull-down;
		};

		mosi-pins {
			pins = "gpio9";
			function = "spi0_mosi";
			drive-strength = <8>;
			bias-pull-down;
		};
	};

	sdc_default_state: sdc-default-state {
		clk-pins {
			pins = "gpio5";
			function = "sdc_clk";
			drive-strength = <8>;
			bias-disable;
		};

		cmd-pins {
			pins = "gpio4";
			function = "sdc_cmd";
			drive-strength = <8>;
			bias-pull-up;
		};

		data-pins {
			pins = "gpio0", "gpio1", "gpio2", "gpio3";
			function = "sdc_data";
			drive-strength = <8>;
			bias-pull-up;
		};
	};

	uart0_pins: uart0-default-state {
		pins = "gpio10", "gpio11", "gpio12", "gpio13";
		function = "uart0";
		drive-strength = <8>;
		bias-pull-down;
	};

	pcie2_default_state: pcie2-default-state {
		pins = "gpio31";
		function = "gpio";
		drive-strength = <8>;
		bias-pull-up;
	};

	pcie3_default_state: pcie3-default-state {
		pins = "gpio34";
		function = "gpio";
		drive-strength = <8>;
		bias-pull-up;
	};
};

&uart0 {
	pinctrl-0 = <&uart0_pins>;
	pinctrl-names = "default";
	/*
	 * The required initialization for this SE is not handled by the
	 * bootloader. Therefore, keep the device in "reserved" state until
	 * linux gains support for configuring the SE.
	 */
	status = "reserved";
};

&uart1 {
	pinctrl-0 = <&uart1_pins>;
	pinctrl-names = "default";
	status = "okay";
};

&usb2 {
	status = "okay";
};

&usb3 {
	status = "okay";
};

/*
 * The bootstrap pins for the board select the XO clock frequency that
 * supports 48 MHZ, 96 MHZ or 192 MHZ. This setting automatically
 * enables the right dividers, to ensure the reference clock output
 * from WiFi to the CMN PLL is 48 MHZ.
 */
&ref_48mhz_clk {
	clock-div = <1>;
	clock-mult = <1>;
};

/*
 * The frequency of xo_board is fixed to 24 MHZ, which is routed
 * from WiFi output clock 48 MHZ divided by 2.
 */
&xo_board {
	clock-div = <2>;
	clock-mult = <1>;
};

&xo_clk {
	clock-frequency = <48000000>;
};