arch/arm64/boot/dts/mediatek/mt7981b.dtsi - third_party/linux - Git at Google

 // SPDX-License-Identifier: GPL-2.0-only OR MIT

 #include <dt-bindings/clock/mediatek,mt7981-clk.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/leds/common.h>
 #include <dt-bindings/phy/phy.h>
 #include <dt-bindings/reset/mt7986-resets.h>

 / {
 	compatible = "mediatek,mt7981b";
 	interrupt-parent = <&gic>;
 	#address-cells = <2>;
 	#size-cells = <2>;

 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;

 		cpu@0 {
 			compatible = "arm,cortex-a53";
 			reg = <0x0>;
 			device_type = "cpu";
 			enable-method = "psci";
 		};

 		cpu@1 {
 			compatible = "arm,cortex-a53";
 			reg = <0x1>;
 			device_type = "cpu";
 			enable-method = "psci";
 		};
 	};

 	oscillator-40m {
 		compatible = "fixed-clock";
 		clock-frequency = <40000000>;
 		clock-output-names = "clkxtal";
 		#clock-cells = <0>;
 	};

 	psci {
 		compatible = "arm,psci-1.0";
 		method = "smc";
 	};

 	reserved-memory {
 		#address-cells = <2>;
 		#size-cells = <2>;
 		ranges;

 		wo_boot: wo-boot@15194000 {
 			reg = <0 0x15194000 0 0x1000>;
 			no-map;
 		};

 		wo_ilm0: wo-ilm@151e0000 {
 			reg = <0 0x151e0000 0 0x8000>;
 			no-map;
 		};

 		wo_dlm0: wo-dlm@151e8000 {
 			reg = <0 0x151e8000 0 0x2000>;
 			no-map;
 		};

 		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
 		secmon_reserved: secmon@43000000 {
 			reg = <0 0x43000000 0 0x30000>;
 			no-map;
 		};

 		wmcpu_emi: wmcpu-reserved@47c80000 {
 			reg = <0 0x47c80000 0 0x100000>;
 			no-map;
 		};

 		wo_emi0: wo-emi@47d80000 {
 			reg = <0 0x47d80000 0 0x40000>;
 			no-map;
 		};

 		wo_data: wo-data@47dc0000 {
 			reg = <0 0x47dc0000 0 0x240000>;
 			no-map;
 		};
 	};

 	soc {
 		compatible = "simple-bus";
 		ranges;
 		#address-cells = <2>;
 		#size-cells = <2>;

 		gic: interrupt-controller@c000000 {
 			compatible = "arm,gic-v3";
 			reg = <0 0x0c000000 0 0x40000>,  /* GICD */
 			      <0 0x0c080000 0 0x200000>; /* GICR */
 			interrupt-parent = <&gic>;
 			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-controller;
 			#interrupt-cells = <3>;
 		};

 		infracfg: clock-controller@10001000 {
 			compatible = "mediatek,mt7981-infracfg", "syscon";
 			reg = <0 0x10001000 0 0x1000>;
 			#clock-cells = <1>;
 		};

 		topckgen: clock-controller@1001b000 {
 			compatible = "mediatek,mt7981-topckgen", "syscon";
 			reg = <0 0x1001b000 0 0x1000>;
 			#clock-cells = <1>;
 		};

 		watchdog: watchdog@1001c000 {
 			compatible = "mediatek,mt7986-wdt";
 			reg = <0 0x1001c000 0 0x1000>;
 			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 			#reset-cells = <1>;
 		};

 		apmixedsys: clock-controller@1001e000 {
 			compatible = "mediatek,mt7981-apmixedsys";
 			reg = <0 0x1001e000 0 0x1000>;
 			#clock-cells = <1>;
 		};

 		pwm: pwm@10048000 {
 			compatible = "mediatek,mt7981-pwm";
 			reg = <0 0x10048000 0 0x1000>;
 			clocks = <&infracfg CLK_INFRA_PWM_STA>,
 				 <&infracfg CLK_INFRA_PWM_HCK>,
 				 <&infracfg CLK_INFRA_PWM1_CK>,
 				 <&infracfg CLK_INFRA_PWM2_CK>,
 				 <&infracfg CLK_INFRA_PWM3_CK>;
 			clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
 			#pwm-cells = <2>;
 		};

 		sgmiisys0: syscon@10060000 {
 			compatible = "mediatek,mt7981-sgmiisys_0", "syscon";
 			reg = <0 0x10060000 0 0x1000>;
 			#clock-cells = <1>;
 		};

 		sgmiisys1: syscon@10070000 {
 			compatible = "mediatek,mt7981-sgmiisys_1", "syscon";
 			reg = <0 0x10070000 0 0x1000>;
 			#clock-cells = <1>;
 		};

 		uart0: serial@11002000 {
 			compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart";
 			reg = <0 0x11002000 0 0x100>;
 			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "uart", "wakeup";
 			clocks = <&infracfg CLK_INFRA_UART0_SEL>,
 				 <&infracfg CLK_INFRA_UART0_CK>;
 			clock-names = "baud", "bus";
 			pinctrl-names = "default";
 			pinctrl-0 = <&uart0_pins>;
 			status = "disabled";
 		};

 		uart1: serial@11003000 {
 			compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart";
 			reg = <0 0x11003000 0 0x100>;
 			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "uart", "wakeup";
 			clocks = <&infracfg CLK_INFRA_UART1_SEL>,
 				 <&infracfg CLK_INFRA_UART1_CK>;
 			clock-names = "baud", "bus";
 			status = "disabled";
 		};

 		uart2: serial@11004000 {
 			compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart";
 			reg = <0 0x11004000 0 0x100>;
 			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "uart", "wakeup";
 			clocks = <&infracfg CLK_INFRA_UART2_SEL>,
 				 <&infracfg CLK_INFRA_UART2_CK>;
 			clock-names = "baud", "bus";
 			status = "disabled";
 		};

 		i2c@11007000 {
 			compatible = "mediatek,mt7981-i2c";
 			reg = <0 0x11007000 0 0x1000>,
 			      <0 0x10217080 0 0x80>;
 			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&infracfg CLK_INFRA_I2C0_CK>,
 				 <&infracfg CLK_INFRA_AP_DMA_CK>,
 				 <&infracfg CLK_INFRA_I2C_MCK_CK>,
 				 <&infracfg CLK_INFRA_I2C_PCK_CK>;
 			clock-names = "main", "dma", "arb", "pmic";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
 		};

 		spi2: spi@11009000 {
 			compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm";
 			reg = <0 0x11009000 0 0x1000>;
 			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&topckgen CLK_TOP_CB_M_D2>,
 				 <&topckgen CLK_TOP_SPI_SEL>,
 				 <&infracfg CLK_INFRA_SPI2_CK>,
 				 <&infracfg CLK_INFRA_SPI2_HCK_CK>;
 			clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
 		};

 		spi@1100a000 {
 			compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm";
 			reg = <0 0x1100a000 0 0x1000>;
 			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&topckgen CLK_TOP_CB_M_D2>,
 				 <&topckgen CLK_TOP_SPI_SEL>,
 				 <&infracfg CLK_INFRA_SPI0_CK>,
 				 <&infracfg CLK_INFRA_SPI0_HCK_CK>;
 			clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
 		};

 		spi@1100b000 {
 			compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm";
 			reg = <0 0x1100b000 0 0x1000>;
 			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&topckgen CLK_TOP_CB_M_D2>,
 				 <&topckgen CLK_TOP_SPI_SEL>,
 				 <&infracfg CLK_INFRA_SPI1_CK>,
 				 <&infracfg CLK_INFRA_SPI1_HCK_CK>;
 			clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
 		};

 		thermal@1100c800 {
 			compatible = "mediatek,mt7981-thermal",
 				     "mediatek,mt7986-thermal";
 			reg = <0 0x1100c800 0 0x800>;
 			interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&infracfg CLK_INFRA_THERM_CK>,
 				 <&infracfg CLK_INFRA_ADC_26M_CK>;
 			clock-names = "therm", "auxadc";
 			nvmem-cells = <&thermal_calibration>;
 			nvmem-cell-names = "calibration-data";
 			#thermal-sensor-cells = <1>;
 			mediatek,auxadc = <&auxadc>;
 			mediatek,apmixedsys = <&apmixedsys>;
 		};

 		auxadc: adc@1100d000 {
 			compatible = "mediatek,mt7981-auxadc",
 				     "mediatek,mt7986-auxadc";
 			reg = <0 0x1100d000 0 0x1000>;
 			clocks = <&infracfg CLK_INFRA_ADC_26M_CK>;
 			clock-names = "main";
 			#io-channel-cells = <1>;
 			status = "disabled";
 		};

 		xhci: usb@11200000 {
 			compatible = "mediatek,mt7986-xhci", "mediatek,mtk-xhci";
 			reg = <0 0x11200000 0 0x2e00>, <0 0x11203e00 0 0x0100>;
 			reg-names = "mac", "ippc";
 			clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
 				 <&infracfg CLK_INFRA_IUSB_CK>,
 				 <&infracfg CLK_INFRA_IUSB_133_CK>,
 				 <&infracfg CLK_INFRA_IUSB_66M_CK>,
 				 <&topckgen CLK_TOP_U2U3_XHCI_SEL>;
 			clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
 			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
 			phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
 			status = "disabled";
 		};

 		pcie: pcie@11280000 {
 			compatible = "mediatek,mt7981-pcie",
 				     "mediatek,mt8192-pcie";
 			reg = <0 0x11280000 0 0x4000>;
 			reg-names = "pcie-mac";
 			ranges = <0x82000000 0 0x20000000
 				  0x0 0x20000000 0 0x10000000>;
 			bus-range = <0x00 0xff>;
 			clocks = <&infracfg CLK_INFRA_IPCIE_CK>,
 				 <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
 				 <&infracfg CLK_INFRA_IPCIER_CK>,
 				 <&infracfg CLK_INFRA_IPCIEB_CK>;
 			clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m";
 			device_type = "pci";
 			phys = <&u3port0 PHY_TYPE_PCIE>;
 			phy-names = "pcie-phy";
 			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-map-mask = <0 0 0 7>;
 			interrupt-map = <0 0 0 1 &pcie_intc 0>,
 					<0 0 0 2 &pcie_intc 1>,
 					<0 0 0 3 &pcie_intc 2>,
 					<0 0 0 4 &pcie_intc 3>;
 			#address-cells = <3>;
 			#interrupt-cells = <1>;
 			#size-cells = <2>;
 			status = "disabled";

 			pcie_intc: interrupt-controller {
 				interrupt-controller;
 				#address-cells = <0>;
 				#interrupt-cells = <1>;
 			};
 		};

 		pio: pinctrl@11d00000 {
 			compatible = "mediatek,mt7981-pinctrl";
 			reg = <0 0x11d00000 0 0x1000>,
 			      <0 0x11c00000 0 0x1000>,
 			      <0 0x11c10000 0 0x1000>,
 			      <0 0x11d20000 0 0x1000>,
 			      <0 0x11e00000 0 0x1000>,
 			      <0 0x11e20000 0 0x1000>,
 			      <0 0x11f00000 0 0x1000>,
 			      <0 0x11f10000 0 0x1000>,
 			      <0 0x1000b000 0 0x1000>;
 			reg-names = "gpio", "iocfg_rt", "iocfg_rm", "iocfg_rb", "iocfg_lb",
 				    "iocfg_bl", "iocfg_tm", "iocfg_tl", "eint";
 			interrupt-controller;
 			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-parent = <&gic>;
 			gpio-ranges = <&pio 0 0 56>;
 			gpio-controller;
 			#gpio-cells = <2>;
 			#interrupt-cells = <2>;

 			uart0_pins: uart0-pins {
 				mux {
 					function = "uart";
 					groups = "uart0";
 				};
 			};
 		};

 		topmisc: topmisc@11d10000 {
 			compatible = "mediatek,mt7981-topmisc", "syscon";
 			reg = <0 0x11d10000 0 0x10000>;
 			#clock-cells = <1>;
 		};

 		usb_phy: t-phy@11e10000 {
 			compatible = "mediatek,mt7981-tphy",
 				     "mediatek,generic-tphy-v2";
 			ranges = <0 0 0x11e10000 0x1700>;
 			#address-cells = <1>;
 			#size-cells = <1>;
 			status = "disabled";

 			u2port0: usb-phy@0 {
 				reg = <0x0 0x700>;
 				clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>;
 				clock-names = "ref";
 				#phy-cells = <1>;
 			};

 			u3port0: usb-phy@700 {
 				reg = <0x700 0x900>;
 				clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
 				clock-names = "ref";
 				#phy-cells = <1>;
 				mediatek,syscon-type = <&topmisc 0x218 0>;
 			};
 		};

 		efuse@11f20000 {
 			compatible = "mediatek,mt7981-efuse", "mediatek,efuse";
 			reg = <0 0x11f20000 0 0x1000>;
 			#address-cells = <1>;
 			#size-cells = <1>;

 			soc-uuid@140 {
 				reg = <0x140 0x10>;
 			};

 			thermal_calibration: thermal-calib@274 {
 				reg = <0x274 0xc>;
 			};

 			phy_calibration: phy-calib@8dc {
 				reg = <0x8dc 0x10>;
 			};
 		};

 		ethsys: clock-controller@15000000 {
 			compatible = "mediatek,mt7981-ethsys", "syscon";
 			reg = <0 0x15000000 0 0x1000>;
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 		};

 		wed: wed@15010000 {
 			compatible = "mediatek,mt7981-wed",
 				     "syscon";
 			reg = <0 0x15010000 0 0x1000>;
 			interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
 			memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>,
 					<&wo_data>, <&wo_boot>;
 			memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
 					      "wo-data", "wo-boot";
 			mediatek,wo-ccif = <&wo_ccif0>;
 		};

 		eth: ethernet@15100000 {
 			compatible = "mediatek,mt7981-eth";
 			reg = <0 0x15100000 0 0x40000>;
 			assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
 					  <&topckgen CLK_TOP_SGM_325M_SEL>;
 			assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_800M>,
 						 <&topckgen CLK_TOP_CB_SGM_325M>;
 			clocks = <&ethsys CLK_ETH_FE_EN>,
 				 <&ethsys CLK_ETH_GP2_EN>,
 				 <&ethsys CLK_ETH_GP1_EN>,
 				 <&ethsys CLK_ETH_WOCPU0_EN>,
 				 <&topckgen CLK_TOP_SGM_REG>,
 				 <&sgmiisys0 CLK_SGM0_TX_EN>,
 				 <&sgmiisys0 CLK_SGM0_RX_EN>,
 				 <&sgmiisys0 CLK_SGM0_CK0_EN>,
 				 <&sgmiisys0 CLK_SGM0_CDR_CK0_EN>,
 				 <&sgmiisys1 CLK_SGM1_TX_EN>,
 				 <&sgmiisys1 CLK_SGM1_RX_EN>,
 				 <&sgmiisys1 CLK_SGM1_CK1_EN>,
 				 <&sgmiisys1 CLK_SGM1_CDR_CK1_EN>,
 				 <&topckgen CLK_TOP_NETSYS_SEL>,
 				 <&topckgen CLK_TOP_NETSYS_500M_SEL>;
 			clock-names = "fe", "gp2", "gp1", "wocpu0",
 				      "sgmii_ck",
 				      "sgmii_tx250m", "sgmii_rx250m",
 				      "sgmii_cdr_ref", "sgmii_cdr_fb",
 				      "sgmii2_tx250m", "sgmii2_rx250m",
 				      "sgmii2_cdr_ref", "sgmii2_cdr_fb",
 				      "netsys0", "netsys1";
 			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "fe0", "fe1", "fe2", "fe3", "pdma0",
 					  "pdma1", "pdma2", "pdma3";
 			sram = <&eth_sram>;
 			mediatek,ethsys = <&ethsys>;
 			mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
 			mediatek,infracfg = <&topmisc>;
 			mediatek,wed = <&wed>;
 			status = "disabled";

 			mdio_bus: mdio-bus {
 				#address-cells = <1>;
 				#size-cells = <0>;

 				int_gbe_phy: ethernet-phy@0 {
 					compatible = "ethernet-phy-ieee802.3-c22";
 					reg = <0>;
 					phy-mode = "gmii";
 					phy-is-integrated;
 					nvmem-cells = <&phy_calibration>;
 					nvmem-cell-names = "phy-cal-data";
 				};
 			};
 		};

 		eth_sram: sram@15140000 {
 			compatible = "mmio-sram";
 			reg = <0 0x15140000 0 0x40000>;
 			ranges = <0 0x15140000 0 0x40000>;
 			#address-cells = <1>;
 			#size-cells = <1>;
 		};

 		wo_ccif0: syscon@151a5000 {
 			compatible = "mediatek,mt7986-wo-ccif", "syscon";
 			reg = <0 0x151a5000 0 0x1000>;
 			interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
 		};

 		wifi: wifi@18000000 {
 			compatible = "mediatek,mt7981-wmac";
 			reg = <0 0x18000000 0 0x1000000>,
 			      <0 0x10003000 0 0x1000>,
 			      <0 0x11d10000 0 0x1000>;
 			interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>,
 				 <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
 			clock-names = "mcu", "ap2conn";
 			memory-region = <&wmcpu_emi>;
 			resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
 			reset-names = "consys";
 			status = "disabled";
 		};
 	};

 	timer {
 		compatible = "arm,armv8-timer";
 		interrupt-parent = <&gic>;
 		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 	};
 };
	// SPDX-License-Identifier: GPL-2.0-only OR MIT

	#include <dt-bindings/clock/mediatek,mt7981-clk.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/leds/common.h>
	#include <dt-bindings/phy/phy.h>
	#include <dt-bindings/reset/mt7986-resets.h>

	/ {
	compatible = "mediatek,mt7981b";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu@0 {
	compatible = "arm,cortex-a53";
	reg = <0x0>;
	device_type = "cpu";
	enable-method = "psci";
	};

	cpu@1 {
	compatible = "arm,cortex-a53";
	reg = <0x1>;
	device_type = "cpu";
	enable-method = "psci";
	};
	};

	oscillator-40m {
	compatible = "fixed-clock";
	clock-frequency = <40000000>;
	clock-output-names = "clkxtal";
	#clock-cells = <0>;
	};

	psci {
	compatible = "arm,psci-1.0";
	method = "smc";
	};

	reserved-memory {
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	wo_boot: wo-boot@15194000 {
	reg = <0 0x15194000 0 0x1000>;
	no-map;
	};

	wo_ilm0: wo-ilm@151e0000 {
	reg = <0 0x151e0000 0 0x8000>;
	no-map;
	};

	wo_dlm0: wo-dlm@151e8000 {
	reg = <0 0x151e8000 0 0x2000>;
	no-map;
	};

	/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
	secmon_reserved: secmon@43000000 {
	reg = <0 0x43000000 0 0x30000>;
	no-map;
	};

	wmcpu_emi: wmcpu-reserved@47c80000 {
	reg = <0 0x47c80000 0 0x100000>;
	no-map;
	};

	wo_emi0: wo-emi@47d80000 {
	reg = <0 0x47d80000 0 0x40000>;
	no-map;
	};

	wo_data: wo-data@47dc0000 {
	reg = <0 0x47dc0000 0 0x240000>;
	no-map;
	};
	};

	soc {
	compatible = "simple-bus";
	ranges;
	#address-cells = <2>;
	#size-cells = <2>;

	gic: interrupt-controller@c000000 {
	compatible = "arm,gic-v3";
	reg = <0 0x0c000000 0 0x40000>, /* GICD */
	<0 0x0c080000 0 0x200000>; /* GICR */
	interrupt-parent = <&gic>;
	interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-controller;
	#interrupt-cells = <3>;
	};

	infracfg: clock-controller@10001000 {
	compatible = "mediatek,mt7981-infracfg", "syscon";
	reg = <0 0x10001000 0 0x1000>;
	#clock-cells = <1>;
	};

	topckgen: clock-controller@1001b000 {
	compatible = "mediatek,mt7981-topckgen", "syscon";
	reg = <0 0x1001b000 0 0x1000>;
	#clock-cells = <1>;
	};

	watchdog: watchdog@1001c000 {
	compatible = "mediatek,mt7986-wdt";
	reg = <0 0x1001c000 0 0x1000>;
	interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
	#reset-cells = <1>;
	};

	apmixedsys: clock-controller@1001e000 {
	compatible = "mediatek,mt7981-apmixedsys";
	reg = <0 0x1001e000 0 0x1000>;
	#clock-cells = <1>;
	};

	pwm: pwm@10048000 {
	compatible = "mediatek,mt7981-pwm";
	reg = <0 0x10048000 0 0x1000>;
	clocks = <&infracfg CLK_INFRA_PWM_STA>,
	<&infracfg CLK_INFRA_PWM_HCK>,
	<&infracfg CLK_INFRA_PWM1_CK>,
	<&infracfg CLK_INFRA_PWM2_CK>,
	<&infracfg CLK_INFRA_PWM3_CK>;
	clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
	#pwm-cells = <2>;
	};

	sgmiisys0: syscon@10060000 {
	compatible = "mediatek,mt7981-sgmiisys_0", "syscon";
	reg = <0 0x10060000 0 0x1000>;
	#clock-cells = <1>;
	};

	sgmiisys1: syscon@10070000 {
	compatible = "mediatek,mt7981-sgmiisys_1", "syscon";
	reg = <0 0x10070000 0 0x1000>;
	#clock-cells = <1>;
	};

	uart0: serial@11002000 {
	compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart";
	reg = <0 0x11002000 0 0x100>;
	interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "uart", "wakeup";
	clocks = <&infracfg CLK_INFRA_UART0_SEL>,
	<&infracfg CLK_INFRA_UART0_CK>;
	clock-names = "baud", "bus";
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_pins>;
	status = "disabled";
	};

	uart1: serial@11003000 {
	compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart";
	reg = <0 0x11003000 0 0x100>;
	interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "uart", "wakeup";
	clocks = <&infracfg CLK_INFRA_UART1_SEL>,
	<&infracfg CLK_INFRA_UART1_CK>;
	clock-names = "baud", "bus";
	status = "disabled";
	};

	uart2: serial@11004000 {
	compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart";
	reg = <0 0x11004000 0 0x100>;
	interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "uart", "wakeup";
	clocks = <&infracfg CLK_INFRA_UART2_SEL>,
	<&infracfg CLK_INFRA_UART2_CK>;
	clock-names = "baud", "bus";
	status = "disabled";
	};

	i2c@11007000 {
	compatible = "mediatek,mt7981-i2c";
	reg = <0 0x11007000 0 0x1000>,
	<0 0x10217080 0 0x80>;
	interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&infracfg CLK_INFRA_I2C0_CK>,
	<&infracfg CLK_INFRA_AP_DMA_CK>,
	<&infracfg CLK_INFRA_I2C_MCK_CK>,
	<&infracfg CLK_INFRA_I2C_PCK_CK>;
	clock-names = "main", "dma", "arb", "pmic";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi2: spi@11009000 {
	compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm";
	reg = <0 0x11009000 0 0x1000>;
	interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&topckgen CLK_TOP_CB_M_D2>,
	<&topckgen CLK_TOP_SPI_SEL>,
	<&infracfg CLK_INFRA_SPI2_CK>,
	<&infracfg CLK_INFRA_SPI2_HCK_CK>;
	clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi@1100a000 {
	compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm";
	reg = <0 0x1100a000 0 0x1000>;
	interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&topckgen CLK_TOP_CB_M_D2>,
	<&topckgen CLK_TOP_SPI_SEL>,
	<&infracfg CLK_INFRA_SPI0_CK>,
	<&infracfg CLK_INFRA_SPI0_HCK_CK>;
	clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi@1100b000 {
	compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm";
	reg = <0 0x1100b000 0 0x1000>;
	interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&topckgen CLK_TOP_CB_M_D2>,
	<&topckgen CLK_TOP_SPI_SEL>,
	<&infracfg CLK_INFRA_SPI1_CK>,
	<&infracfg CLK_INFRA_SPI1_HCK_CK>;
	clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	thermal@1100c800 {
	compatible = "mediatek,mt7981-thermal",
	"mediatek,mt7986-thermal";
	reg = <0 0x1100c800 0 0x800>;
	interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&infracfg CLK_INFRA_THERM_CK>,
	<&infracfg CLK_INFRA_ADC_26M_CK>;
	clock-names = "therm", "auxadc";
	nvmem-cells = <&thermal_calibration>;
	nvmem-cell-names = "calibration-data";
	#thermal-sensor-cells = <1>;
	mediatek,auxadc = <&auxadc>;
	mediatek,apmixedsys = <&apmixedsys>;
	};

	auxadc: adc@1100d000 {
	compatible = "mediatek,mt7981-auxadc",
	"mediatek,mt7986-auxadc";
	reg = <0 0x1100d000 0 0x1000>;
	clocks = <&infracfg CLK_INFRA_ADC_26M_CK>;
	clock-names = "main";
	#io-channel-cells = <1>;
	status = "disabled";
	};

	xhci: usb@11200000 {
	compatible = "mediatek,mt7986-xhci", "mediatek,mtk-xhci";
	reg = <0 0x11200000 0 0x2e00>, <0 0x11203e00 0 0x0100>;
	reg-names = "mac", "ippc";
	clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
	<&infracfg CLK_INFRA_IUSB_CK>,
	<&infracfg CLK_INFRA_IUSB_133_CK>,
	<&infracfg CLK_INFRA_IUSB_66M_CK>,
	<&topckgen CLK_TOP_U2U3_XHCI_SEL>;
	clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
	interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
	phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
	status = "disabled";
	};

	pcie: pcie@11280000 {
	compatible = "mediatek,mt7981-pcie",
	"mediatek,mt8192-pcie";
	reg = <0 0x11280000 0 0x4000>;
	reg-names = "pcie-mac";
	ranges = <0x82000000 0 0x20000000
	0x0 0x20000000 0 0x10000000>;
	bus-range = <0x00 0xff>;
	clocks = <&infracfg CLK_INFRA_IPCIE_CK>,
	<&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
	<&infracfg CLK_INFRA_IPCIER_CK>,
	<&infracfg CLK_INFRA_IPCIEB_CK>;
	clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m";
	device_type = "pci";
	phys = <&u3port0 PHY_TYPE_PCIE>;
	phy-names = "pcie-phy";
	interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-map-mask = <0 0 0 7>;
	interrupt-map = <0 0 0 1 &pcie_intc 0>,
	<0 0 0 2 &pcie_intc 1>,
	<0 0 0 3 &pcie_intc 2>,
	<0 0 0 4 &pcie_intc 3>;
	#address-cells = <3>;
	#interrupt-cells = <1>;
	#size-cells = <2>;
	status = "disabled";

	pcie_intc: interrupt-controller {
	interrupt-controller;
	#address-cells = <0>;
	#interrupt-cells = <1>;
	};
	};

	pio: pinctrl@11d00000 {
	compatible = "mediatek,mt7981-pinctrl";
	reg = <0 0x11d00000 0 0x1000>,
	<0 0x11c00000 0 0x1000>,
	<0 0x11c10000 0 0x1000>,
	<0 0x11d20000 0 0x1000>,
	<0 0x11e00000 0 0x1000>,
	<0 0x11e20000 0 0x1000>,
	<0 0x11f00000 0 0x1000>,
	<0 0x11f10000 0 0x1000>,
	<0 0x1000b000 0 0x1000>;
	reg-names = "gpio", "iocfg_rt", "iocfg_rm", "iocfg_rb", "iocfg_lb",
	"iocfg_bl", "iocfg_tm", "iocfg_tl", "eint";
	interrupt-controller;
	interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-parent = <&gic>;
	gpio-ranges = <&pio 0 0 56>;
	gpio-controller;
	#gpio-cells = <2>;
	#interrupt-cells = <2>;

	uart0_pins: uart0-pins {
	mux {
	function = "uart";
	groups = "uart0";
	};
	};
	};

	topmisc: topmisc@11d10000 {
	compatible = "mediatek,mt7981-topmisc", "syscon";
	reg = <0 0x11d10000 0 0x10000>;
	#clock-cells = <1>;
	};

	usb_phy: t-phy@11e10000 {
	compatible = "mediatek,mt7981-tphy",
	"mediatek,generic-tphy-v2";
	ranges = <0 0 0x11e10000 0x1700>;
	#address-cells = <1>;
	#size-cells = <1>;
	status = "disabled";

	u2port0: usb-phy@0 {
	reg = <0x0 0x700>;
	clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>;
	clock-names = "ref";
	#phy-cells = <1>;
	};

	u3port0: usb-phy@700 {
	reg = <0x700 0x900>;
	clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
	clock-names = "ref";
	#phy-cells = <1>;
	mediatek,syscon-type = <&topmisc 0x218 0>;
	};
	};

	efuse@11f20000 {
	compatible = "mediatek,mt7981-efuse", "mediatek,efuse";
	reg = <0 0x11f20000 0 0x1000>;
	#address-cells = <1>;
	#size-cells = <1>;

	soc-uuid@140 {
	reg = <0x140 0x10>;
	};

	thermal_calibration: thermal-calib@274 {
	reg = <0x274 0xc>;
	};

	phy_calibration: phy-calib@8dc {
	reg = <0x8dc 0x10>;
	};
	};

	ethsys: clock-controller@15000000 {
	compatible = "mediatek,mt7981-ethsys", "syscon";
	reg = <0 0x15000000 0 0x1000>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	wed: wed@15010000 {
	compatible = "mediatek,mt7981-wed",
	"syscon";
	reg = <0 0x15010000 0 0x1000>;
	interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
	memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>,
	<&wo_data>, <&wo_boot>;
	memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
	"wo-data", "wo-boot";
	mediatek,wo-ccif = <&wo_ccif0>;
	};

	eth: ethernet@15100000 {
	compatible = "mediatek,mt7981-eth";
	reg = <0 0x15100000 0 0x40000>;
	assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
	<&topckgen CLK_TOP_SGM_325M_SEL>;
	assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_800M>,
	<&topckgen CLK_TOP_CB_SGM_325M>;
	clocks = <&ethsys CLK_ETH_FE_EN>,
	<&ethsys CLK_ETH_GP2_EN>,
	<&ethsys CLK_ETH_GP1_EN>,
	<&ethsys CLK_ETH_WOCPU0_EN>,
	<&topckgen CLK_TOP_SGM_REG>,
	<&sgmiisys0 CLK_SGM0_TX_EN>,
	<&sgmiisys0 CLK_SGM0_RX_EN>,
	<&sgmiisys0 CLK_SGM0_CK0_EN>,
	<&sgmiisys0 CLK_SGM0_CDR_CK0_EN>,
	<&sgmiisys1 CLK_SGM1_TX_EN>,
	<&sgmiisys1 CLK_SGM1_RX_EN>,
	<&sgmiisys1 CLK_SGM1_CK1_EN>,
	<&sgmiisys1 CLK_SGM1_CDR_CK1_EN>,
	<&topckgen CLK_TOP_NETSYS_SEL>,
	<&topckgen CLK_TOP_NETSYS_500M_SEL>;
	clock-names = "fe", "gp2", "gp1", "wocpu0",
	"sgmii_ck",
	"sgmii_tx250m", "sgmii_rx250m",
	"sgmii_cdr_ref", "sgmii_cdr_fb",
	"sgmii2_tx250m", "sgmii2_rx250m",
	"sgmii2_cdr_ref", "sgmii2_cdr_fb",
	"netsys0", "netsys1";
	interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "fe0", "fe1", "fe2", "fe3", "pdma0",
	"pdma1", "pdma2", "pdma3";
	sram = <&eth_sram>;
	mediatek,ethsys = <&ethsys>;
	mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
	mediatek,infracfg = <&topmisc>;
	mediatek,wed = <&wed>;
	status = "disabled";

	mdio_bus: mdio-bus {
	#address-cells = <1>;
	#size-cells = <0>;

	int_gbe_phy: ethernet-phy@0 {
	compatible = "ethernet-phy-ieee802.3-c22";
	reg = <0>;
	phy-mode = "gmii";
	phy-is-integrated;
	nvmem-cells = <&phy_calibration>;
	nvmem-cell-names = "phy-cal-data";
	};
	};
	};

	eth_sram: sram@15140000 {
	compatible = "mmio-sram";
	reg = <0 0x15140000 0 0x40000>;
	ranges = <0 0x15140000 0 0x40000>;
	#address-cells = <1>;
	#size-cells = <1>;
	};

	wo_ccif0: syscon@151a5000 {
	compatible = "mediatek,mt7986-wo-ccif", "syscon";
	reg = <0 0x151a5000 0 0x1000>;
	interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
	};

	wifi: wifi@18000000 {
	compatible = "mediatek,mt7981-wmac";
	reg = <0 0x18000000 0 0x1000000>,
	<0 0x10003000 0 0x1000>,
	<0 0x11d10000 0 0x1000>;
	interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>,
	<&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
	clock-names = "mcu", "ap2conn";
	memory-region = <&wmcpu_emi>;
	resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
	reset-names = "consys";
	status = "disabled";
	};
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupt-parent = <&gic>;
	interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
	<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
	<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
	<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
	};
	};