arch/arm64/boot/dts/freescale/imx8mp-kontron-bl-osm-s.dts - third_party/linux - Git at Google

 // SPDX-License-Identifier: GPL-2.0+ OR MIT
 /*
  * Copyright (C) 2022 Kontron Electronics GmbH
  */

 /dts-v1/;

 #include "imx8mp-kontron-osm-s.dtsi"

 / {
 	model = "Kontron BL i.MX8MP OSM-S";
 	compatible = "kontron,imx8mp-bl-osm-s", "kontron,imx8mp-osm-s", "fsl,imx8mp";

 	aliases {
 		ethernet0 = &fec;
 		ethernet1 = &eqos;
 	};

 	connector {
 		compatible = "gpio-usb-b-connector", "usb-b-connector";
 		id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
 		label = "Type-C";
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_usb1_id>;
 		type = "micro";
 		vbus-supply = <&reg_usb1_vbus>;

 		port {
 			usb_dr_connector: endpoint {
 				remote-endpoint = <&usb3_dwc>;
 			};
 		};
 	};

 	leds {
 		compatible = "gpio-leds";

 		led1 {
 			label = "led1";
 			gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "heartbeat";
 		};
 	};

 	pwm-beeper {
 		compatible = "pwm-beeper";
 		pwms = <&pwm2 0 5000 0>;
 	};

 	reg_vcc_panel: regulator-vcc-panel {
 		compatible = "regulator-fixed";
 		gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
 		enable-active-high;
 		regulator-max-microvolt = <3300000>;
 		regulator-min-microvolt = <3300000>;
 		regulator-name = "VCC_PANEL";
 	};
 };

 &ecspi2 {
 	status = "okay";

 	eeram@0 {
 		compatible = "microchip,48l640";
 		reg = <0>;
 		spi-max-frequency = <20000000>;
 	};
 };

 &eqos {	/* Second ethernet (OSM-S ETH_B) */
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_eqos_rgmii>;
 	phy-mode = "rgmii-id";
 	phy-handle = <&ethphy1>;
 	status = "okay";

 	mdio {
 		compatible = "snps,dwmac-mdio";
 		#address-cells = <1>;
 		#size-cells = <0>;

 		ethphy1: ethernet-phy@1 {
 			compatible = "ethernet-phy-id4f51.e91b";
 			reg = <1>;
 			pinctrl-0 = <&pinctrl_ethphy1>;
 			pinctrl-names = "default";
 			reset-assert-us = <10000>;
 			reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
 		};
 	};
 };

 &fec { /* First ethernet (OSM-S ETH_A) */
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_enet_rgmii>;
 	phy-connection-type = "rgmii-id";
 	phy-handle = <&ethphy0>;
 	status = "okay";

 	mdio {
 		#address-cells = <1>;
 		#size-cells = <0>;

 		ethphy0: ethernet-phy@1 {
 			compatible = "ethernet-phy-id4f51.e91b";
 			reg = <1>;
 			pinctrl-0 = <&pinctrl_ethphy0>;
 			pinctrl-names = "default";
 			reset-assert-us = <10000>;
 			reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
 		};
 	};
 };

 &flexcan1 {
 	status = "okay";
 };

 /*
  * Rename SoM signals according to board usage:
  *   SDIO_A_PWR_EN -> CAN_ADDR2
  *   SDIO_A_WP     -> CAN_ADDR3
  */
 &gpio2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_gpio2>;
 	gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", "",
 			  "SDIO_A_CD", "SDIO_A_CLK", "SDIO_A_CMD", "SDIO_A_D0",
 			  "SDIO_A_D1", "SDIO_A_D2", "SDIO_A_D3", "CAN_ADDR2",
 			  "CAN_ADDR3";
 };

 /*
  * Rename SoM signals according to board usage:
  *   GPIO_B_0      -> IO_EXP_INT
  *   GPIO_B_1      -> IO_EXP_RST
  */
 &gpio3 {
 	gpio-line-names = "PCIE_WAKE", "PCIE_CLKREQ", "PCIE_A_PERST", "SDIO_B_D5",
 			  "SDIO_B_D6", "SDIO_B_D7", "SPI_A_WP", "SPI_A_HOLD",
 			  "UART_B_RTS", "UART_B_CTS", "SDIO_B_D0", "SDIO_B_D1",
 			  "SDIO_B_D2", "SDIO_B_D3", "SDIO_B_WP", "SDIO_B_D4",
 			  "PCIE_SM_ALERT", "SDIO_B_CLK", "SDIO_B_CMD", "IO_EXP_INT",
 			  "IO_EXP_RST", "", "BOOT_SEL0", "BOOT_SEL1",
 			  "", "", "SDIO_B_CD", "SDIO_B_PWR_EN",
 			  "HDMI_CEC", "HDMI_HPD";
 };

 /*
  * Rename SoM signals according to board usage and remove labels for unsed pins:
  *   GPIO_A_6      -> TFT_RESET
  *   GPIO_A_7      -> TFT_STBY
  *   GPIO_B_3      -> CSI_ENABLE
  *   GPIO_B_2      -> USB_HUB_RST
  */
 &gpio4 {
 	gpio-line-names = "", "", "", "",
 			  "ETH_A_MDC", "ETH_A_MDIO", "ETH_A_RXD0", "ETH_A_RXD1",
 			  "ETH_A_RXD2", "ETH_A_RXD3", "ETH_A_RX_DV", "ETH_A_RX_CLK",
 			  "ETH_A_TXD0", "ETH_A_TXD1", "ETH_A_TXD2", "ETH_A_TXD3",
 			  "ETH_A_TX_EN", "ETH_A_TX_CLK", "CSI_ENABLE", "",
 			  "USB_HUB_RST", "TFT_RESET", "CAN_A_TX", "UART_A_CTS",
 			  "UART_A_RTS", "CAN_A_RX", "CAN_B_TX", "CAN_B_RX",
 			  "TFT_STBY", "CARRIER_PWR_EN", "I2S_A_DATA_IN", "I2S_LRCLK";
 };

 /*
  * Rename SoM signals according to board usage:
  *   SPI_A_SDI	-> CAN_ADDR0
  *   SPI_A_SDO	-> CAN_ADDR1
  */
 &gpio5 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_gpio5>;
 	gpio-line-names = "I2S_BITCLK", "I2S_A_DATA_OUT", "I2S_MCLK", "PWM_2",
 			  "PWM_1", "PWM_0", "SPI_A_SCK", "CAN_ADDR1",
 			  "CAN_ADDR0", "SPI_A_CS0", "SPI_B_SCK", "SPI_B_SDO",
 			  "SPI_B_SDI", "SPI_B_CS0", "I2C_A_SCL", "I2C_A_SDA",
 			  "I2C_B_SCL", "I2C_B_SDA", "PCIE_SMCLK", "PCIE_SMDAT",
 			  "I2C_CAM_SCL", "I2C_CAM_SDA", "UART_A_RX", "UART_A_TX",
 			  "UART_C_RX", "UART_C_TX", "UART_CON_RX", "UART_CON_TX",
 			  "UART_B_RX", "UART_B_TX";
 };

 &hdmi_pvi {
 	status = "okay";
 };

 &hdmi_tx {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_hdmi>;
 	ddc-i2c-bus = <&i2c2>;
 	status = "okay";
 };

 &hdmi_tx_phy {
 	status = "okay";
 };

 &i2c1 {
 	status = "okay";

 	gpio_expander_dio: io-expander@20 {
 		compatible = "ti,tca6408";
 		reg = <0x20>;
 		gpio-controller;
 		#gpio-cells = <2>;
 		gpio-line-names = "DIO1_OUT","DIO1_IN", "DIO2_OUT","DIO2_IN",
 				  "DIO3_OUT","DIO3_IN", "DIO4_OUT","DIO4_IN";
 		interrupt-parent = <&gpio3>;
 		interrupts = <19 IRQ_TYPE_EDGE_FALLING>;
 		reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
 	};
 };

 &i2c2 {
 	status = "okay";
 };

 &i2c4 {
 	status = "okay";
 };

 &lcdif3 {
 	status = "okay";
 };

 &pwm2 {
 	status = "okay";
 };

 &reg_usdhc2_vcc {
 	status = "disabled";
 };

 &snvs_pwrkey {
 	status = "okay";
 };

 &uart1 {
 	uart-has-rtscts;
 	status = "okay";
 };

 &uart4 {
 	linux,rs485-enabled-at-boot-time;
 	uart-has-rtscts;
 	status = "okay";
 };

 &usb_dwc3_0 {
 	adp-disable;
 	hnp-disable;
 	srp-disable;
 	dr_mode = "otg";
 	usb-role-switch;
 	role-switch-default-mode = "peripheral";
 	status = "okay";

 	port {
 		usb3_dwc: endpoint {
 			remote-endpoint = <&usb_dr_connector>;
 		};
 	};
 };

 &usb_dwc3_1 {
 	#address-cells = <1>;
 	#size-cells = <0>;
 	dr_mode = "host";
 	status = "okay";

 	usb-hub@1 {
 		compatible = "usb424,2514";
 		reg = <1>;
 		reset-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>;
 	};
 };

 &usb3_0 {
 	status = "okay";
 };

 &usb3_1 {
 	fsl,disable-port-power-control;
 	fsl,permanently-attached;
 	status = "okay";
 };

 &usb3_phy0 {
 	status = "okay";
 };

 &usb3_phy1 {
 	status = "okay";
 };

 &usdhc2 {
 	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
 	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
 	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
 	vmmc-supply = <&reg_vdd_3v3>;
 	status = "okay";
 };

 &iomuxc {
 	pinctrl_ethphy0: ethphy0grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01		0x46
 		>;
 	};

 	pinctrl_ethphy1: ethphy1grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00		0x46
 		>;
 	};

 	pinctrl_gpio2: gpio2grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19		0x46
 			MX8MP_IOMUXC_SD2_WP__GPIO2_IO20			0x46
 		>;
 	};

 	pinctrl_gpio5: gpio5grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_ECSPI1_MOSI__GPIO5_IO07		0x46 /* CAN_ADR0 */
 			MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08		0x46 /* CAN_ADR1 */
 		>;
 	};
 };
	// SPDX-License-Identifier: GPL-2.0+ OR MIT
	/*
	* Copyright (C) 2022 Kontron Electronics GmbH
	*/

	/dts-v1/;

	#include "imx8mp-kontron-osm-s.dtsi"

	/ {
	model = "Kontron BL i.MX8MP OSM-S";
	compatible = "kontron,imx8mp-bl-osm-s", "kontron,imx8mp-osm-s", "fsl,imx8mp";

	aliases {
	ethernet0 = &fec;
	ethernet1 = &eqos;
	};

	connector {
	compatible = "gpio-usb-b-connector", "usb-b-connector";
	id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
	label = "Type-C";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb1_id>;
	type = "micro";
	vbus-supply = <&reg_usb1_vbus>;

	port {
	usb_dr_connector: endpoint {
	remote-endpoint = <&usb3_dwc>;
	};
	};
	};

	leds {
	compatible = "gpio-leds";

	led1 {
	label = "led1";
	gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
	linux,default-trigger = "heartbeat";
	};
	};

	pwm-beeper {
	compatible = "pwm-beeper";
	pwms = <&pwm2 0 5000 0>;
	};

	reg_vcc_panel: regulator-vcc-panel {
	compatible = "regulator-fixed";
	gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
	enable-active-high;
	regulator-max-microvolt = <3300000>;
	regulator-min-microvolt = <3300000>;
	regulator-name = "VCC_PANEL";
	};
	};

	&ecspi2 {
	status = "okay";

	eeram@0 {
	compatible = "microchip,48l640";
	reg = <0>;
	spi-max-frequency = <20000000>;
	};
	};

	&eqos { /* Second ethernet (OSM-S ETH_B) */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_eqos_rgmii>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy1>;
	status = "okay";

	mdio {
	compatible = "snps,dwmac-mdio";
	#address-cells = <1>;
	#size-cells = <0>;

	ethphy1: ethernet-phy@1 {
	compatible = "ethernet-phy-id4f51.e91b";
	reg = <1>;
	pinctrl-0 = <&pinctrl_ethphy1>;
	pinctrl-names = "default";
	reset-assert-us = <10000>;
	reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
	};
	};
	};

	&fec { /* First ethernet (OSM-S ETH_A) */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet_rgmii>;
	phy-connection-type = "rgmii-id";
	phy-handle = <&ethphy0>;
	status = "okay";

	mdio {
	#address-cells = <1>;
	#size-cells = <0>;

	ethphy0: ethernet-phy@1 {
	compatible = "ethernet-phy-id4f51.e91b";
	reg = <1>;
	pinctrl-0 = <&pinctrl_ethphy0>;
	pinctrl-names = "default";
	reset-assert-us = <10000>;
	reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
	};
	};
	};

	&flexcan1 {
	status = "okay";
	};

	/*
	* Rename SoM signals according to board usage:
	* SDIO_A_PWR_EN -> CAN_ADDR2
	* SDIO_A_WP -> CAN_ADDR3
	*/
	&gpio2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpio2>;
	gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", "",
	"SDIO_A_CD", "SDIO_A_CLK", "SDIO_A_CMD", "SDIO_A_D0",
	"SDIO_A_D1", "SDIO_A_D2", "SDIO_A_D3", "CAN_ADDR2",
	"CAN_ADDR3";
	};

	/*
	* Rename SoM signals according to board usage:
	* GPIO_B_0 -> IO_EXP_INT
	* GPIO_B_1 -> IO_EXP_RST
	*/
	&gpio3 {
	gpio-line-names = "PCIE_WAKE", "PCIE_CLKREQ", "PCIE_A_PERST", "SDIO_B_D5",
	"SDIO_B_D6", "SDIO_B_D7", "SPI_A_WP", "SPI_A_HOLD",
	"UART_B_RTS", "UART_B_CTS", "SDIO_B_D0", "SDIO_B_D1",
	"SDIO_B_D2", "SDIO_B_D3", "SDIO_B_WP", "SDIO_B_D4",
	"PCIE_SM_ALERT", "SDIO_B_CLK", "SDIO_B_CMD", "IO_EXP_INT",
	"IO_EXP_RST", "", "BOOT_SEL0", "BOOT_SEL1",
	"", "", "SDIO_B_CD", "SDIO_B_PWR_EN",
	"HDMI_CEC", "HDMI_HPD";
	};

	/*
	* Rename SoM signals according to board usage and remove labels for unsed pins:
	* GPIO_A_6 -> TFT_RESET
	* GPIO_A_7 -> TFT_STBY
	* GPIO_B_3 -> CSI_ENABLE
	* GPIO_B_2 -> USB_HUB_RST
	*/
	&gpio4 {
	gpio-line-names = "", "", "", "",
	"ETH_A_MDC", "ETH_A_MDIO", "ETH_A_RXD0", "ETH_A_RXD1",
	"ETH_A_RXD2", "ETH_A_RXD3", "ETH_A_RX_DV", "ETH_A_RX_CLK",
	"ETH_A_TXD0", "ETH_A_TXD1", "ETH_A_TXD2", "ETH_A_TXD3",
	"ETH_A_TX_EN", "ETH_A_TX_CLK", "CSI_ENABLE", "",
	"USB_HUB_RST", "TFT_RESET", "CAN_A_TX", "UART_A_CTS",
	"UART_A_RTS", "CAN_A_RX", "CAN_B_TX", "CAN_B_RX",
	"TFT_STBY", "CARRIER_PWR_EN", "I2S_A_DATA_IN", "I2S_LRCLK";
	};

	/*
	* Rename SoM signals according to board usage:
	* SPI_A_SDI -> CAN_ADDR0
	* SPI_A_SDO -> CAN_ADDR1
	*/
	&gpio5 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpio5>;
	gpio-line-names = "I2S_BITCLK", "I2S_A_DATA_OUT", "I2S_MCLK", "PWM_2",
	"PWM_1", "PWM_0", "SPI_A_SCK", "CAN_ADDR1",
	"CAN_ADDR0", "SPI_A_CS0", "SPI_B_SCK", "SPI_B_SDO",
	"SPI_B_SDI", "SPI_B_CS0", "I2C_A_SCL", "I2C_A_SDA",
	"I2C_B_SCL", "I2C_B_SDA", "PCIE_SMCLK", "PCIE_SMDAT",
	"I2C_CAM_SCL", "I2C_CAM_SDA", "UART_A_RX", "UART_A_TX",
	"UART_C_RX", "UART_C_TX", "UART_CON_RX", "UART_CON_TX",
	"UART_B_RX", "UART_B_TX";
	};

	&hdmi_pvi {
	status = "okay";
	};

	&hdmi_tx {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hdmi>;
	ddc-i2c-bus = <&i2c2>;
	status = "okay";
	};

	&hdmi_tx_phy {
	status = "okay";
	};

	&i2c1 {
	status = "okay";

	gpio_expander_dio: io-expander@20 {
	compatible = "ti,tca6408";
	reg = <0x20>;
	gpio-controller;
	#gpio-cells = <2>;
	gpio-line-names = "DIO1_OUT","DIO1_IN", "DIO2_OUT","DIO2_IN",
	"DIO3_OUT","DIO3_IN", "DIO4_OUT","DIO4_IN";
	interrupt-parent = <&gpio3>;
	interrupts = <19 IRQ_TYPE_EDGE_FALLING>;
	reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
	};
	};

	&i2c2 {
	status = "okay";
	};

	&i2c4 {
	status = "okay";
	};

	&lcdif3 {
	status = "okay";
	};

	&pwm2 {
	status = "okay";
	};

	&reg_usdhc2_vcc {
	status = "disabled";
	};

	&snvs_pwrkey {
	status = "okay";
	};

	&uart1 {
	uart-has-rtscts;
	status = "okay";
	};

	&uart4 {
	linux,rs485-enabled-at-boot-time;
	uart-has-rtscts;
	status = "okay";
	};

	&usb_dwc3_0 {
	adp-disable;
	hnp-disable;
	srp-disable;
	dr_mode = "otg";
	usb-role-switch;
	role-switch-default-mode = "peripheral";
	status = "okay";

	port {
	usb3_dwc: endpoint {
	remote-endpoint = <&usb_dr_connector>;
	};
	};
	};

	&usb_dwc3_1 {
	#address-cells = <1>;
	#size-cells = <0>;
	dr_mode = "host";
	status = "okay";

	usb-hub@1 {
	compatible = "usb424,2514";
	reg = <1>;
	reset-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>;
	};
	};

	&usb3_0 {
	status = "okay";
	};

	&usb3_1 {
	fsl,disable-port-power-control;
	fsl,permanently-attached;
	status = "okay";
	};

	&usb3_phy0 {
	status = "okay";
	};

	&usb3_phy1 {
	status = "okay";
	};

	&usdhc2 {
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	vmmc-supply = <&reg_vdd_3v3>;
	status = "okay";
	};

	&iomuxc {
	pinctrl_ethphy0: ethphy0grp {
	fsl,pins = <
	MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x46
	>;
	};

	pinctrl_ethphy1: ethphy1grp {
	fsl,pins = <
	MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x46
	>;
	};

	pinctrl_gpio2: gpio2grp {
	fsl,pins = <
	MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x46
	MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x46
	>;
	};

	pinctrl_gpio5: gpio5grp {
	fsl,pins = <
	MX8MP_IOMUXC_ECSPI1_MOSI__GPIO5_IO07 0x46 /* CAN_ADR0 */
	MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x46 /* CAN_ADR1 */
	>;
	};
	};