| // SPDX-License-Identifier: (GPL-2.0 OR MIT) |
| /* |
| * Copyright 2024 TechNexion Ltd. |
| * |
| * Author: Ray Chang <ray.chang@technexion.com> |
| */ |
| |
| #include "imx8mp.dtsi" |
| |
| / { |
| chosen { |
| stdout-path = &uart2; |
| }; |
| |
| i2c_0: i2c { |
| compatible = "i2c-gpio"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-frequency = <100000>; |
| pinctrl-0 = <&pinctrl_i2c_brd_conf>; |
| pinctrl-names = "default"; |
| scl-gpios = <&gpio4 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| sda-gpios = <&gpio4 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| |
| eeprom: eeprom@53 { |
| compatible = "atmel,24c02"; |
| reg = <0x53>; |
| pagesize = <16>; |
| }; |
| }; |
| |
| memory@40000000 { |
| reg = <0x0 0x40000000 0 0xc0000000>, |
| <0x1 0x00000000 0 0xc0000000>; |
| device_type = "memory"; |
| }; |
| |
| reg_usdhc2_vmmc: regulator-usdhc2 { |
| compatible = "regulator-fixed"; |
| off-on-delay-us = <12000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-min-microvolt = <3300000>; |
| regulator-name = "VSD_3V3"; |
| startup-delay-us = <100>; |
| gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| }; |
| |
| rfkill { |
| compatible = "rfkill-gpio"; |
| name = "rfkill"; |
| pinctrl-0 = <&pinctrl_bt_ctrl>; |
| pinctrl-names = "default"; |
| radio-type = "bluetooth"; |
| shutdown-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; |
| }; |
| |
| wl_reg_on: regulator-wl-reg-on { |
| compatible = "regulator-fixed"; |
| off-on-delay-us = <20000>; |
| pinctrl-0 = <&pinctrl_wifi_ctrl>; |
| pinctrl-names = "default"; |
| regulator-max-microvolt = <3300000>; |
| regulator-min-microvolt = <3300000>; |
| regulator-name = "WL_REG_ON"; |
| startup-delay-us = <100>; |
| gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| }; |
| }; |
| |
| &A53_0 { |
| cpu-supply = <®_arm>; |
| }; |
| |
| &A53_1 { |
| cpu-supply = <®_arm>; |
| }; |
| |
| &A53_2 { |
| cpu-supply = <®_arm>; |
| }; |
| |
| &A53_3 { |
| cpu-supply = <®_arm>; |
| }; |
| |
| &ecspi1 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; |
| num-cs = <1>; |
| pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; |
| pinctrl-names = "default"; |
| }; |
| |
| &eqos { |
| phy-handle = <ðphy0>; |
| phy-mode = "rgmii-id"; |
| pinctrl-0 = <&pinctrl_eqos>; |
| pinctrl-names = "default"; |
| snps,force_thresh_dma_mode; |
| snps,mtl-rx-config = <&mtl_rx_setup>; |
| snps,mtl-tx-config = <&mtl_tx_setup>; |
| status = "okay"; |
| |
| mdio { |
| compatible = "snps,dwmac-mdio"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| ethphy0: ethernet-phy@1 { |
| compatible = "ethernet-phy-ieee802.3-c22"; |
| reg = <1>; |
| eee-broken-1000t; |
| reset-assert-us = <35000>; |
| reset-deassert-us = <75000>; |
| reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; |
| realtek,clkout-disable; |
| }; |
| }; |
| |
| mtl_rx_setup: rx-queues-config { |
| snps,rx-queues-to-use = <5>; |
| |
| queue0 { |
| snps,dcb-algorithm; |
| snps,map-to-dma-channel = <0>; |
| snps,priority = <0x1>; |
| }; |
| |
| queue1 { |
| snps,dcb-algorithm; |
| snps,map-to-dma-channel = <1>; |
| snps,priority = <0x2>; |
| }; |
| |
| queue2 { |
| snps,dcb-algorithm; |
| snps,map-to-dma-channel = <2>; |
| snps,priority = <0x4>; |
| }; |
| |
| queue3 { |
| snps,dcb-algorithm; |
| snps,map-to-dma-channel = <3>; |
| snps,priority = <0x8>; |
| }; |
| |
| queue4 { |
| snps,dcb-algorithm; |
| snps,map-to-dma-channel = <4>; |
| snps,priority = <0xf0>; |
| }; |
| }; |
| |
| mtl_tx_setup: tx-queues-config { |
| snps,tx-queues-to-use = <5>; |
| |
| queue0 { |
| snps,dcb-algorithm; |
| snps,priority = <0x1>; |
| }; |
| |
| queue1 { |
| snps,dcb-algorithm; |
| snps,priority = <0x2>; |
| }; |
| |
| queue2 { |
| snps,dcb-algorithm; |
| snps,priority = <0x4>; |
| }; |
| |
| queue3 { |
| snps,dcb-algorithm; |
| snps,priority = <0x8>; |
| }; |
| |
| queue4 { |
| snps,dcb-algorithm; |
| snps,priority = <0xf0>; |
| }; |
| }; |
| }; |
| |
| &flexcan1 { |
| pinctrl-0 = <&pinctrl_flexcan1>; |
| pinctrl-names = "default"; |
| }; |
| |
| &flexcan2 { |
| pinctrl-0 = <&pinctrl_flexcan2>; |
| pinctrl-names = "default"; |
| }; |
| |
| &i2c1 { |
| clock-frequency = <100000>; |
| pinctrl-0 = <&pinctrl_i2c1>; |
| pinctrl-names = "default"; |
| status = "okay"; |
| |
| pmic: pmic@25 { |
| compatible = "nxp,pca9450c"; |
| reg = <0x25>; |
| interrupt-parent = <&gpio1>; |
| interrupts = <3 IRQ_TYPE_LEVEL_LOW>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_pmic>; |
| |
| regulators { |
| BUCK1 { |
| regulator-always-on; |
| regulator-boot-on; |
| regulator-max-microvolt = <1000000>; |
| regulator-min-microvolt = <720000>; |
| regulator-name = "BUCK1"; |
| regulator-ramp-delay = <3125>; |
| }; |
| |
| reg_arm: BUCK2 { |
| regulator-always-on; |
| regulator-boot-on; |
| regulator-max-microvolt = <1025000>; |
| regulator-min-microvolt = <720000>; |
| regulator-name = "BUCK2"; |
| regulator-ramp-delay = <3125>; |
| nxp,dvs-run-voltage = <950000>; |
| nxp,dvs-standby-voltage = <850000>; |
| }; |
| |
| BUCK4 { |
| regulator-always-on; |
| regulator-boot-on; |
| regulator-max-microvolt = <3600000>; |
| regulator-min-microvolt = <3000000>; |
| regulator-name = "BUCK4"; |
| }; |
| |
| reg_buck5: BUCK5 { |
| regulator-always-on; |
| regulator-boot-on; |
| regulator-max-microvolt = <1950000>; |
| regulator-min-microvolt = <1650000>; |
| regulator-name = "BUCK5"; |
| }; |
| |
| BUCK6 { |
| regulator-always-on; |
| regulator-boot-on; |
| regulator-max-microvolt = <1155000>; |
| regulator-min-microvolt = <1045000>; |
| regulator-name = "BUCK6"; |
| }; |
| |
| LDO1 { |
| regulator-always-on; |
| regulator-boot-on; |
| regulator-max-microvolt = <1950000>; |
| regulator-min-microvolt = <1650000>; |
| regulator-name = "LDO1"; |
| }; |
| |
| LDO3 { |
| regulator-always-on; |
| regulator-boot-on; |
| regulator-max-microvolt = <1890000>; |
| regulator-min-microvolt = <1710000>; |
| regulator-name = "LDO3"; |
| }; |
| |
| LDO5 { |
| regulator-always-on; |
| regulator-boot-on; |
| regulator-max-microvolt = <3300000>; |
| regulator-min-microvolt = <1800000>; |
| regulator-name = "LDO5"; |
| }; |
| }; |
| }; |
| }; |
| |
| &i2c2 { |
| /* I2C_B on EDMG */ |
| clock-frequency = <400000>; |
| pinctrl-0 = <&pinctrl_i2c2>; |
| pinctrl-names = "default"; |
| }; |
| |
| &i2c3 { |
| clock-frequency = <100000>; |
| pinctrl-0 = <&pinctrl_i2c3>; |
| pinctrl-names = "default"; |
| }; |
| |
| &i2c4 { |
| /* I2C_A on EDMG */ |
| clock-frequency = <100000>; |
| pinctrl-0 = <&pinctrl_i2c4>; |
| pinctrl-names = "default"; |
| }; |
| |
| &i2c5 { |
| /* I2C_C on EDMG */ |
| clock-frequency = <400000>; |
| pinctrl-0 = <&pinctrl_i2c5>; |
| pinctrl-names = "default"; |
| }; |
| |
| &pcie { |
| pinctrl-0 = <&pinctrl_pcie>; |
| pinctrl-names = "default"; |
| reset-gpio = <&gpio1 1 GPIO_ACTIVE_LOW>; |
| }; |
| |
| &pwm1 { |
| pinctrl-0 = <&pinctrl_pwm1>; |
| pinctrl-names = "default"; |
| status = "okay"; |
| }; |
| |
| &pwm2 { |
| pinctrl-0 = <&pinctrl_pwm2>; |
| pinctrl-names = "default"; |
| status = "okay"; |
| }; |
| |
| &pwm3 { |
| pinctrl-0 = <&pinctrl_pwm3>; |
| pinctrl-names = "default"; |
| status = "okay"; |
| }; |
| |
| &pwm4 { |
| pinctrl-0 = <&pinctrl_pwm4>; |
| pinctrl-names = "default"; |
| status = "okay"; |
| }; |
| |
| &sai2 { |
| /* AUD_B on EDMG */ |
| assigned-clocks = <&clk IMX8MP_CLK_SAI2>; |
| assigned-clock-rates = <12288000>; |
| assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; |
| pinctrl-0 = <&pinctrl_sai2>; |
| pinctrl-names = "default"; |
| fsl,sai-mclk-direction-output; |
| status = "okay"; |
| }; |
| |
| &sai3 { |
| /* AUD_A on EDMG */ |
| assigned-clocks = <&clk IMX8MP_CLK_SAI3>; |
| assigned-clock-rates = <12288000>; |
| assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; |
| pinctrl-0 = <&pinctrl_sai3>; |
| pinctrl-names = "default"; |
| fsl,sai-mclk-direction-output; |
| status = "okay"; |
| }; |
| |
| &uart1 { |
| /* BT */ |
| assigned-clocks = <&clk IMX8MP_CLK_UART1>; |
| assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; |
| pinctrl-0 = <&pinctrl_uart1>; |
| pinctrl-names = "default"; |
| uart-has-rtscts; |
| status = "okay"; |
| }; |
| |
| &uart2 { |
| /* UART_A on EDMG, console */ |
| pinctrl-0 = <&pinctrl_uart2>; |
| pinctrl-names = "default"; |
| status = "okay"; |
| }; |
| |
| &uart3 { |
| /* UART_C on EDMG */ |
| assigned-clocks = <&clk IMX8MP_CLK_UART3>; |
| assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; |
| pinctrl-0 = <&pinctrl_uart3>; |
| pinctrl-names = "default"; |
| uart-has-rtscts; |
| status = "okay"; |
| }; |
| |
| &uart4 { |
| /* UART_B on EDMG */ |
| assigned-clocks = <&clk IMX8MP_CLK_UART4>; |
| assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; |
| pinctrl-0 = <&pinctrl_uart4>; |
| pinctrl-names = "default"; |
| uart-has-rtscts; |
| status = "okay"; |
| }; |
| |
| &usdhc1 { |
| /* WIFI SDIO */ |
| assigned-clocks = <&clk IMX8MP_CLK_USDHC1>; |
| assigned-clock-rates = <200000000>; |
| bus-width = <4>; |
| keep-power-in-suspend; |
| non-removable; |
| pinctrl-0 = <&pinctrl_usdhc1>; |
| pinctrl-1 = <&pinctrl_usdhc1_100mhz>; |
| pinctrl-2 = <&pinctrl_usdhc1_200mhz>; |
| pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| vmmc-supply = <&wl_reg_on>; |
| status = "okay"; |
| }; |
| |
| &usdhc2 { |
| /* SD card on baseboard */ |
| assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; |
| assigned-clock-rates = <400000000>; |
| bus-width = <4>; |
| cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; |
| pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; |
| pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; |
| pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; |
| pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| vmmc-supply = <®_usdhc2_vmmc>; |
| status = "okay"; |
| }; |
| |
| &usdhc3 { |
| /* eMMC on SOM */ |
| assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; |
| assigned-clock-rates = <400000000>; |
| bus-width = <8>; |
| non-removable; |
| pinctrl-0 = <&pinctrl_usdhc3>; |
| pinctrl-1 = <&pinctrl_usdhc3_100mhz>; |
| pinctrl-2 = <&pinctrl_usdhc3_200mhz>; |
| pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| status = "okay"; |
| }; |
| |
| &wdog1 { |
| pinctrl-0 = <&pinctrl_wdog>; |
| pinctrl-names = "default"; |
| fsl,ext-reset-output; |
| status = "okay"; |
| }; |
| |
| &iomuxc { |
| pinctrl-0 = <&pinctrl_hog>; |
| pinctrl-names = "default"; |
| |
| pinctrl_bt_ctrl: bt-ctrlgrp { |
| fsl,pins = < |
| MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x41 /* BT_REG_ON */ |
| MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x41 /* BT_WAKE_HOST */ |
| >; |
| }; |
| |
| pinctrl_ecspi1_cs: ecspi1csgrp { |
| fsl,pins = < |
| MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x40000 |
| >; |
| }; |
| |
| pinctrl_ecspi1: ecspi1grp { |
| fsl,pins = < |
| MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x82 |
| MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x82 |
| MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x82 |
| >; |
| }; |
| |
| pinctrl_eqos: eqosgrp { |
| fsl,pins = < |
| MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 |
| MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x23 |
| MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 |
| MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 |
| MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 |
| MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 |
| MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 |
| MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 |
| MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f |
| MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f |
| MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f |
| MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f |
| MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f |
| MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f |
| MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x19 |
| MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x19 |
| >; |
| }; |
| |
| pinctrl_flexcan1: flexcan1grp { |
| fsl,pins = < |
| MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x154 |
| MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x154 |
| >; |
| }; |
| |
| pinctrl_flexcan2: flexcan2grp { |
| fsl,pins = < |
| MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 |
| MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 |
| >; |
| }; |
| |
| pinctrl_hog: hoggrp { |
| fsl,pins = < |
| MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000019 |
| >; |
| }; |
| |
| pinctrl_i2c1: i2c1grp { |
| fsl,pins = < |
| MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001a3 |
| MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001a3 |
| >; |
| }; |
| |
| pinctrl_i2c2: i2c2grp { |
| fsl,pins = < |
| MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001a3 |
| MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001a3 |
| >; |
| }; |
| |
| pinctrl_i2c3: i2c3grp { |
| fsl,pins = < |
| MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 |
| MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 |
| >; |
| }; |
| |
| pinctrl_i2c4: i2c4grp { |
| fsl,pins = < |
| MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 |
| MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3 |
| >; |
| }; |
| |
| pinctrl_i2c5: i2c5grp { |
| fsl,pins = < |
| MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001a3 |
| MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001a3 |
| >; |
| }; |
| |
| pinctrl_i2c_brd_conf: i2cbrdconfgrp { |
| fsl,pins = < |
| MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x1c3 /* BRD_CONF_SCL, bitbang */ |
| MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x1c3 /* BRD_CONF_SDA, bitbang */ |
| >; |
| }; |
| |
| pinctrl_pcie: pciegrp { |
| fsl,pins = < |
| MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x41 /* PCIE CLKREQ */ |
| MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x41 /* PCIE WAKE */ |
| MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x41 /* PCIE RST */ |
| >; |
| }; |
| |
| pinctrl_pmic: pmicirqgrp { |
| fsl,pins = < |
| MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 |
| >; |
| }; |
| |
| pinctrl_pwm1: pwm1grp { |
| fsl,pins = < |
| MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x116 |
| >; |
| }; |
| |
| pinctrl_pwm2: pwm2grp { |
| fsl,pins = < |
| MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x116 |
| >; |
| }; |
| |
| pinctrl_pwm3: pwm3grp { |
| fsl,pins = < |
| MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT 0x116 |
| >; |
| }; |
| |
| pinctrl_pwm4: pwm4grp { |
| fsl,pins = < |
| MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x116 |
| >; |
| }; |
| |
| pinctrl_sai2: sai2grp { |
| fsl,pins = < |
| MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK 0xd6 |
| MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6 |
| MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6 |
| MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0xd6 |
| MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6 |
| >; |
| }; |
| |
| pinctrl_sai3: sai3grp { |
| fsl,pins = < |
| MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 |
| MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 |
| MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 |
| MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 |
| MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 |
| >; |
| }; |
| |
| pinctrl_uart1: uart1grp { |
| fsl,pins = < |
| MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 |
| MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 |
| MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 |
| MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 |
| >; |
| }; |
| |
| pinctrl_uart2: uart2grp { |
| fsl,pins = < |
| MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 |
| MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 |
| MX8MP_IOMUXC_UART4_RXD__UART2_DCE_CTS 0x140 |
| MX8MP_IOMUXC_UART4_TXD__UART2_DCE_RTS 0x140 |
| >; |
| }; |
| |
| pinctrl_uart3: uart3grp { |
| fsl,pins = < |
| MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX 0x140 |
| MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX 0x140 |
| MX8MP_IOMUXC_SD1_STROBE__UART3_DCE_CTS 0x140 |
| MX8MP_IOMUXC_SD1_RESET_B__UART3_DCE_RTS 0x140 |
| >; |
| }; |
| |
| pinctrl_uart4: uart4grp { |
| fsl,pins = < |
| MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DCE_RX 0x140 |
| MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DCE_TX 0x140 |
| MX8MP_IOMUXC_ECSPI2_MISO__UART4_DCE_CTS 0x140 |
| MX8MP_IOMUXC_ECSPI2_SS0__UART4_DCE_RTS 0x140 |
| >; |
| }; |
| |
| pinctrl_usdhc1: usdhc1grp { |
| fsl,pins = < |
| MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 |
| MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 |
| MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 |
| MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 |
| MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 |
| MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 |
| >; |
| }; |
| |
| pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { |
| fsl,pins = < |
| MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 |
| MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 |
| MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 |
| MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 |
| MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 |
| MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 |
| >; |
| }; |
| |
| pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { |
| fsl,pins = < |
| MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 |
| MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 |
| MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 |
| MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 |
| MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 |
| MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 |
| >; |
| }; |
| |
| pinctrl_usdhc2: usdhc2grp { |
| fsl,pins = < |
| MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 |
| MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 |
| MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 |
| MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 |
| MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 |
| MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 |
| MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 |
| >; |
| }; |
| |
| pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { |
| fsl,pins = < |
| MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 |
| MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 |
| MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 |
| MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 |
| MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 |
| MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 |
| MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 |
| >; |
| }; |
| |
| pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { |
| fsl,pins = < |
| MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 |
| MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 |
| MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 |
| MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 |
| MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 |
| MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 |
| MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 |
| >; |
| }; |
| |
| pinctrl_usdhc2_gpio: usdhc2-gpiogrp { |
| fsl,pins = < |
| MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 |
| MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 |
| >; |
| }; |
| |
| pinctrl_usdhc3: usdhc3grp { |
| fsl,pins = < |
| MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 |
| MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 |
| MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 |
| MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 |
| MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 |
| MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 |
| MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 |
| MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 |
| MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 |
| MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 |
| MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 |
| >; |
| }; |
| |
| pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { |
| fsl,pins = < |
| MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 |
| MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 |
| MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 |
| MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 |
| MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 |
| MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 |
| MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 |
| MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 |
| MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 |
| MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 |
| MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 |
| >; |
| }; |
| |
| pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { |
| fsl,pins = < |
| MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 |
| MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 |
| MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 |
| MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 |
| MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 |
| MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 |
| MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 |
| MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 |
| MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 |
| MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 |
| MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 |
| >; |
| }; |
| |
| pinctrl_wdog: wdoggrp { |
| fsl,pins = < |
| MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 |
| >; |
| }; |
| |
| pinctrl_wifi_ctrl: wifi-ctrlgrp { |
| fsl,pins = < |
| MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x41 /* WL_REG_ON */ |
| MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x41 /* WL_WAKE_HOST */ |
| >; |
| }; |
| }; |
