arch/arm64/boot/dts/apple/t8012.dtsi

// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
 * Apple T8012 "T2" SoC
 *
 * Other names: H9M, "Gibraltar"
 *
 * Copyright (c) 2024, Nick Chan <towinchenmi@gmail.com>
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/apple-aic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/apple.h>
#include <dt-bindings/spmi/spmi.h>

/ {
	interrupt-parent = <&aic>;
	#address-cells = <2>;
	#size-cells = <2>;

	clkref: clock-ref {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24000000>;
		clock-output-names = "clkref";
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu0: cpu@10000 {
			compatible = "apple,hurricane-zephyr";
			reg = <0x0 0x10000>;
			cpu-release-addr = <0 0>; /* To be filled by loader */
			operating-points-v2 = <&fusion_opp>;
			performance-domains = <&cpufreq>;
			enable-method = "spin-table";
			device_type = "cpu";
			next-level-cache = <&l2_cache>;
			i-cache-size = <0x10000>; /* P-core */
			d-cache-size = <0x10000>; /* P-core */
		};

		cpu1: cpu@10001 {
			compatible = "apple,hurricane-zephyr";
			reg = <0x0 0x10001>;
			cpu-release-addr = <0 0>; /* To be filled by loader */
			operating-points-v2 = <&fusion_opp>;
			performance-domains = <&cpufreq>;
			enable-method = "spin-table";
			device_type = "cpu";
			next-level-cache = <&l2_cache>;
			i-cache-size = <0x10000>; /* P-core */
			d-cache-size = <0x10000>; /* P-core */
		};

		l2_cache: l2-cache {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
			cache-size = <0x300000>; /* P-cluster */
		};
	};

	fusion_opp: opp-table {
		compatible = "operating-points-v2";

		/*
		 * Apple Fusion Architecture: Hardware big.LITTLE switcher
		 * that use p-state transitions to switch between cores.
		 * Only one type of core can be active at a given time.
		 *
		 * The E-core frequencies are adjusted so performance scales
		 * linearly with reported clock speed.
		 */

		opp01 {
			opp-hz = /bits/ 64 <172000000>; /* 300 MHz, E-core */
			opp-level = <1>;
			clock-latency-ns = <11000>;
		};
		opp02 {
			opp-hz = /bits/ 64 <230000000>; /* 396 MHz, E-core */
			opp-level = <2>;
			clock-latency-ns = <140000>;
		};
		opp03 {
			opp-hz = /bits/ 64 <425000000>; /* 732 MHz, E-core */
			opp-level = <3>;
			clock-latency-ns = <110000>;
		};
		opp04 {
			opp-hz = /bits/ 64 <637000000>; /* 1092 MHz, E-core */
			opp-level = <4>;
			clock-latency-ns = <130000>;
		};
		opp05 {
			opp-hz = /bits/ 64 <756000000>;
			opp-level = <5>;
			clock-latency-ns = <130000>;
		};
		opp06 {
			opp-hz = /bits/ 64 <1056000000>;
			opp-level = <6>;
			clock-latency-ns = <130000>;
		};
		opp07 {
			opp-hz = /bits/ 64 <1356000000>;
			opp-level = <7>;
			clock-latency-ns = <130000>;
		};
		opp08 {
			opp-hz = /bits/ 64 <1644000000>;
			opp-level = <8>;
			clock-latency-ns = <135000>;
		};
		opp09 {
			opp-hz = /bits/ 64 <1944000000>;
			opp-level = <9>;
			clock-latency-ns = <140000>;
		};
		opp10 {
			opp-hz = /bits/ 64 <2244000000>;
			opp-level = <10>;
			clock-latency-ns = <150000>;
		};
#if 0
		/* Not available until CPU deep sleep is implemented */
		opp11 {
			opp-hz = /bits/ 64 <2340000000>;
			opp-level = <11>;
			clock-latency-ns = <150000>;
			turbo-mode;
		};
#endif
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		nonposted-mmio;
		ranges;

		cpufreq: performance-controller@202f20000 {
			compatible = "apple,t8010-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
			reg = <0x2 0x02f20000 0 0x1000>;
			#performance-domain-cells = <0>;
		};

		serial0: serial@20a600000 {
			compatible = "apple,s5l-uart";
			reg = <0x2 0x0a600000 0x0 0x4000>;
			reg-io-width = <4>;
			interrupt-parent = <&aic>;
			interrupts = <AIC_IRQ 271 IRQ_TYPE_LEVEL_HIGH>;
			/* Use the bootloader-enabled clocks for now. */
			clocks = <&clkref>, <&clkref>;
			clock-names = "uart", "clk_uart_baud0";
			power-domains = <&ps_uart0>;
			status = "disabled";
		};

		pmgr: power-management@20e000000 {
			compatible = "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd";
			#address-cells = <1>;
			#size-cells = <1>;

			reg = <0x2 0xe000000 0 0x8c000>;
		};

		aic: interrupt-controller@20e100000 {
			compatible = "apple,t8010-aic", "apple,aic";
			reg = <0x2 0x0e100000 0x0 0x100000>;
			#interrupt-cells = <3>;
			interrupt-controller;
			power-domains = <&ps_aic>;
		};

		pinctrl_ap: pinctrl@20f100000 {
			compatible = "apple,t8010-pinctrl", "apple,pinctrl";
			reg = <0x2 0x0f100000 0x0 0x100000>;
			power-domains = <&ps_gpio>;

			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl_ap 0 0 221>;
			apple,npins = <221>;

			interrupt-controller;
			#interrupt-cells = <2>;
			interrupt-parent = <&aic>;
			interrupts = <AIC_IRQ 45 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 46 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 47 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 48 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 49 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 50 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 51 IRQ_TYPE_LEVEL_HIGH>;
		};

		pinctrl_aop: pinctrl@2100f0000 {
			compatible = "apple,t8010-pinctrl", "apple,pinctrl";
			reg = <0x2 0x0100f0000 0x0 0x10000>;

			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl_aop 0 0 41>;
			apple,npins = <41>;

			interrupt-controller;
			#interrupt-cells = <2>;
			interrupt-parent = <&aic>;
			interrupts = <AIC_IRQ 131 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 132 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 133 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 134 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 135 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 136 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 137 IRQ_TYPE_LEVEL_HIGH>;
		};

		spmi: spmi@211180700 {
			compatible = "apple,t8012-spmi", "apple,t8103-spmi";
			reg = <0x2 0x11180700 0x0 0x100>;
			#address-cells = <2>;
			#size-cells = <0>;
		};

		pinctrl_nub: pinctrl@2111f0000 {
			compatible = "apple,t8010-pinctrl", "apple,pinctrl";
			reg = <0x2 0x111f0000 0x0 0x1000>;

			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl_nub 0 0 19>;
			apple,npins = <19>;

			interrupt-controller;
			#interrupt-cells = <2>;
			interrupt-parent = <&aic>;
			interrupts = <AIC_IRQ 164 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 165 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 166 IRQ_TYPE_LEVEL_HIGH>;
		};

		pmgr_mini: power-management@211200000 {
			compatible = "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd";
			#address-cells = <1>;
			#size-cells = <1>;

			reg = <0x2 0x11200000 0 0x84000>;
		};

		wdt: watchdog@2112b0000 {
			compatible = "apple,t8010-wdt", "apple,wdt";
			reg = <0x2 0x112b0000 0x0 0x4000>;
			clocks = <&clkref>;
			interrupt-parent = <&aic>;
			interrupts = <AIC_IRQ 168 IRQ_TYPE_LEVEL_HIGH>;
		};

		pinctrl_smc: pinctrl@212024000 {
			compatible = "apple,t8010-pinctrl", "apple,pinctrl";
			reg = <0x2 0x12024000 0x0 0x1000>;
			power-domains = <&ps_smc_cpu>;

			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl_smc 0 0 81>;
			apple,npins = <81>;

			interrupt-controller;
			#interrupt-cells = <2>;
			interrupt-parent = <&aic>;
			interrupts = <AIC_IRQ 195 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 196 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 197 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 198 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 199 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 200 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 201 IRQ_TYPE_LEVEL_HIGH>;
			/*
			 * SMC is not yet supported and accessing this pinctrl while SMC is
			 * suspended results in a hang.
			 */
			status = "disabled";
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&aic>;
		interrupt-names = "phys", "virt";
		/* Note that T2 doesn't actually have a hypervisor (EL2 is not implemented). */
		interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>,
			     <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>;
	};
};

#include "t8012-pmgr.dtsi"