| // SPDX-License-Identifier: GPL-2.0 OR MIT |
| /* |
| * Apple T8010 "A10" SoC |
| * |
| * Other names: H9P, "Cayman" |
| * |
| * Copyright (c) 2022, Konrad Dybcio <konradybcio@kernel.org> |
| */ |
| |
| #include <dt-bindings/gpio/gpio.h> |
| #include <dt-bindings/interrupt-controller/apple-aic.h> |
| #include <dt-bindings/interrupt-controller/irq.h> |
| #include <dt-bindings/pinctrl/apple.h> |
| |
| / { |
| interrupt-parent = <&aic>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| clkref: clock-ref { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <24000000>; |
| clock-output-names = "clkref"; |
| }; |
| |
| cpus { |
| #address-cells = <2>; |
| #size-cells = <0>; |
| |
| cpu0: cpu@0 { |
| compatible = "apple,hurricane-zephyr"; |
| reg = <0x0 0x0>; |
| cpu-release-addr = <0 0>; /* To be filled by loader */ |
| operating-points-v2 = <&fusion_opp>; |
| performance-domains = <&cpufreq>; |
| enable-method = "spin-table"; |
| device_type = "cpu"; |
| next-level-cache = <&l2_cache>; |
| i-cache-size = <0x10000>; /* P-core */ |
| d-cache-size = <0x10000>; /* P-core */ |
| }; |
| |
| cpu1: cpu@1 { |
| compatible = "apple,hurricane-zephyr"; |
| reg = <0x0 0x1>; |
| cpu-release-addr = <0 0>; /* To be filled by loader */ |
| operating-points-v2 = <&fusion_opp>; |
| performance-domains = <&cpufreq>; |
| enable-method = "spin-table"; |
| device_type = "cpu"; |
| next-level-cache = <&l2_cache>; |
| i-cache-size = <0x10000>; /* P-core */ |
| d-cache-size = <0x10000>; /* P-core */ |
| }; |
| |
| l2_cache: l2-cache { |
| compatible = "cache"; |
| cache-level = <2>; |
| cache-unified; |
| cache-size = <0x300000>; /* P-cluster */ |
| }; |
| }; |
| |
| fusion_opp: opp-table { |
| compatible = "operating-points-v2"; |
| |
| /* |
| * Apple Fusion Architecture: Hardware big.LITTLE switcher |
| * that use p-state transitions to switch between cores. |
| * Only one type of core can be active at a given time. |
| * |
| * The E-core frequencies are adjusted so performance scales |
| * linearly with reported clock speed. |
| */ |
| |
| opp01 { |
| opp-hz = /bits/ 64 <172000000>; /* 300 MHz, E-core */ |
| opp-level = <1>; |
| clock-latency-ns = <11000>; |
| }; |
| opp02 { |
| opp-hz = /bits/ 64 <230000000>; /* 396 MHz, E-core */ |
| opp-level = <2>; |
| clock-latency-ns = <49000>; |
| }; |
| opp03 { |
| opp-hz = /bits/ 64 <425000000>; /* 732 MHz, E-core */ |
| opp-level = <3>; |
| clock-latency-ns = <13000>; |
| }; |
| opp04 { |
| opp-hz = /bits/ 64 <637000000>; /* 1092 MHz, E-core */ |
| opp-level = <4>; |
| clock-latency-ns = <18000>; |
| }; |
| opp05 { |
| opp-hz = /bits/ 64 <756000000>; |
| opp-level = <5>; |
| clock-latency-ns = <35000>; |
| }; |
| opp06 { |
| opp-hz = /bits/ 64 <1056000000>; |
| opp-level = <6>; |
| clock-latency-ns = <31000>; |
| }; |
| opp07 { |
| opp-hz = /bits/ 64 <1356000000>; |
| opp-level = <7>; |
| clock-latency-ns = <37000>; |
| }; |
| opp08 { |
| opp-hz = /bits/ 64 <1644000000>; |
| opp-level = <8>; |
| clock-latency-ns = <39500>; |
| }; |
| hurricane_opp09: opp09 { |
| opp-hz = /bits/ 64 <1944000000>; |
| opp-level = <9>; |
| clock-latency-ns = <46000>; |
| status = "disabled"; /* Not available on N112 */ |
| }; |
| hurricane_opp10: opp10 { |
| opp-hz = /bits/ 64 <2244000000>; |
| opp-level = <10>; |
| clock-latency-ns = <56000>; |
| status = "disabled"; /* Not available on N112 */ |
| }; |
| #if 0 |
| /* Not available until CPU deep sleep is implemented */ |
| hurricane_opp11: opp11 { |
| opp-hz = /bits/ 64 <2340000000>; |
| opp-level = <11>; |
| clock-latency-ns = <56000>; |
| turbo-mode; |
| status = "disabled"; /* Not available on N112 */ |
| }; |
| #endif |
| }; |
| |
| soc { |
| compatible = "simple-bus"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| nonposted-mmio; |
| ranges; |
| |
| cpufreq: performance-controller@202f20000 { |
| compatible = "apple,t8010-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; |
| reg = <0x2 0x02f20000 0 0x1000>; |
| #performance-domain-cells = <0>; |
| }; |
| |
| serial0: serial@20a0c0000 { |
| compatible = "apple,s5l-uart"; |
| reg = <0x2 0x0a0c0000 0x0 0x4000>; |
| reg-io-width = <4>; |
| interrupt-parent = <&aic>; |
| interrupts = <AIC_IRQ 218 IRQ_TYPE_LEVEL_HIGH>; |
| /* Use the bootloader-enabled clocks for now. */ |
| clocks = <&clkref>, <&clkref>; |
| clock-names = "uart", "clk_uart_baud0"; |
| power-domains = <&ps_uart0>; |
| status = "disabled"; |
| }; |
| |
| i2c0: i2c@20a110000 { |
| compatible = "apple,t8010-i2c", "apple,i2c"; |
| reg = <0x2 0x0a110000 0x0 0x1000>; |
| clocks = <&clkref>; |
| interrupt-parent = <&aic>; |
| interrupts = <AIC_IRQ 232 IRQ_TYPE_LEVEL_HIGH>; |
| pinctrl-0 = <&i2c0_pins>; |
| pinctrl-names = "default"; |
| power-domains = <&ps_i2c0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@20a111000 { |
| compatible = "apple,t8010-i2c", "apple,i2c"; |
| reg = <0x2 0x0a111000 0x0 0x1000>; |
| clocks = <&clkref>; |
| interrupt-parent = <&aic>; |
| interrupts = <AIC_IRQ 233 IRQ_TYPE_LEVEL_HIGH>; |
| pinctrl-0 = <&i2c1_pins>; |
| pinctrl-names = "default"; |
| power-domains = <&ps_i2c1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@20a112000 { |
| compatible = "apple,t8010-i2c", "apple,i2c"; |
| reg = <0x2 0x0a112000 0x0 0x1000>; |
| clocks = <&clkref>; |
| interrupt-parent = <&aic>; |
| interrupts = <AIC_IRQ 234 IRQ_TYPE_LEVEL_HIGH>; |
| pinctrl-0 = <&i2c2_pins>; |
| pinctrl-names = "default"; |
| power-domains = <&ps_i2c2>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@20a113000 { |
| compatible = "apple,t8010-i2c", "apple,i2c"; |
| reg = <0x2 0x0a113000 0x0 0x1000>; |
| clocks = <&clkref>; |
| interrupt-parent = <&aic>; |
| interrupts = <AIC_IRQ 235 IRQ_TYPE_LEVEL_HIGH>; |
| pinctrl-0 = <&i2c3_pins>; |
| pinctrl-names = "default"; |
| power-domains = <&ps_i2c3>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| pmgr: power-management@20e000000 { |
| compatible = "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| reg = <0x2 0xe000000 0 0x8c000>; |
| }; |
| |
| aic: interrupt-controller@20e100000 { |
| compatible = "apple,t8010-aic", "apple,aic"; |
| reg = <0x2 0x0e100000 0x0 0x100000>; |
| #interrupt-cells = <3>; |
| interrupt-controller; |
| power-domains = <&ps_aic>; |
| }; |
| |
| dwi_bl: backlight@20e200080 { |
| compatible = "apple,t8010-dwi-bl", "apple,dwi-bl"; |
| reg = <0x2 0x0e200080 0x0 0x8>; |
| power-domains = <&ps_dwi>; |
| status = "disabled"; |
| }; |
| |
| pinctrl_ap: pinctrl@20f100000 { |
| compatible = "apple,t8010-pinctrl", "apple,pinctrl"; |
| reg = <0x2 0x0f100000 0x0 0x100000>; |
| power-domains = <&ps_gpio>; |
| |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pinctrl_ap 0 0 208>; |
| apple,npins = <208>; |
| |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| interrupt-parent = <&aic>; |
| interrupts = <AIC_IRQ 42 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 43 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 44 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 45 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 46 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 47 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 48 IRQ_TYPE_LEVEL_HIGH>; |
| |
| i2c0_pins: i2c0-pins { |
| pinmux = <APPLE_PINMUX(197, 1)>, |
| <APPLE_PINMUX(196, 1)>; |
| }; |
| |
| i2c1_pins: i2c1-pins { |
| pinmux = <APPLE_PINMUX(40, 1)>, |
| <APPLE_PINMUX(39, 1)>; |
| }; |
| |
| i2c2_pins: i2c2-pins { |
| pinmux = <APPLE_PINMUX(132, 1)>, |
| <APPLE_PINMUX(133, 1)>; |
| }; |
| |
| i2c3_pins: i2c3-pins { |
| pinmux = <APPLE_PINMUX(41, 1)>, |
| <APPLE_PINMUX(42, 1)>; |
| }; |
| }; |
| |
| pinctrl_aop: pinctrl@2100f0000 { |
| compatible = "apple,t8010-pinctrl", "apple,pinctrl"; |
| reg = <0x2 0x100f0000 0x0 0x100000>; |
| power-domains = <&ps_aop_gpio>; |
| |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pinctrl_aop 0 0 42>; |
| apple,npins = <42>; |
| |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| interrupt-parent = <&aic>; |
| interrupts = <AIC_IRQ 128 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 129 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 130 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 131 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 132 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 133 IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_IRQ 134 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| pmgr_mini: power-management@210200000 { |
| compatible = "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| reg = <0x2 0x10200000 0 0x84000>; |
| }; |
| |
| wdt: watchdog@2102b0000 { |
| compatible = "apple,t8010-wdt", "apple,wdt"; |
| reg = <0x2 0x102b0000 0x0 0x4000>; |
| clocks = <&clkref>; |
| interrupt-parent = <&aic>; |
| interrupts = <AIC_IRQ 4 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupt-parent = <&aic>; |
| interrupt-names = "phys", "virt"; |
| /* Note that A10 doesn't actually have a hypervisor (EL2 is not implemented). */ |
| interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, |
| <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| }; |
| |
| #include "t8010-pmgr.dtsi" |
