Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml

# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Microchip PolarFire SoC Microprocessor Subsystem (MSS) sysreg register region

maintainers:
  - Conor Dooley <conor.dooley@microchip.com>

description:
  An wide assortment of registers that control elements of the MSS on PolarFire
  SoC, including pinmuxing, resets and clocks among others.

properties:
  compatible:
    items:
      - const: microchip,mpfs-mss-top-sysreg
      - const: syscon
      - const: simple-mfd

  reg:
    maxItems: 1

  '#address-cells':
    const: 1

  '#size-cells':
    const: 1

  '#reset-cells':
    description:
      The AHB/AXI peripherals on the PolarFire SoC have reset support, so
      from CLK_ENVM to CLK_CFM. The reset consumer should specify the
      desired peripheral via the clock ID in its "resets" phandle cell.
      See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list
      of PolarFire clock/reset IDs.
    const: 1

  pinctrl@200:
    type: object
    $ref: /schemas/pinctrl/microchip,mpfs-pinctrl-iomux0.yaml

  pinctrl@204:
    type: object
    $ref: /schemas/pinctrl/microchip,mpfs-pinctrl-mssio.yaml

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    syscon@20002000 {
      compatible = "microchip,mpfs-mss-top-sysreg", "syscon", "simple-mfd";
      reg = <0x20002000 0x1000>;
      #reset-cells = <1>;
    };