Documentation/devicetree/bindings/opp/opp-v2-qcom-adreno.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/opp/opp-v2-qcom-adreno.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Adreno compatible OPP supply

description:
  Adreno GPUs present in Qualcomm's Snapdragon chipsets uses an OPP specific
  ACD related information tailored for the specific chipset. This binding
  provides the information needed to describe such a hardware value.

maintainers:
  - Rob Clark <robdclark@gmail.com>

allOf:
  - $ref: opp-v2-base.yaml#

properties:
  compatible:
    contains:
      const: operating-points-v2-adreno

patternProperties:
  '^opp(-[0-9]+){1,2}$':
    type: object
    additionalProperties: false

    properties:
      opp-hz: true

      opp-level: true

      opp-peak-kBps: true

      opp-supported-hw: true

      qcom,opp-acd-level:
        description: |
          A positive value representing the ACD (Adaptive Clock Distribution,
          a fancy name for clk throttling during voltage droop) level associated
          with this OPP node. This value is shared to a co-processor inside GPU
          (called Graphics Management Unit a.k.a GMU) during wake up. It may not
          be present for some OPPs and GMU will disable ACD while transitioning
          to that OPP. This value encodes a voltage threshold, delay cycles &
          calibration margins which are identified by characterization of the
          SoC. So, it doesn't have any unit. This data is passed to GMU firmware
          via 'HFI_H2F_MSG_ACD' packet.
        $ref: /schemas/types.yaml#/definitions/uint32

    required:
      - opp-hz
      - opp-level

required:
  - compatible

additionalProperties: false

examples:
  - |
    #include <dt-bindings/power/qcom-rpmpd.h>

    gpu_opp_table: opp-table {
        compatible = "operating-points-v2-adreno", "operating-points-v2";

        opp-687000000 {
            opp-hz = /bits/ 64 <687000000>;
            opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
            opp-peak-kBps = <8171875>;
            qcom,opp-acd-level = <0x882e5ffd>;
        };

        opp-550000000 {
            opp-hz = /bits/ 64 <550000000>;
            opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
            opp-peak-kBps = <6074219>;
            qcom,opp-acd-level = <0xc0285ffd>;
        };

        opp-390000000 {
            opp-hz = /bits/ 64 <390000000>;
            opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
            opp-peak-kBps = <3000000>;
            qcom,opp-acd-level = <0xc0285ffd>;
        };

        opp-300000000 {
            opp-hz = /bits/ 64 <300000000>;
            opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
            opp-peak-kBps = <2136719>;
            /* Intentionally left out qcom,opp-acd-level property here */
        };

    };