| # SPDX-License-Identifier: GPL-2.0 | |
| %YAML 1.2 | |
| --- | |
| $id: http://devicetree.org/schemas/mmc/mtk-sd.yaml# | |
| $schema: http://devicetree.org/meta-schemas/core.yaml# | |
| title: MTK MSDC Storage Host Controller | |
| maintainers: | |
| - Chaotian Jing <chaotian.jing@mediatek.com> | |
| - Wenbin Mei <wenbin.mei@mediatek.com> | |
| properties: | |
| compatible: | |
| oneOf: | |
| - enum: | |
| - mediatek,mt2701-mmc | |
| - mediatek,mt2712-mmc | |
| - mediatek,mt6779-mmc | |
| - mediatek,mt6795-mmc | |
| - mediatek,mt7620-mmc | |
| - mediatek,mt7622-mmc | |
| - mediatek,mt7986-mmc | |
| - mediatek,mt7988-mmc | |
| - mediatek,mt8135-mmc | |
| - mediatek,mt8173-mmc | |
| - mediatek,mt8183-mmc | |
| - mediatek,mt8189-mmc | |
| - mediatek,mt8196-mmc | |
| - mediatek,mt8516-mmc | |
| - items: | |
| - const: mediatek,mt7623-mmc | |
| - const: mediatek,mt2701-mmc | |
| - items: | |
| - enum: | |
| - mediatek,mt6893-mmc | |
| - mediatek,mt8186-mmc | |
| - mediatek,mt8188-mmc | |
| - mediatek,mt8192-mmc | |
| - mediatek,mt8195-mmc | |
| - mediatek,mt8365-mmc | |
| - const: mediatek,mt8183-mmc | |
| reg: | |
| minItems: 1 | |
| items: | |
| - description: base register (required). | |
| - description: top base register (required for MT8183). | |
| clocks: | |
| description: | |
| Should contain phandle for the clock feeding the MMC controller. | |
| minItems: 2 | |
| maxItems: 7 | |
| clock-names: | |
| minItems: 2 | |
| maxItems: 7 | |
| interrupts: | |
| description: | |
| Should at least contain MSDC GIC interrupt. To support SDIO in-band wakeup, an extended | |
| interrupt is required and be configured as wakeup source irq. | |
| minItems: 1 | |
| maxItems: 2 | |
| interrupt-names: | |
| items: | |
| - const: msdc | |
| - const: sdio_wakeup | |
| pinctrl-names: | |
| description: | |
| Should at least contain default and state_uhs. To support SDIO in-band wakeup, dat1 pin | |
| will be switched between GPIO mode and SDIO DAT1 mode, state_eint is mandatory in this | |
| scenario. | |
| minItems: 2 | |
| items: | |
| - const: default | |
| - const: state_uhs | |
| - const: state_eint | |
| pinctrl-0: | |
| description: | |
| should contain default/high speed pin ctrl. | |
| maxItems: 1 | |
| pinctrl-1: | |
| description: | |
| should contain uhs mode pin ctrl. | |
| maxItems: 1 | |
| pinctrl-2: | |
| description: | |
| should switch dat1 pin to GPIO mode. | |
| maxItems: 1 | |
| hs400-ds-delay: | |
| $ref: /schemas/types.yaml#/definitions/uint32 | |
| description: | |
| HS400 DS delay setting. | |
| minimum: 0 | |
| maximum: 0xffffffff | |
| mediatek,hs200-cmd-int-delay: | |
| $ref: /schemas/types.yaml#/definitions/uint32 | |
| description: | |
| HS200 command internal delay setting. | |
| This field has total 32 stages. | |
| The value is an integer from 0 to 31. | |
| minimum: 0 | |
| maximum: 31 | |
| mediatek,hs400-cmd-int-delay: | |
| $ref: /schemas/types.yaml#/definitions/uint32 | |
| description: | |
| HS400 command internal delay setting. | |
| This field has total 32 stages. | |
| The value is an integer from 0 to 31. | |
| minimum: 0 | |
| maximum: 31 | |
| mediatek,hs400-cmd-resp-sel-rising: | |
| $ref: /schemas/types.yaml#/definitions/flag | |
| description: | |
| HS400 command response sample selection. | |
| If present, HS400 command responses are sampled on rising edges. | |
| If not present, HS400 command responses are sampled on falling edges. | |
| mediatek,hs400-ds-dly3: | |
| $ref: /schemas/types.yaml#/definitions/uint32 | |
| description: | |
| Gear of the third delay line for DS for input data latch in data | |
| pad macro, there are 32 stages from 0 to 31. | |
| For different corner IC, the time is different about one step, it is | |
| about 100ps. | |
| The value is confirmed by doing scan and calibration to find a best | |
| value with corner IC and it is valid only for HS400 mode. | |
| minimum: 0 | |
| maximum: 31 | |
| mediatek,latch-ck: | |
| $ref: /schemas/types.yaml#/definitions/uint32 | |
| description: | |
| Some SoCs do not support enhance_rx, need set correct latch-ck to avoid | |
| data crc error caused by stop clock(fifo full) Valid range = [0:0x7]. | |
| if not present, default value is 0. | |
| applied to compatible "mediatek,mt2701-mmc". | |
| minimum: 0 | |
| maximum: 7 | |
| mediatek,tuning-step: | |
| $ref: /schemas/types.yaml#/definitions/uint32 | |
| description: | |
| Some SoCs need extend tuning step for better delay value to avoid CRC issue. | |
| If not present, default tuning step is 32. For eMMC and SD, this can yield | |
| satisfactory calibration results in most cases. | |
| enum: [32, 64] | |
| default: 32 | |
| resets: | |
| maxItems: 1 | |
| reset-names: | |
| const: hrst | |
| required: | |
| - compatible | |
| - reg | |
| - interrupts | |
| - clocks | |
| - clock-names | |
| - pinctrl-names | |
| - pinctrl-0 | |
| - pinctrl-1 | |
| - vmmc-supply | |
| - vqmmc-supply | |
| allOf: | |
| - $ref: mmc-controller.yaml# | |
| - if: | |
| properties: | |
| compatible: | |
| enum: | |
| - mediatek,mt2701-mmc | |
| - mediatek,mt6779-mmc | |
| - mediatek,mt6795-mmc | |
| - mediatek,mt7620-mmc | |
| - mediatek,mt7622-mmc | |
| - mediatek,mt7623-mmc | |
| - mediatek,mt8135-mmc | |
| - mediatek,mt8173-mmc | |
| - mediatek,mt8183-mmc | |
| - mediatek,mt8186-mmc | |
| - mediatek,mt8188-mmc | |
| - mediatek,mt8195-mmc | |
| - mediatek,mt8196-mmc | |
| - mediatek,mt8516-mmc | |
| then: | |
| properties: | |
| clocks: | |
| minItems: 2 | |
| items: | |
| - description: source clock | |
| - description: HCLK which used for host | |
| - description: independent source clock gate | |
| clock-names: | |
| minItems: 2 | |
| items: | |
| - const: source | |
| - const: hclk | |
| - const: source_cg | |
| - if: | |
| properties: | |
| compatible: | |
| contains: | |
| const: mediatek,mt2712-mmc | |
| then: | |
| properties: | |
| clocks: | |
| minItems: 3 | |
| items: | |
| - description: source clock | |
| - description: HCLK which used for host | |
| - description: independent source clock gate | |
| - description: bus clock used for internal register access (required for MSDC0/3). | |
| clock-names: | |
| minItems: 3 | |
| items: | |
| - const: source | |
| - const: hclk | |
| - const: source_cg | |
| - const: bus_clk | |
| - if: | |
| properties: | |
| compatible: | |
| contains: | |
| enum: | |
| - mediatek,mt7986-mmc | |
| - mediatek,mt7988-mmc | |
| - mediatek,mt8183-mmc | |
| - mediatek,mt8189-mmc | |
| - mediatek,mt8196-mmc | |
| then: | |
| properties: | |
| reg: | |
| minItems: 2 | |
| else: | |
| properties: | |
| reg: | |
| maxItems: 1 | |
| - if: | |
| properties: | |
| compatible: | |
| contains: | |
| enum: | |
| - mediatek,mt7986-mmc | |
| then: | |
| properties: | |
| clocks: | |
| minItems: 3 | |
| items: | |
| - description: source clock | |
| - description: HCLK which used for host | |
| - description: independent source clock gate | |
| - description: bus clock used for internal register access (required for MSDC0/3). | |
| - description: msdc subsys clock gate | |
| clock-names: | |
| minItems: 3 | |
| items: | |
| - const: source | |
| - const: hclk | |
| - const: source_cg | |
| - const: bus_clk | |
| - const: sys_cg | |
| - if: | |
| properties: | |
| compatible: | |
| contains: | |
| enum: | |
| - mediatek,mt7988-mmc | |
| then: | |
| properties: | |
| clocks: | |
| items: | |
| - description: source clock | |
| - description: HCLK which used for host | |
| - description: Advanced eXtensible Interface | |
| - description: Advanced High-performance Bus clock | |
| clock-names: | |
| items: | |
| - const: source | |
| - const: hclk | |
| - const: axi_cg | |
| - const: ahb_cg | |
| - if: | |
| properties: | |
| compatible: | |
| enum: | |
| - mediatek,mt6893-mmc | |
| - mediatek,mt8186-mmc | |
| - mediatek,mt8188-mmc | |
| - mediatek,mt8195-mmc | |
| then: | |
| properties: | |
| clocks: | |
| items: | |
| - description: source clock | |
| - description: HCLK which used for host | |
| - description: independent source clock gate | |
| - description: crypto clock used for data encrypt/decrypt (optional) | |
| clock-names: | |
| items: | |
| - const: source | |
| - const: hclk | |
| - const: source_cg | |
| - const: crypto | |
| - if: | |
| properties: | |
| compatible: | |
| contains: | |
| const: mediatek,mt8192-mmc | |
| then: | |
| properties: | |
| clocks: | |
| items: | |
| - description: source clock | |
| - description: HCLK which used for host | |
| - description: independent source clock gate | |
| - description: msdc subsys clock gate | |
| - description: peripheral bus clock gate | |
| - description: AXI bus clock gate | |
| - description: AHB bus clock gate | |
| clock-names: | |
| items: | |
| - const: source | |
| - const: hclk | |
| - const: source_cg | |
| - const: sys_cg | |
| - const: pclk_cg | |
| - const: axi_cg | |
| - const: ahb_cg | |
| - if: | |
| properties: | |
| compatible: | |
| contains: | |
| const: mediatek,mt8189-mmc | |
| then: | |
| properties: | |
| clocks: | |
| minItems: 6 | |
| items: | |
| - description: source clock | |
| - description: HCLK which used for host | |
| - description: independent source clock gate | |
| - description: bus clock used for internal register access | |
| - description: peripheral bus clock gate | |
| - description: AXI bus clock gate | |
| - description: crypto clock used for data encrypt/decrypt (optional) | |
| clock-names: | |
| minItems: 6 | |
| items: | |
| - const: source | |
| - const: hclk | |
| - const: source_cg | |
| - const: bus_clk | |
| - const: pclk_cg | |
| - const: axi_cg | |
| - const: crypto | |
| unevaluatedProperties: false | |
| examples: | |
| - | | |
| #include <dt-bindings/interrupt-controller/irq.h> | |
| #include <dt-bindings/interrupt-controller/arm-gic.h> | |
| #include <dt-bindings/clock/mt8173-clk.h> | |
| mmc0: mmc@11230000 { | |
| compatible = "mediatek,mt8173-mmc"; | |
| reg = <0x11230000 0x1000>; | |
| interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>; | |
| vmmc-supply = <&mt6397_vemc_3v3_reg>; | |
| vqmmc-supply = <&mt6397_vio18_reg>; | |
| clocks = <&pericfg CLK_PERI_MSDC30_0>, | |
| <&topckgen CLK_TOP_MSDC50_0_H_SEL>; | |
| clock-names = "source", "hclk"; | |
| pinctrl-names = "default", "state_uhs"; | |
| pinctrl-0 = <&mmc0_pins_default>; | |
| pinctrl-1 = <&mmc0_pins_uhs>; | |
| assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>; | |
| assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; | |
| hs400-ds-delay = <0x14015>; | |
| mediatek,hs200-cmd-int-delay = <26>; | |
| mediatek,hs400-cmd-int-delay = <14>; | |
| mediatek,hs400-cmd-resp-sel-rising; | |
| }; | |
| mmc3: mmc@11260000 { | |
| compatible = "mediatek,mt8173-mmc"; | |
| reg = <0x11260000 0x1000>; | |
| clock-names = "source", "hclk"; | |
| clocks = <&pericfg CLK_PERI_MSDC30_3>, | |
| <&topckgen CLK_TOP_MSDC50_2_H_SEL>; | |
| interrupt-names = "msdc", "sdio_wakeup"; | |
| interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_LOW 0>, | |
| <&pio 23 IRQ_TYPE_LEVEL_LOW>; | |
| pinctrl-names = "default", "state_uhs", "state_eint"; | |
| pinctrl-0 = <&mmc2_pins_default>; | |
| pinctrl-1 = <&mmc2_pins_uhs>; | |
| pinctrl-2 = <&mmc2_pins_eint>; | |
| bus-width = <4>; | |
| max-frequency = <200000000>; | |
| cap-sd-highspeed; | |
| sd-uhs-sdr104; | |
| keep-power-in-suspend; | |
| wakeup-source; | |
| cap-sdio-irq; | |
| no-mmc; | |
| no-sd; | |
| non-removable; | |
| vmmc-supply = <&sdio_fixed_3v3>; | |
| vqmmc-supply = <&mt6397_vgp3_reg>; | |
| mmc-pwrseq = <&wifi_pwrseq>; | |
| }; | |
| ... |