Documentation/devicetree/bindings/memory-controllers/xlnx,versal-net-ddrmc5.yaml

# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/xlnx,versal-net-ddrmc5.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Xilinx Versal NET Memory Controller

maintainers:
  - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>

description:
  The integrated DDR Memory Controllers (DDRMCs) support both DDR5 and LPDDR5
  compact and extended  memory interfaces. Versal NET DDR memory controller
  has an optional ECC support which correct single bit ECC errors and detect
  double bit ECC errors. It also has support for reporting other errors like
  MMCM (Mixed-Mode Clock Manager) errors and General software errors.

properties:
  compatible:
    const: xlnx,versal-net-ddrmc5

  amd,rproc:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      phandle to the remoteproc_r5 rproc node using which APU interacts
      with remote processor. APU primarily communicates with the RPU for
      accessing the DDRMC address space and getting error notification.

required:
  - compatible
  - amd,rproc

additionalProperties: false

examples:
  - |
    memory-controller {
        compatible = "xlnx,versal-net-ddrmc5";
        amd,rproc = <&remoteproc_r5>;
    };