| # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) | |
| %YAML 1.2 | |
| --- | |
| $id: http://devicetree.org/schemas/dsp/fsl,dsp.yaml# | |
| $schema: http://devicetree.org/meta-schemas/core.yaml# | |
| title: NXP i.MX8 DSP core | |
| maintainers: | |
| - Daniel Baluta <daniel.baluta@nxp.com> | |
| - Shengjiu Wang <shengjiu.wang@nxp.com> | |
| description: | | |
| Some boards from i.MX8 family contain a DSP core used for | |
| advanced pre- and post- audio processing. | |
| properties: | |
| compatible: | |
| enum: | |
| - fsl,imx8qxp-dsp | |
| - fsl,imx8qm-dsp | |
| - fsl,imx8mp-dsp | |
| - fsl,imx8ulp-dsp | |
| - fsl,imx8qxp-hifi4 | |
| - fsl,imx8qm-hifi4 | |
| - fsl,imx8mp-hifi4 | |
| - fsl,imx8ulp-hifi4 | |
| reg: | |
| maxItems: 1 | |
| clocks: | |
| items: | |
| - description: ipg clock | |
| - description: ocram clock | |
| - description: core clock | |
| - description: debug interface clock | |
| - description: message unit clock | |
| minItems: 3 | |
| clock-names: | |
| items: | |
| - const: ipg | |
| - const: ocram | |
| - const: core | |
| - const: debug | |
| - const: mu | |
| minItems: 3 | |
| power-domains: | |
| description: | |
| List of phandle and PM domain specifier as documented in | |
| Documentation/devicetree/bindings/power/power_domain.txt | |
| minItems: 1 | |
| maxItems: 4 | |
| mboxes: | |
| description: | |
| List of <&phandle type channel> - 2 channels for TXDB, 2 channels for RXDB | |
| or - 1 channel for TX, 1 channel for RX, 1 channel for RXDB | |
| (see mailbox/fsl,mu.txt) | |
| minItems: 3 | |
| maxItems: 4 | |
| mbox-names: | |
| minItems: 3 | |
| maxItems: 4 | |
| memory-region: | |
| description: | |
| phandle to a node describing reserved memory (System RAM memory) | |
| used by DSP (see bindings/reserved-memory/reserved-memory.txt) | |
| minItems: 1 | |
| maxItems: 4 | |
| firmware-name: | |
| description: | | |
| Default name of the firmware to load to the remote processor. | |
| fsl,dsp-ctrl: | |
| $ref: /schemas/types.yaml#/definitions/phandle | |
| description: | |
| Phandle to syscon block which provide access for processor enablement | |
| resets: | |
| minItems: 1 | |
| reset-names: | |
| minItems: 1 | |
| items: | |
| - const: runstall | |
| - const: softreset | |
| access-controllers: | |
| maxItems: 1 | |
| required: | |
| - compatible | |
| - reg | |
| - clocks | |
| - clock-names | |
| - power-domains | |
| - mboxes | |
| - mbox-names | |
| - memory-region | |
| allOf: | |
| - if: | |
| properties: | |
| compatible: | |
| contains: | |
| enum: | |
| - fsl,imx8qxp-dsp | |
| - fsl,imx8qxp-hifi4 | |
| then: | |
| properties: | |
| power-domains: | |
| minItems: 2 | |
| maxItems: 2 | |
| - if: | |
| properties: | |
| compatible: | |
| contains: | |
| enum: | |
| - fsl,imx8qm-dsp | |
| - fsl,imx8qm-hifi4 | |
| then: | |
| properties: | |
| power-domains: | |
| minItems: 4 | |
| - if: | |
| properties: | |
| compatible: | |
| contains: | |
| enum: | |
| - fsl,imx8mp-dsp | |
| - fsl,imx8mp-hifi4 | |
| - fsl,imx8ulp-dsp | |
| - fsl,imx8ulp-hifi4 | |
| then: | |
| properties: | |
| power-domains: | |
| maxItems: 1 | |
| - if: | |
| properties: | |
| compatible: | |
| contains: | |
| enum: | |
| - fsl,imx8qxp-hifi4 | |
| - fsl,imx8qm-hifi4 | |
| - fsl,imx8mp-hifi4 | |
| - fsl,imx8ulp-hifi4 | |
| then: | |
| properties: | |
| memory-region: | |
| minItems: 4 | |
| mboxes: | |
| maxItems: 3 | |
| mbox-names: | |
| items: | |
| - const: tx | |
| - const: rx | |
| - const: rxdb | |
| else: | |
| properties: | |
| memory-region: | |
| maxItems: 1 | |
| mboxes: | |
| minItems: 4 | |
| mbox-names: | |
| items: | |
| - const: txdb0 | |
| - const: txdb1 | |
| - const: rxdb0 | |
| - const: rxdb1 | |
| - if: | |
| properties: | |
| compatible: | |
| contains: | |
| enum: | |
| - fsl,imx8mp-dsp | |
| - fsl,imx8mp-hifi4 | |
| then: | |
| required: | |
| - resets | |
| - reset-names | |
| additionalProperties: false | |
| examples: | |
| - | | |
| #include <dt-bindings/firmware/imx/rsrc.h> | |
| #include <dt-bindings/clock/imx8-clock.h> | |
| dsp@596e8000 { | |
| compatible = "fsl,imx8qxp-dsp"; | |
| reg = <0x596e8000 0x88000>; | |
| clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>, | |
| <&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>, | |
| <&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>; | |
| clock-names = "ipg", "ocram", "core"; | |
| power-domains = <&pd IMX_SC_R_MU_13B>, | |
| <&pd IMX_SC_R_MU_2A>; | |
| mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1"; | |
| mboxes = <&lsio_mu13 2 0>, <&lsio_mu13 2 1>, <&lsio_mu13 3 0>, <&lsio_mu13 3 1>; | |
| memory-region = <&dsp_reserved>; | |
| }; | |
| - | | |
| #include <dt-bindings/clock/imx8mp-clock.h> | |
| #include <dt-bindings/reset/imx8mp-reset-audiomix.h> | |
| dsp_reserved: dsp@92400000 { | |
| reg = <0x92400000 0x1000000>; | |
| no-map; | |
| }; | |
| dsp_vdev0vring0: vdev0vring0@942f0000 { | |
| reg = <0x942f0000 0x8000>; | |
| no-map; | |
| }; | |
| dsp_vdev0vring1: vdev0vring1@942f8000 { | |
| reg = <0x942f8000 0x8000>; | |
| no-map; | |
| }; | |
| dsp_vdev0buffer: vdev0buffer@94300000 { | |
| compatible = "shared-dma-pool"; | |
| reg = <0x94300000 0x100000>; | |
| no-map; | |
| }; | |
| dsp: dsp@3b6e8000 { | |
| compatible = "fsl,imx8mp-hifi4"; | |
| reg = <0x3b6e8000 0x88000>; | |
| clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSP_ROOT>, | |
| <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_OCRAMA_IPG>, | |
| <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSP_ROOT>, | |
| <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSPDBG_ROOT>; | |
| clock-names = "ipg", "ocram", "core", "debug"; | |
| firmware-name = "imx/dsp/hifi4.bin"; | |
| power-domains = <&audiomix_pd>; | |
| mbox-names = "tx", "rx", "rxdb"; | |
| mboxes = <&mu2 0 0>, | |
| <&mu2 1 0>, | |
| <&mu2 3 0>; | |
| memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>, | |
| <&dsp_vdev0vring1>, <&dsp_reserved>; | |
| resets = <&audio_blk_ctrl IMX8MP_AUDIOMIX_DSP_RUNSTALL>; | |
| reset-names = "runstall"; | |
| }; |