| # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/display/msm/qcom,sm8750-mdss.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: Qualcomm SM8750 Display MDSS |
| |
| maintainers: |
| - Krzysztof Kozlowski <krzk@kernel.org> |
| |
| description: |
| SM8750 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like |
| DPU display controller, DSI and DP interfaces etc. |
| |
| $ref: /schemas/display/msm/mdss-common.yaml# |
| |
| properties: |
| compatible: |
| const: qcom,sm8750-mdss |
| |
| clocks: |
| items: |
| - description: Display AHB |
| - description: Display hf AXI |
| - description: Display core |
| |
| iommus: |
| maxItems: 1 |
| |
| interconnects: |
| items: |
| - description: Interconnect path from mdp0 port to the data bus |
| - description: Interconnect path from CPU to the reg bus |
| |
| interconnect-names: |
| items: |
| - const: mdp0-mem |
| - const: cpu-cfg |
| |
| patternProperties: |
| "^display-controller@[0-9a-f]+$": |
| type: object |
| additionalProperties: true |
| properties: |
| compatible: |
| const: qcom,sm8750-dpu |
| |
| "^displayport-controller@[0-9a-f]+$": |
| type: object |
| additionalProperties: true |
| properties: |
| compatible: |
| contains: |
| const: qcom,sm8750-dp |
| |
| "^dsi@[0-9a-f]+$": |
| type: object |
| additionalProperties: true |
| properties: |
| compatible: |
| contains: |
| const: qcom,sm8750-dsi-ctrl |
| |
| "^phy@[0-9a-f]+$": |
| type: object |
| additionalProperties: true |
| properties: |
| compatible: |
| const: qcom,sm8750-dsi-phy-3nm |
| |
| required: |
| - compatible |
| |
| unevaluatedProperties: false |
| |
| examples: |
| - | |
| #include <dt-bindings/clock/qcom,rpmh.h> |
| #include <dt-bindings/interconnect/qcom,icc.h> |
| #include <dt-bindings/interconnect/qcom,sm8750-rpmh.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/phy/phy-qcom-qmp.h> |
| #include <dt-bindings/power/qcom,rpmhpd.h> |
| |
| display-subsystem@ae00000 { |
| compatible = "qcom,sm8750-mdss"; |
| reg = <0x0ae00000 0x1000>; |
| reg-names = "mdss"; |
| |
| interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&disp_cc_mdss_ahb_clk>, |
| <&gcc_disp_hf_axi_clk>, |
| <&disp_cc_mdss_mdp_clk>; |
| |
| interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS |
| &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, |
| <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY |
| &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; |
| interconnect-names = "mdp0-mem", |
| "cpu-cfg"; |
| |
| resets = <&disp_cc_mdss_core_bcr>; |
| |
| power-domains = <&mdss_gdsc>; |
| |
| iommus = <&apps_smmu 0x800 0x2>; |
| |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| display-controller@ae01000 { |
| compatible = "qcom,sm8750-dpu"; |
| reg = <0x0ae01000 0x93000>, |
| <0x0aeb0000 0x2008>; |
| reg-names = "mdp", |
| "vbif"; |
| |
| interrupts-extended = <&mdss 0>; |
| |
| clocks = <&gcc_disp_hf_axi_clk>, |
| <&disp_cc_mdss_ahb_clk>, |
| <&disp_cc_mdss_mdp_lut_clk>, |
| <&disp_cc_mdss_mdp_clk>, |
| <&disp_cc_mdss_vsync_clk>; |
| clock-names = "nrt_bus", |
| "iface", |
| "lut", |
| "core", |
| "vsync"; |
| |
| assigned-clocks = <&disp_cc_mdss_vsync_clk>; |
| assigned-clock-rates = <19200000>; |
| |
| operating-points-v2 = <&mdp_opp_table>; |
| |
| power-domains = <&rpmhpd RPMHPD_MMCX>; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| |
| dpu_intf1_out: endpoint { |
| remote-endpoint = <&mdss_dsi0_in>; |
| }; |
| }; |
| |
| port@1 { |
| reg = <1>; |
| |
| dpu_intf2_out: endpoint { |
| remote-endpoint = <&mdss_dsi1_in>; |
| }; |
| }; |
| |
| port@2 { |
| reg = <2>; |
| |
| dpu_intf0_out: endpoint { |
| remote-endpoint = <&mdss_dp0_in>; |
| }; |
| }; |
| }; |
| |
| mdp_opp_table: opp-table { |
| compatible = "operating-points-v2"; |
| |
| opp-207000000 { |
| opp-hz = /bits/ 64 <207000000>; |
| required-opps = <&rpmhpd_opp_low_svs>; |
| }; |
| |
| opp-337000000 { |
| opp-hz = /bits/ 64 <337000000>; |
| required-opps = <&rpmhpd_opp_svs>; |
| }; |
| |
| opp-417000000 { |
| opp-hz = /bits/ 64 <417000000>; |
| required-opps = <&rpmhpd_opp_svs_l1>; |
| }; |
| |
| opp-532000000 { |
| opp-hz = /bits/ 64 <532000000>; |
| required-opps = <&rpmhpd_opp_nom>; |
| }; |
| |
| opp-575000000 { |
| opp-hz = /bits/ 64 <575000000>; |
| required-opps = <&rpmhpd_opp_nom_l1>; |
| }; |
| }; |
| }; |
| |
| dsi@ae94000 { |
| compatible = "qcom,sm8750-dsi-ctrl", "qcom,mdss-dsi-ctrl"; |
| reg = <0x0ae94000 0x400>; |
| reg-names = "dsi_ctrl"; |
| |
| interrupts-extended = <&mdss 4>; |
| |
| clocks = <&disp_cc_mdss_byte0_clk>, |
| <&disp_cc_mdss_byte0_intf_clk>, |
| <&disp_cc_mdss_pclk0_clk>, |
| <&disp_cc_mdss_esc0_clk>, |
| <&disp_cc_mdss_ahb_clk>, |
| <&gcc_disp_hf_axi_clk>, |
| <&mdss_dsi0_phy 1>, |
| <&mdss_dsi0_phy 0>, |
| <&disp_cc_esync0_clk>, |
| <&disp_cc_osc_clk>, |
| <&disp_cc_mdss_byte0_clk_src>, |
| <&disp_cc_mdss_pclk0_clk_src>; |
| clock-names = "byte", |
| "byte_intf", |
| "pixel", |
| "core", |
| "iface", |
| "bus", |
| "dsi_pll_pixel", |
| "dsi_pll_byte", |
| "esync", |
| "osc", |
| "byte_src", |
| "pixel_src"; |
| |
| operating-points-v2 = <&mdss_dsi_opp_table>; |
| |
| power-domains = <&rpmhpd RPMHPD_MMCX>; |
| |
| phys = <&mdss_dsi0_phy>; |
| phy-names = "dsi"; |
| |
| vdda-supply = <&vreg_l3g_1p2>; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| |
| mdss_dsi0_in: endpoint { |
| remote-endpoint = <&dpu_intf1_out>; |
| }; |
| }; |
| |
| port@1 { |
| reg = <1>; |
| |
| mdss_dsi0_out: endpoint { |
| remote-endpoint = <&panel0_in>; |
| data-lanes = <0 1 2 3>; |
| }; |
| }; |
| }; |
| |
| mdss_dsi_opp_table: opp-table { |
| compatible = "operating-points-v2"; |
| |
| opp-187500000 { |
| opp-hz = /bits/ 64 <187500000>; |
| required-opps = <&rpmhpd_opp_low_svs>; |
| }; |
| |
| opp-300000000 { |
| opp-hz = /bits/ 64 <300000000>; |
| required-opps = <&rpmhpd_opp_svs>; |
| }; |
| |
| opp-358000000 { |
| opp-hz = /bits/ 64 <358000000>; |
| required-opps = <&rpmhpd_opp_svs_l1>; |
| }; |
| }; |
| }; |
| |
| mdss_dsi0_phy: phy@ae95000 { |
| compatible = "qcom,sm8750-dsi-phy-3nm"; |
| reg = <0x0ae95000 0x200>, |
| <0x0ae95200 0x280>, |
| <0x0ae95500 0x400>; |
| reg-names = "dsi_phy", |
| "dsi_phy_lane", |
| "dsi_pll"; |
| |
| clocks = <&disp_cc_mdss_ahb_clk>, |
| <&rpmhcc RPMH_CXO_CLK>; |
| clock-names = "iface", |
| "ref"; |
| |
| vdds-supply = <&vreg_l3i_0p88>; |
| |
| #clock-cells = <1>; |
| #phy-cells = <0>; |
| }; |
| |
| dsi@ae96000 { |
| compatible = "qcom,sm8750-dsi-ctrl", "qcom,mdss-dsi-ctrl"; |
| reg = <0x0ae96000 0x400>; |
| reg-names = "dsi_ctrl"; |
| |
| interrupts-extended = <&mdss 5>; |
| |
| clocks = <&disp_cc_mdss_byte1_clk>, |
| <&disp_cc_mdss_byte1_intf_clk>, |
| <&disp_cc_mdss_pclk1_clk>, |
| <&disp_cc_mdss_esc1_clk>, |
| <&disp_cc_mdss_ahb_clk>, |
| <&gcc_disp_hf_axi_clk>, |
| <&mdss_dsi1_phy 1>, |
| <&mdss_dsi1_phy 0>, |
| <&disp_cc_esync1_clk>, |
| <&disp_cc_osc_clk>, |
| <&disp_cc_mdss_byte1_clk_src>, |
| <&disp_cc_mdss_pclk1_clk_src>; |
| clock-names = "byte", |
| "byte_intf", |
| "pixel", |
| "core", |
| "iface", |
| "bus", |
| "dsi_pll_pixel", |
| "dsi_pll_byte", |
| "esync", |
| "osc", |
| "byte_src", |
| "pixel_src"; |
| |
| operating-points-v2 = <&mdss_dsi_opp_table>; |
| |
| power-domains = <&rpmhpd RPMHPD_MMCX>; |
| |
| phys = <&mdss_dsi1_phy>; |
| phy-names = "dsi"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| |
| mdss_dsi1_in: endpoint { |
| remote-endpoint = <&dpu_intf2_out>; |
| }; |
| }; |
| |
| port@1 { |
| reg = <1>; |
| |
| mdss_dsi1_out: endpoint { |
| }; |
| }; |
| }; |
| }; |
| |
| mdss_dsi1_phy: phy@ae97000 { |
| compatible = "qcom,sm8750-dsi-phy-3nm"; |
| reg = <0x0ae97000 0x200>, |
| <0x0ae97200 0x280>, |
| <0x0ae97500 0x400>; |
| reg-names = "dsi_phy", |
| "dsi_phy_lane", |
| "dsi_pll"; |
| |
| clocks = <&disp_cc_mdss_ahb_clk>, |
| <&rpmhcc RPMH_CXO_CLK>; |
| clock-names = "iface", |
| "ref"; |
| |
| #clock-cells = <1>; |
| #phy-cells = <0>; |
| }; |
| |
| displayport-controller@af54000 { |
| compatible = "qcom,sm8750-dp", "qcom,sm8650-dp"; |
| reg = <0xaf54000 0x104>, |
| <0xaf54200 0xc0>, |
| <0xaf55000 0x770>, |
| <0xaf56000 0x9c>, |
| <0xaf57000 0x9c>; |
| |
| interrupts-extended = <&mdss 12>; |
| |
| clocks = <&disp_cc_mdss_ahb_clk>, |
| <&disp_cc_mdss_dptx0_aux_clk>, |
| <&disp_cc_mdss_dptx0_link_clk>, |
| <&disp_cc_mdss_dptx0_link_intf_clk>, |
| <&disp_cc_mdss_dptx0_pixel0_clk>, |
| <&disp_cc_mdss_dptx0_pixel1_clk>; |
| clock-names = "core_iface", |
| "core_aux", |
| "ctrl_link", |
| "ctrl_link_iface", |
| "stream_pixel", |
| "stream_1_pixel"; |
| |
| assigned-clocks = <&disp_cc_mdss_dptx0_link_clk_src>, |
| <&disp_cc_mdss_dptx0_pixel0_clk_src>, |
| <&disp_cc_mdss_dptx0_pixel1_clk_src>; |
| assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, |
| <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, |
| <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; |
| |
| operating-points-v2 = <&dp_opp_table>; |
| |
| power-domains = <&rpmhpd RPMHPD_MMCX>; |
| |
| phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; |
| phy-names = "dp"; |
| |
| #sound-dai-cells = <0>; |
| |
| dp_opp_table: opp-table { |
| compatible = "operating-points-v2"; |
| |
| opp-192000000 { |
| opp-hz = /bits/ 64 <192000000>; |
| required-opps = <&rpmhpd_opp_low_svs_d1>; |
| }; |
| |
| opp-270000000 { |
| opp-hz = /bits/ 64 <270000000>; |
| required-opps = <&rpmhpd_opp_low_svs>; |
| }; |
| |
| opp-540000000 { |
| opp-hz = /bits/ 64 <540000000>; |
| required-opps = <&rpmhpd_opp_svs_l1>; |
| }; |
| |
| opp-810000000 { |
| opp-hz = /bits/ 64 <810000000>; |
| required-opps = <&rpmhpd_opp_nom>; |
| }; |
| }; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| |
| mdss_dp0_in: endpoint { |
| remote-endpoint = <&dpu_intf0_out>; |
| }; |
| }; |
| |
| port@1 { |
| reg = <1>; |
| |
| mdss_dp0_out: endpoint { |
| remote-endpoint = <&usb_dp_qmpphy_dp_in>; |
| }; |
| }; |
| }; |
| }; |
| }; |
