Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,x1e80100-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Global Clock & Reset Controller on X1E80100

maintainers:
  - Rajendra Nayak <quic_rjendra@quicinc.com>

description: |
  Qualcomm global clock control module provides the clocks, resets and power
  domains on X1E80100

  See also: include/dt-bindings/clock/qcom,x1e80100-gcc.h

properties:
  compatible:
    oneOf:
      - items:
          - const: qcom,x1p42100-gcc
          - const: qcom,x1e80100-gcc
      - const: qcom,x1e80100-gcc

  clocks:
    items:
      - description: Board XO source
      - description: Sleep clock source
      - description: PCIe 3 pipe clock
      - description: PCIe 4 pipe clock
      - description: PCIe 5 pipe clock
      - description: PCIe 6a pipe clock
      - description: PCIe 6b pipe clock
      - description: USB4_0 QMPPHY clock source
      - description: USB4_1 QMPPHY clock source
      - description: USB4_2 QMPPHY clock source
      - description: USB4_0 PHY DP0 GMUX clock source
      - description: USB4_0 PHY DP1 GMUX clock source
      - description: USB4_0 PHY PCIE PIPEGMUX clock source
      - description: USB4_0 PHY PIPEGMUX clock source
      - description: USB4_0 PHY SYS PCIE PIPEGMUX clock source
      - description: USB4_1 PHY DP0 GMUX 2 clock source
      - description: USB4_1 PHY DP1 GMUX 2 clock source
      - description: USB4_1 PHY PCIE PIPEGMUX clock source
      - description: USB4_1 PHY PIPEGMUX clock source
      - description: USB4_1 PHY SYS PCIE PIPEGMUX clock source
      - description: USB4_2 PHY DP0 GMUX 2 clock source
      - description: USB4_2 PHY DP1 GMUX 2 clock source
      - description: USB4_2 PHY PCIE PIPEGMUX clock source
      - description: USB4_2 PHY PIPEGMUX clock source
      - description: USB4_2 PHY SYS PCIE PIPEGMUX clock source
      - description: USB4_0 PHY RX 0 clock source
      - description: USB4_0 PHY RX 1 clock source
      - description: USB4_1 PHY RX 0 clock source
      - description: USB4_1 PHY RX 1 clock source
      - description: USB4_2 PHY RX 0 clock source
      - description: USB4_2 PHY RX 1 clock source
      - description: USB4_0 PHY PCIE PIPE clock source
      - description: USB4_0 PHY max PIPE clock source
      - description: USB4_1 PHY PCIE PIPE clock source
      - description: USB4_1 PHY max PIPE clock source
      - description: USB4_2 PHY PCIE PIPE clock source
      - description: USB4_2 PHY max PIPE clock source
      - description: UFS PHY RX Symbol 0 clock source
      - description: UFS PHY RX Symbol 1 clock source
      - description: UFS PHY TX Symbol 0 clock source

  power-domains:
    description:
      A phandle and PM domain specifier for the CX power domain.
    maxItems: 1

required:
  - compatible
  - clocks
  - power-domains
  - '#power-domain-cells'

allOf:
  - $ref: qcom,gcc.yaml#

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/power/qcom,rpmhpd.h>
    clock-controller@100000 {
      compatible = "qcom,x1e80100-gcc";
      reg = <0x00100000 0x200000>;
      clocks = <&bi_tcxo_div2>,
               <&sleep_clk>,
               <&pcie3_phy>,
               <&pcie4_phy>,
               <&pcie5_phy>,
               <&pcie6a_phy>,
               <&pcie6b_phy>,
               <&usb_1_ss0_qmpphy 0>,
               <&usb_1_ss1_qmpphy 1>,
               <&usb_1_ss2_qmpphy 2>,
               <&usb4_0_phy_dp0_gmux_clk>,
               <&usb4_0_phy_dp1_gmux_clk>,
               <&usb4_0_phy_pcie_pipegmux_clk>,
               <&usb4_0_phy_pipegmux_clk>,
               <&usb4_0_phy_sys_pcie_pipegmux_clk>,
               <&usb4_1_phy_dp0_gmux_2_clk>,
               <&usb4_1_phy_dp1_gmux_2_clk>,
               <&usb4_1_phy_pcie_pipegmux_clk>,
               <&usb4_1_phy_pipegmux_clk>,
               <&usb4_1_phy_sys_pcie_pipegmux_clk>,
               <&usb4_2_phy_dp0_gmux_2_clk>,
               <&usb4_2_phy_dp1_gmux_2_clk>,
               <&usb4_2_phy_pcie_pipegmux_clk>,
               <&usb4_2_phy_pipegmux_clk>,
               <&usb4_2_phy_sys_pcie_pipegmux_clk>,
               <&usb4_0_phy_rx_0_clk>,
               <&usb4_0_phy_rx_1_clk>,
               <&usb4_1_phy_rx_0_clk>,
               <&usb4_1_phy_rx_1_clk>,
               <&usb4_2_phy_rx_0_clk>,
               <&usb4_2_phy_rx_1_clk>,
               <&usb4_0_phy_pcie_pipe_clk>,
               <&usb4_0_phy_max_pipe_clk>,
               <&usb4_1_phy_pcie_pipe_clk>,
               <&usb4_1_phy_max_pipe_clk>,
               <&usb4_2_phy_pcie_pipe_clk>,
               <&usb4_2_phy_max_pipe_clk>,
               <&ufs_phy_rx_symbol_0>,
               <&ufs_phy_rx_symbol_1>,
               <&ufs_phy_tx_symbol_0>;
      power-domains = <&rpmhpd RPMHPD_CX>;
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
    };

...