Documentation/devicetree/bindings/clock/qcom,qcs615-dispcc.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,qcs615-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Display Clock & Reset Controller on QCS615

maintainers:
  - Taniya Das <quic_tdas@quicinc.com>

description: |
  Qualcomm display clock control module provides the clocks, resets and power
  domains on QCS615.

  See also: include/dt-bindings/clock/qcom,qcs615-dispcc.h

properties:
  compatible:
    const: qcom,qcs615-dispcc

  clocks:
    items:
      - description: Board XO source
      - description: GPLL0 clock source from GCC
      - description: Byte clock from DSI PHY0
      - description: Pixel clock from DSI PHY0
      - description: Pixel clock from DSI PHY1
      - description: Display port PLL link clock
      - description: Display port PLL VCO DIV clock

allOf:
  - $ref: qcom,gcc.yaml#

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,rpmh.h>
    #include <dt-bindings/clock/qcom,qcs615-gcc.h>
    clock-controller@af00000 {
      compatible = "qcom,qcs615-dispcc";
      reg = <0x0af00000 0x20000>;
      clocks = <&rpmhcc RPMH_CXO_CLK>,
               <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
               <&mdss_dsi0_phy 0>,
               <&mdss_dsi0_phy 1>,
               <&mdss_dsi1_phy 0>,
               <&mdss_dp_phy 0>,
               <&mdss_dp_vco 0>;
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
    };
...