Documentation/devicetree/bindings/clock/img,pistachio-clk.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/img,pistachio-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Imagination Technologies Pistachio SoC clock controllers

maintainers:
  - Andrew Bresticker <abrestic@chromium.org>

description: |
  Pistachio has four clock controllers (core clock, peripheral clock, peripheral
  general control, and top general control) which are instantiated individually
  from the device-tree.

  Core clock controller:

  The core clock controller generates clocks for the CPU, RPU (WiFi + BT
  co-processor), audio, and several peripherals.

  Peripheral clock controller:

  The peripheral clock controller generates clocks for the DDR, ROM, and other
  peripherals. The peripheral system clock ("periph_sys") generated by the core
  clock controller is the input clock to the peripheral clock controller.

  Peripheral general control:

  The peripheral general control block generates system interface clocks and
  resets for various peripherals. It also contains miscellaneous peripheral
  control registers.

  Top-level general control:

  The top-level general control block contains miscellaneous control registers
  and gates for the external clocks "audio_clk_in" and "enet_clk_in".

properties:
  compatible:
    items:
      - enum:
          - img,pistachio-clk
          - img,pistachio-clk-periph
          - img,pistachio-cr-periph
          - img,pistachio-cr-top

  reg:
    maxItems: 1

  '#clock-cells':
    const: 1

  clocks:
    minItems: 1
    maxItems: 3

  clock-names:
    minItems: 1
    maxItems: 3

required:
  - compatible
  - reg
  - '#clock-cells'
  - clocks
  - clock-names

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: img,pistachio-clk
    then:
      properties:
        clocks:
          items:
            - description: External 52Mhz oscillator
            - description: Alternate audio reference clock
            - description: Alternate ethernet PHY clock

        clock-names:
          items:
            - const: xtal
            - const: audio_refclk_ext_gate
            - const: ext_enet_in_gate

  - if:
      properties:
        compatible:
          contains:
            const: img,pistachio-clk-periph
    then:
      properties:
        clocks:
          items:
            - description: Peripheral system clock

        clock-names:
          items:
            - const: periph_sys_core

  - if:
      properties:
        compatible:
          contains:
            const: img,pistachio-cr-periph
    then:
      properties:
        clocks:
          items:
            - description: System interface clock

        clock-names:
          items:
            - const: sys

  - if:
      properties:
        compatible:
          contains:
            const: img,pistachio-cr-top
    then:
      properties:
        clocks:
          items:
            - description: External audio reference clock
            - description: External ethernet PHY clock

        clock-names:
          items:
            - const: audio_clk_in
            - const: enet_clk_in

additionalProperties: false