| // SPDX-License-Identifier: GPL-2.0-only OR MIT |
| /* |
| * Copyright (C) 2025 PHYTEC America LLC |
| * Author: Garrett Giordano <ggiordano@phytec.com> |
| */ |
| |
| /dts-v1/; |
| /plugin/; |
| |
| #include <dt-bindings/net/ti-dp83869.h> |
| #include "k3-pinctrl.h" |
| |
| &{/} { |
| aliases { |
| ethernet3 = "/icssg1-ethernet/ethernet-ports/port@0"; |
| ethernet4 = "/icssg1-ethernet/ethernet-ports/port@1"; |
| }; |
| |
| icssg1-ethernet { |
| compatible = "ti,am642-icssg-prueth"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&icssg1_rgmii1_pins_default>, <&icssg1_rgmii2_pins_default>; |
| |
| dmas = <&main_pktdma 0xc200 15>, /* egress slice 0 */ |
| <&main_pktdma 0xc201 15>, /* egress slice 0 */ |
| <&main_pktdma 0xc202 15>, /* egress slice 0 */ |
| <&main_pktdma 0xc203 15>, /* egress slice 0 */ |
| <&main_pktdma 0xc204 15>, /* egress slice 1 */ |
| <&main_pktdma 0xc205 15>, /* egress slice 1 */ |
| <&main_pktdma 0xc206 15>, /* egress slice 1 */ |
| <&main_pktdma 0xc207 15>, /* egress slice 1 */ |
| <&main_pktdma 0x4200 15>, /* ingress slice 0 */ |
| <&main_pktdma 0x4201 15>; /* ingress slice 1 */ |
| dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3", |
| "tx1-0", "tx1-1", "tx1-2", "tx1-3", |
| "rx0", "rx1"; |
| |
| firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf", |
| "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf", |
| "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf", |
| "ti-pruss/am65x-sr2-pru1-prueth-fw.elf", |
| "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf", |
| "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf"; |
| |
| interrupt-parent = <&icssg1_intc>; |
| interrupts = <24 0 2>, <25 1 3>; |
| interrupt-names = "tx_ts0", "tx_ts1"; |
| sram = <&oc_sram>; |
| |
| ti,iep = <&icssg1_iep0>, <&icssg1_iep1>; |
| ti,mii-g-rt = <&icssg1_mii_g_rt>; |
| ti,mii-rt = <&icssg1_mii_rt>; |
| ti,pa-stats = <&icssg1_pa_stats>; |
| ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>; |
| ti,pruss-gp-mux-sel = <2>, /* MII mode */ |
| <2>, |
| <2>, |
| <2>, /* MII mode */ |
| <2>, |
| <2>; |
| |
| ethernet-ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| icssg1_emac0: port@0 { |
| reg = <0>; |
| phy-handle = <&icssg1_phy1>; |
| phy-mode = "rgmii-id"; |
| /* Filled in by bootloader */ |
| local-mac-address = [00 00 00 00 00 00]; |
| ti,syscon-rgmii-delay = <&main_conf 0x4110>; |
| }; |
| |
| icssg1_emac1: port@1 { |
| reg = <1>; |
| phy-handle = <&icssg1_phy2>; |
| phy-mode = "rgmii-id"; |
| /* Filled in by bootloader */ |
| local-mac-address = [00 00 00 00 00 00]; |
| ti,syscon-rgmii-delay = <&main_conf 0x4114>; |
| }; |
| }; |
| }; |
| }; |
| |
| &main_pmx0 { |
| icssg1_mdio_pins_default: icssg1-mdio-default-pins { |
| pinctrl-single,pins = < |
| AM64X_IOPAD(0x015c, PIN_OUTPUT, 0) /* (Y6) PRG1_MDIO0_MDC */ |
| AM64X_IOPAD(0x0158, PIN_INPUT, 0) /* (AA6) PRG1_MDIO0_MDIO */ |
| >; |
| }; |
| |
| icssg1_rgmii1_pins_default: icssg1-rgmii1-default-pins { |
| pinctrl-single,pins = < |
| AM64X_IOPAD(0x00b8, PIN_INPUT, 2) /* (Y7) PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */ |
| AM64X_IOPAD(0x00bc, PIN_INPUT, 2) /* (U8) PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */ |
| AM64X_IOPAD(0x00c0, PIN_INPUT, 2) /* (W8) PRG1_PRU0_GPO2.PRG1_RGMII1_RD2 */ |
| AM64X_IOPAD(0x00c4, PIN_INPUT, 2) /* (V8) PRG1_PRU0_GPO3.PRG1_RGMII1_RD3 */ |
| AM64X_IOPAD(0x00d0, PIN_INPUT, 2) /* (AA7) PRG1_PRU0_GPO6.PRG1_RGMII1_RXC */ |
| AM64X_IOPAD(0x00c8, PIN_INPUT, 2) /* (Y8) PRG1_PRU0_GPO4.PRG1_RGMII1_RX_CTL */ |
| AM64X_IOPAD(0x00e4, PIN_OUTPUT, 2) /* (AA8) PRG1_PRU0_GPO11.PRG1_RGMII1_TD0 */ |
| AM64X_IOPAD(0x00e8, PIN_OUTPUT, 2) /* (U9) PRG1_PRU0_GPO12.PRG1_RGMII1_TD1 */ |
| AM64X_IOPAD(0x00ec, PIN_OUTPUT, 2) /* (W9) PRG1_PRU0_GPO13.PRG1_RGMII1_TD2 */ |
| AM64X_IOPAD(0x00f0, PIN_OUTPUT, 2) /* (AA9) PRG1_PRU0_GPO14.PRG1_RGMII1_TD3 */ |
| AM64X_IOPAD(0x00f4, PIN_OUTPUT, 2) /* (Y9) PRG1_PRU0_GPO15.PRG1_RGMII1_TX_CTL */ |
| AM64X_IOPAD(0x00f8, PIN_INPUT, 2) /* (V9) PRG1_PRU0_GPO16.PRG1_RGMII1_TXC */ |
| >; |
| }; |
| |
| icssg1_rgmii2_pins_default: icssg1-rgmii2-default-pins { |
| pinctrl-single,pins = < |
| AM64X_IOPAD(0x0108, PIN_INPUT, 2) /* (W11) PRG1_PRU1_GPO0.PRG1_RGMII2_RD0 */ |
| AM64X_IOPAD(0x010c, PIN_INPUT, 2) /* (V11) PRG1_PRU1_GPO1.PRG1_RGMII2_RD1 */ |
| AM64X_IOPAD(0x0110, PIN_INPUT, 2) /* (AA12) PRG1_PRU1_GPO2.PRG1_RGMII2_RD2 */ |
| AM64X_IOPAD(0x0114, PIN_INPUT, 2) /* (Y12) PRG1_PRU1_GPO3.PRG1_RGMII2_RD3 */ |
| AM64X_IOPAD(0x0118, PIN_INPUT, 2) /* (W12) PRG1_PRU1_GPO4.PRG1_RGMII2_RX_CTL */ |
| AM64X_IOPAD(0x0120, PIN_INPUT, 2) /* (U11) PRG1_PRU1_GPO6.PRG1_RGMII2_RXC */ |
| AM64X_IOPAD(0x0134, PIN_OUTPUT, 2) /* (AA10) PRG1_PRU1_GPO11.PRG1_RGMII2_TD0 */ |
| AM64X_IOPAD(0x0138, PIN_OUTPUT, 2) /* (V10) PRG1_PRU1_GPO12.PRG1_RGMII2_TD1 */ |
| AM64X_IOPAD(0x013c, PIN_OUTPUT, 2) /* (U10) PRG1_PRU1_GPO13.PRG1_RGMII2_TD2 */ |
| AM64X_IOPAD(0x0140, PIN_OUTPUT, 2) /* (AA11) PRG1_PRU1_GPO14.PRG1_RGMII2_TD3 */ |
| AM64X_IOPAD(0x0144, PIN_OUTPUT, 2) /* (Y11) PRG1_PRU1_GPO15.PRG1_RGMII2_TX_CTL */ |
| AM64X_IOPAD(0x0148, PIN_INPUT, 2) /* (Y10) PRG1_PRU1_GPO16.PRG1_RGMII2_TXC */ |
| >; |
| }; |
| }; |
| |
| &icssg1_mdio { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&icssg1_mdio_pins_default>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "okay"; |
| |
| icssg1_phy1: ethernet-phy@1 { |
| reg = <0x1>; |
| rx-fifo-depth = <DP83869_PHYCR_FIFO_DEPTH_4_B_NIB>; |
| tx-fifo-depth = <DP83869_PHYCR_FIFO_DEPTH_4_B_NIB>; |
| rx-internal-delay-ps = <2000>; |
| tx-internal-delay-ps = <2000>; |
| ti,clk-output-sel = <DP83869_CLK_O_SEL_REF_CLK>; |
| ti,min-output-impedance; |
| }; |
| |
| icssg1_phy2: ethernet-phy@2 { |
| reg = <0x2>; |
| rx-fifo-depth = <DP83869_PHYCR_FIFO_DEPTH_4_B_NIB>; |
| tx-fifo-depth = <DP83869_PHYCR_FIFO_DEPTH_4_B_NIB>; |
| rx-internal-delay-ps = <2000>; |
| tx-internal-delay-ps = <2000>; |
| ti,clk-output-sel = <DP83869_CLK_O_SEL_REF_CLK>; |
| ti,min-output-impedance; |
| }; |
| }; |
