arch/arm64/boot/dts/ti/k3-am62a-ti-ipc-firmware.dtsi

// SPDX-License-Identifier: GPL-2.0-only OR MIT
/**
 * Device Tree Source for enabling IPC using TI SDK firmware on AM62A SoCs
 *
 * Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/
 */

&reserved_memory {
	c7x_0_dma_memory_region: memory@99800000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0x99800000 0x00 0x100000>;
		no-map;
	};

	c7x_0_memory_region: memory@99900000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0x99900000 0x00 0xf00000>;
		no-map;
	};

	mcu_r5fss0_core0_dma_memory_region: memory@9b800000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0x9b800000 0x00 0x100000>;
		no-map;
	};

	mcu_r5fss0_core0_memory_region: memory@9b900000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0x9b900000 0x00 0xf00000>;
		no-map;
	};
};

&mailbox0_cluster0 {
	status = "okay";

	mbox_r5_0: mbox-r5-0 {
		ti,mbox-rx = <0 0 0>;
		ti,mbox-tx = <1 0 0>;
	};
};

&mailbox0_cluster1 {
	status = "okay";

	mbox_c7x_0: mbox-c7x-0 {
		ti,mbox-rx = <0 0 0>;
		ti,mbox-tx = <1 0 0>;
	};
};

&mailbox0_cluster2 {
	status = "okay";

	mbox_mcu_r5_0: mbox-mcu-r5-0 {
		ti,mbox-rx = <0 0 0>;
		ti,mbox-tx = <1 0 0>;
	};
};

&wkup_r5fss0 {
	status = "okay";
};

&wkup_r5fss0_core0 {
	mboxes = <&mailbox0_cluster0>, <&mbox_r5_0>;
	memory-region = <&wkup_r5fss0_core0_dma_memory_region>,
			<&wkup_r5fss0_core0_memory_region>;
	status = "okay";
};

&mcu_r5fss0 {
	status = "okay";
};

&mcu_r5fss0_core0 {
	mboxes = <&mailbox0_cluster2>, <&mbox_mcu_r5_0>;
	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
			<&mcu_r5fss0_core0_memory_region>;
	status = "okay";
};

&c7x_0 {
	mboxes = <&mailbox0_cluster1>, <&mbox_c7x_0>;
	memory-region = <&c7x_0_dma_memory_region>,
			<&c7x_0_memory_region>;
	status = "okay";
};

/* main_rti4 is used by C7x DSP */
&main_rti4 {
	status = "reserved";
};

/* main_timer2 is used by C7x DSP */
&main_timer2 {
	status = "reserved";
};