| // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| /* |
| * Copyright (c) 2023 Rockchip Electronics Co., Ltd. |
| */ |
| |
| #include <dt-bindings/pinctrl/rockchip.h> |
| #include "rockchip-pinconf.dtsi" |
| |
| /* |
| * This file is auto generated by pin2dts tool, please keep these code |
| * by adding changes at end of this file. |
| */ |
| &pinctrl { |
| aupll_clk { |
| /omit-if-no-ref/ |
| aupll_clkm0_pins: aupll_clkm0-pins { |
| rockchip,pins = |
| /* aupll_clk_in_m0 */ |
| <0 RK_PA0 3 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| aupll_clkm1_pins: aupll_clkm1-pins { |
| rockchip,pins = |
| /* aupll_clk_in_m1 */ |
| <0 RK_PB0 3 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| aupll_clkm2_pins: aupll_clkm2-pins { |
| rockchip,pins = |
| /* aupll_clk_in_m2 */ |
| <4 RK_PA2 3 &pcfg_pull_none>; |
| }; |
| }; |
| |
| cam_clk0 { |
| /omit-if-no-ref/ |
| cam_clk0m0_clk0: cam_clk0m0-clk0 { |
| rockchip,pins = |
| /* cam_clk0_out_m0 */ |
| <3 RK_PD7 3 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| cam_clk0m1_clk0: cam_clk0m1-clk0 { |
| rockchip,pins = |
| /* cam_clk0_out_m1 */ |
| <2 RK_PD2 1 &pcfg_pull_none>; |
| }; |
| }; |
| |
| cam_clk1 { |
| /omit-if-no-ref/ |
| cam_clk1m0_clk1: cam_clk1m0-clk1 { |
| rockchip,pins = |
| /* cam_clk1_out_m0 */ |
| <4 RK_PA0 3 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| cam_clk1m1_clk1: cam_clk1m1-clk1 { |
| rockchip,pins = |
| /* cam_clk1_out_m1 */ |
| <2 RK_PD6 1 &pcfg_pull_none>; |
| }; |
| }; |
| |
| cam_clk2 { |
| /omit-if-no-ref/ |
| cam_clk2m0_clk2: cam_clk2m0-clk2 { |
| rockchip,pins = |
| /* cam_clk2_out_m0 */ |
| <4 RK_PA1 3 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| cam_clk2m1_clk2: cam_clk2m1-clk2 { |
| rockchip,pins = |
| /* cam_clk2_out_m1 */ |
| <2 RK_PD7 1 &pcfg_pull_none>; |
| }; |
| }; |
| |
| can0 { |
| /omit-if-no-ref/ |
| can0m0_pins: can0m0-pins { |
| rockchip,pins = |
| /* can0_rx_m0 */ |
| <2 RK_PA0 13 &pcfg_pull_none>, |
| /* can0_tx_m0 */ |
| <2 RK_PA1 13 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| can0m1_pins: can0m1-pins { |
| rockchip,pins = |
| /* can0_rx_m1 */ |
| <4 RK_PC3 12 &pcfg_pull_none>, |
| /* can0_tx_m1 */ |
| <4 RK_PC2 12 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| can0m2_pins: can0m2-pins { |
| rockchip,pins = |
| /* can0_rx_m2 */ |
| <4 RK_PA6 13 &pcfg_pull_none>, |
| /* can0_tx_m2 */ |
| <4 RK_PA4 13 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| can0m3_pins: can0m3-pins { |
| rockchip,pins = |
| /* can0_rx_m3 */ |
| <3 RK_PC1 12 &pcfg_pull_none>, |
| /* can0_tx_m3 */ |
| <3 RK_PC4 12 &pcfg_pull_none>; |
| }; |
| }; |
| |
| can1 { |
| /omit-if-no-ref/ |
| can1m0_pins: can1m0-pins { |
| rockchip,pins = |
| /* can1_rx_m0 */ |
| <2 RK_PA2 13 &pcfg_pull_none>, |
| /* can1_tx_m0 */ |
| <2 RK_PA3 13 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| can1m1_pins: can1m1-pins { |
| rockchip,pins = |
| /* can1_rx_m1 */ |
| <4 RK_PC7 13 &pcfg_pull_none>, |
| /* can1_tx_m1 */ |
| <4 RK_PC6 13 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| can1m2_pins: can1m2-pins { |
| rockchip,pins = |
| /* can1_rx_m2 */ |
| <4 RK_PB4 13 &pcfg_pull_none>, |
| /* can1_tx_m2 */ |
| <4 RK_PB5 13 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| can1m3_pins: can1m3-pins { |
| rockchip,pins = |
| /* can1_rx_m3 */ |
| <3 RK_PA3 11 &pcfg_pull_none>, |
| /* can1_tx_m3 */ |
| <3 RK_PA2 11 &pcfg_pull_none>; |
| }; |
| }; |
| |
| clk0_32k { |
| /omit-if-no-ref/ |
| clk0_32k_pins: clk0_32k-pins { |
| rockchip,pins = |
| /* clk0_32k_out */ |
| <0 RK_PA2 10 &pcfg_pull_none>; |
| }; |
| }; |
| |
| clk1_32k { |
| /omit-if-no-ref/ |
| clk1_32k_pins: clk1_32k-pins { |
| rockchip,pins = |
| /* clk1_32k_out */ |
| <1 RK_PD5 13 &pcfg_pull_none>; |
| }; |
| }; |
| |
| clk_32k { |
| /omit-if-no-ref/ |
| clk_32k_pins: clk_32k-pins { |
| rockchip,pins = |
| /* clk_32k_in */ |
| <0 RK_PA2 9 &pcfg_pull_none>; |
| }; |
| }; |
| |
| cpubig { |
| /omit-if-no-ref/ |
| cpubig_pins: cpubig-pins { |
| rockchip,pins = |
| /* cpubig_avs */ |
| <0 RK_PD2 11 &pcfg_pull_none>; |
| }; |
| }; |
| |
| cpulit { |
| /omit-if-no-ref/ |
| cpulit_pins: cpulit-pins { |
| rockchip,pins = |
| /* cpulit_avs */ |
| <0 RK_PC0 11 &pcfg_pull_none>; |
| }; |
| }; |
| |
| debug0_test { |
| /omit-if-no-ref/ |
| debug0_test_pins: debug0_test-pins { |
| rockchip,pins = |
| /* debug0_test_out */ |
| <1 RK_PC4 7 &pcfg_pull_none>; |
| }; |
| }; |
| |
| debug1_test { |
| /omit-if-no-ref/ |
| debug1_test_pins: debug1_test-pins { |
| rockchip,pins = |
| /* debug1_test_out */ |
| <1 RK_PC5 7 &pcfg_pull_none>; |
| }; |
| }; |
| |
| debug2_test { |
| /omit-if-no-ref/ |
| debug2_test_pins: debug2_test-pins { |
| rockchip,pins = |
| /* debug2_test_out */ |
| <1 RK_PC6 7 &pcfg_pull_none>; |
| }; |
| }; |
| |
| debug3_test { |
| /omit-if-no-ref/ |
| debug3_test_pins: debug3_test-pins { |
| rockchip,pins = |
| /* debug3_test_out */ |
| <1 RK_PC7 7 &pcfg_pull_none>; |
| }; |
| }; |
| |
| debug4_test { |
| /omit-if-no-ref/ |
| debug4_test_pins: debug4_test-pins { |
| rockchip,pins = |
| /* debug4_test_out */ |
| <1 RK_PD0 7 &pcfg_pull_none>; |
| }; |
| }; |
| |
| debug5_test { |
| /omit-if-no-ref/ |
| debug5_test_pins: debug5_test-pins { |
| rockchip,pins = |
| /* debug5_test_out */ |
| <1 RK_PD1 7 &pcfg_pull_none>; |
| }; |
| }; |
| |
| debug6_test { |
| /omit-if-no-ref/ |
| debug6_test_pins: debug6_test-pins { |
| rockchip,pins = |
| /* debug6_test_out */ |
| <1 RK_PD2 7 &pcfg_pull_none>; |
| }; |
| }; |
| |
| debug7_test { |
| /omit-if-no-ref/ |
| debug7_test_pins: debug7_test-pins { |
| rockchip,pins = |
| /* debug7_test_out */ |
| <1 RK_PD3 7 &pcfg_pull_none>; |
| }; |
| }; |
| |
| dp { |
| /omit-if-no-ref/ |
| dpm0_pins: dpm0-pins { |
| rockchip,pins = |
| /* dp_hpdin_m0 */ |
| <4 RK_PC4 10 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| dpm1_pins: dpm1-pins { |
| rockchip,pins = |
| /* dp_hpdin_m1 */ |
| <0 RK_PC5 9 &pcfg_pull_none>; |
| }; |
| }; |
| |
| dsm_aud { |
| /omit-if-no-ref/ |
| dsm_audm0_ln: dsm_audm0-ln { |
| rockchip,pins = |
| /* dsm_aud_ln_m0 */ |
| <2 RK_PA1 3 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| dsm_audm0_lp: dsm_audm0-lp { |
| rockchip,pins = |
| /* dsm_aud_lp_m0 */ |
| <2 RK_PA0 3 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| dsm_audm0_rn: dsm_audm0-rn { |
| rockchip,pins = |
| /* dsm_aud_rn_m0 */ |
| <2 RK_PA3 3 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| dsm_audm0_rp: dsm_audm0-rp { |
| rockchip,pins = |
| /* dsm_aud_rp_m0 */ |
| <2 RK_PA2 3 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| dsm_audm1_ln: dsm_audm1-ln { |
| rockchip,pins = |
| /* dsm_aud_ln_m1 */ |
| <4 RK_PC1 1 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| dsm_audm1_lp: dsm_audm1-lp { |
| rockchip,pins = |
| /* dsm_aud_lp_m1 */ |
| <4 RK_PC0 1 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| dsm_audm1_rn: dsm_audm1-rn { |
| rockchip,pins = |
| /* dsm_aud_rn_m1 */ |
| <4 RK_PC3 1 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| dsm_audm1_rp: dsm_audm1-rp { |
| rockchip,pins = |
| /* dsm_aud_rp_m1 */ |
| <4 RK_PC2 1 &pcfg_pull_none>; |
| }; |
| }; |
| |
| dsmc { |
| /omit-if-no-ref/ |
| dsmc_clkn: dsmc-clkn { |
| rockchip,pins = |
| /* dsmc_clkn */ |
| <3 RK_PD6 5 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| dsmc_clkp: dsmc-clkp { |
| rockchip,pins = |
| /* dsmc_clkp */ |
| <3 RK_PD5 5 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| dsmc_csn0: dsmc-csn0 { |
| rockchip,pins = |
| /* dsmc_csn0 */ |
| <3 RK_PD3 5 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| dsmc_csn1: dsmc-csn1 { |
| rockchip,pins = |
| /* dsmc_csn1 */ |
| <3 RK_PB0 5 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| dsmc_csn2: dsmc-csn2 { |
| rockchip,pins = |
| /* dsmc_csn2 */ |
| <3 RK_PD1 5 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| dsmc_csn3: dsmc-csn3 { |
| rockchip,pins = |
| /* dsmc_csn3 */ |
| <3 RK_PD2 5 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| dsmc_data0: dsmc-data0 { |
| rockchip,pins = |
| /* dsmc_data0 */ |
| <3 RK_PD4 5 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| dsmc_data1: dsmc-data1 { |
| rockchip,pins = |
| /* dsmc_data1 */ |
| <3 RK_PD0 5 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| dsmc_data2: dsmc-data2 { |
| rockchip,pins = |
| /* dsmc_data2 */ |
| <3 RK_PC7 5 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| dsmc_data3: dsmc-data3 { |
| rockchip,pins = |
| /* dsmc_data3 */ |
| <3 RK_PC6 5 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| dsmc_data4: dsmc-data4 { |
| rockchip,pins = |
| /* dsmc_data4 */ |
| <3 RK_PC5 5 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| dsmc_data5: dsmc-data5 { |
| rockchip,pins = |
| /* dsmc_data5 */ |
| <3 RK_PC4 5 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| dsmc_data6: dsmc-data6 { |
| rockchip,pins = |
| /* dsmc_data6 */ |
| <3 RK_PC1 5 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| dsmc_data7: dsmc-data7 { |
| rockchip,pins = |
| /* dsmc_data7 */ |
| <3 RK_PC0 5 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| dsmc_data8: dsmc-data8 { |
| rockchip,pins = |
| /* dsmc_data8 */ |
| <3 RK_PB5 5 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| dsmc_data9: dsmc-data9 { |
| rockchip,pins = |
| /* dsmc_data9 */ |
| <3 RK_PB4 5 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| dsmc_data10: dsmc-data10 { |
| rockchip,pins = |
| /* dsmc_data10 */ |
| <3 RK_PB3 5 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| dsmc_data11: dsmc-data11 { |
| rockchip,pins = |
| /* dsmc_data11 */ |
| <3 RK_PB2 5 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| dsmc_data12: dsmc-data12 { |
| rockchip,pins = |
| /* dsmc_data12 */ |
| <3 RK_PB1 5 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| dsmc_data13: dsmc-data13 { |
| rockchip,pins = |
| /* dsmc_data13 */ |
| <3 RK_PA7 5 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| dsmc_data14: dsmc-data14 { |
| rockchip,pins = |
| /* dsmc_data14 */ |
| <3 RK_PA6 5 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| dsmc_data15: dsmc-data15 { |
| rockchip,pins = |
| /* dsmc_data15 */ |
| <3 RK_PA5 5 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| dsmc_dqs0: dsmc-dqs0 { |
| rockchip,pins = |
| /* dsmc_dqs0 */ |
| <3 RK_PB7 5 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| dsmc_dqs1: dsmc-dqs1 { |
| rockchip,pins = |
| /* dsmc_dqs1 */ |
| <3 RK_PB6 5 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| dsmc_int0: dsmc-int0 { |
| rockchip,pins = |
| /* dsmc_int0 */ |
| <4 RK_PA0 5 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| dsmc_int1: dsmc-int1 { |
| rockchip,pins = |
| /* dsmc_int1 */ |
| <3 RK_PC2 5 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| dsmc_int2: dsmc-int2 { |
| rockchip,pins = |
| /* dsmc_int2 */ |
| <4 RK_PA1 5 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| dsmc_int3: dsmc-int3 { |
| rockchip,pins = |
| /* dsmc_int3 */ |
| <3 RK_PC3 5 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| dsmc_rdyn: dsmc-rdyn { |
| rockchip,pins = |
| /* dsmc_rdyn */ |
| <3 RK_PA4 5 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| dsmc_resetn: dsmc-resetn { |
| rockchip,pins = |
| /* dsmc_resetn */ |
| <3 RK_PD7 5 &pcfg_pull_none>; |
| }; |
| }; |
| |
| dsmc_testclk { |
| /omit-if-no-ref/ |
| dsmc_testclk_out: dsmc-testclk-out { |
| rockchip,pins = |
| /* dsmc_testclk_out */ |
| <3 RK_PC2 7 &pcfg_pull_none>; |
| }; |
| }; |
| |
| dsmc_testdata { |
| /omit-if-no-ref/ |
| dsmc_testdata_out: dsmc-testdata-out { |
| rockchip,pins = |
| /* dsmc_testdata_out */ |
| <3 RK_PC3 7 &pcfg_pull_none>; |
| }; |
| }; |
| |
| edp_tx { |
| /omit-if-no-ref/ |
| edp_txm0_pins: edp_txm0-pins { |
| rockchip,pins = |
| /* edp_tx_hpdin_m0 */ |
| <4 RK_PC1 12 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| edp_txm1_pins: edp_txm1-pins { |
| rockchip,pins = |
| /* edp_tx_hpdin_m1 */ |
| <0 RK_PB6 10 &pcfg_pull_none>; |
| }; |
| }; |
| |
| emmc { |
| /omit-if-no-ref/ |
| emmc_rstnout: emmc-rstnout { |
| rockchip,pins = |
| /* emmc_rstn */ |
| <1 RK_PB3 1 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| emmc_bus8: emmc-bus8 { |
| rockchip,pins = |
| /* emmc_d0 */ |
| <1 RK_PA0 1 &pcfg_pull_up_drv_level_2>, |
| /* emmc_d1 */ |
| <1 RK_PA1 1 &pcfg_pull_up_drv_level_2>, |
| /* emmc_d2 */ |
| <1 RK_PA2 1 &pcfg_pull_up_drv_level_2>, |
| /* emmc_d3 */ |
| <1 RK_PA3 1 &pcfg_pull_up_drv_level_2>, |
| /* emmc_d4 */ |
| <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>, |
| /* emmc_d5 */ |
| <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>, |
| /* emmc_d6 */ |
| <1 RK_PA6 1 &pcfg_pull_up_drv_level_2>, |
| /* emmc_d7 */ |
| <1 RK_PA7 1 &pcfg_pull_up_drv_level_2>; |
| }; |
| |
| /omit-if-no-ref/ |
| emmc_clk: emmc-clk { |
| rockchip,pins = |
| /* emmc_clk */ |
| <1 RK_PB1 1 &pcfg_pull_up_drv_level_2>; |
| }; |
| |
| /omit-if-no-ref/ |
| emmc_cmd: emmc-cmd { |
| rockchip,pins = |
| /* emmc_cmd */ |
| <1 RK_PB0 1 &pcfg_pull_up_drv_level_2>; |
| }; |
| |
| /omit-if-no-ref/ |
| emmc_strb: emmc-strb { |
| rockchip,pins = |
| /* emmc_strb */ |
| <1 RK_PB2 1 &pcfg_pull_none>; |
| }; |
| }; |
| |
| emmc_testclk { |
| /omit-if-no-ref/ |
| emmc_testclk_test: emmc_testclk-test { |
| rockchip,pins = |
| /* emmc_testclk_out */ |
| <1 RK_PB3 6 &pcfg_pull_none>; |
| }; |
| }; |
| |
| emmc_testdata { |
| /omit-if-no-ref/ |
| emmc_testdata_test: emmc_testdata-test { |
| rockchip,pins = |
| /* emmc_testdata_out */ |
| <1 RK_PB7 5 &pcfg_pull_none>; |
| }; |
| }; |
| |
| eth0 { |
| /omit-if-no-ref/ |
| eth0m0_miim: eth0m0-miim { |
| rockchip,pins = |
| /* eth0_mdc_m0 */ |
| <3 RK_PA6 3 &pcfg_pull_none>, |
| /* eth0_mdio_m0 */ |
| <3 RK_PA5 3 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| eth0m0_rx_bus2: eth0m0-rx_bus2 { |
| rockchip,pins = |
| /* eth0_rxctl_m0 */ |
| <3 RK_PA7 3 &pcfg_pull_none>, |
| /* eth0_rxd0_m0 */ |
| <3 RK_PB2 3 &pcfg_pull_none>, |
| /* eth0_rxd1_m0 */ |
| <3 RK_PB1 3 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| eth0m0_tx_bus2: eth0m0-tx_bus2 { |
| rockchip,pins = |
| /* eth0_txctl_m0 */ |
| <3 RK_PB3 3 &pcfg_pull_none>, |
| /* eth0_txd0_m0 */ |
| <3 RK_PB5 3 &pcfg_pull_none>, |
| /* eth0_txd1_m0 */ |
| <3 RK_PB4 3 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| eth0m0_rgmii_clk: eth0m0-rgmii_clk { |
| rockchip,pins = |
| /* eth0_rxclk_m0 */ |
| <3 RK_PD1 3 &pcfg_pull_none>, |
| /* eth0_txclk_m0 */ |
| <3 RK_PB6 3 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| eth0m0_rgmii_bus: eth0m0-rgmii_bus { |
| rockchip,pins = |
| /* eth0_rxd2_m0 */ |
| <3 RK_PD3 3 &pcfg_pull_none>, |
| /* eth0_rxd3_m0 */ |
| <3 RK_PD2 3 &pcfg_pull_none>, |
| /* eth0_txd2_m0 */ |
| <3 RK_PC3 3 &pcfg_pull_none>, |
| /* eth0_txd3_m0 */ |
| <3 RK_PC2 3 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| eth0m0_mclk: eth0m0-mclk { |
| rockchip,pins = |
| /* eth0m0_mclk */ |
| <3 RK_PB0 3 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| eth0m0_ppsclk: eth0m0-ppsclk { |
| rockchip,pins = |
| /* eth0m0_ppsclk */ |
| <3 RK_PC0 3 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| eth0m0_ppstrig: eth0m0-ppstrig { |
| rockchip,pins = |
| /* eth0m0_ppstrig */ |
| <3 RK_PB7 3 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| eth0m1_miim: eth0m1-miim { |
| rockchip,pins = |
| /* eth0_mdc_m1 */ |
| <3 RK_PA1 3 &pcfg_pull_none>, |
| /* eth0_mdio_m1 */ |
| <3 RK_PA0 3 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| eth0m1_rx_bus2: eth0m1-rx_bus2 { |
| rockchip,pins = |
| /* eth0_rxctl_m1 */ |
| <3 RK_PA2 3 &pcfg_pull_none>, |
| /* eth0_rxd0_m1 */ |
| <2 RK_PA6 3 &pcfg_pull_none>, |
| /* eth0_rxd1_m1 */ |
| <3 RK_PA3 3 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| eth0m1_tx_bus2: eth0m1-tx_bus2 { |
| rockchip,pins = |
| /* eth0_txctl_m1 */ |
| <2 RK_PA7 3 &pcfg_pull_none>, |
| /* eth0_txd0_m1 */ |
| <2 RK_PB1 3 &pcfg_pull_none>, |
| /* eth0_txd1_m1 */ |
| <2 RK_PB0 3 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| eth0m1_rgmii_clk: eth0m1-rgmii_clk { |
| rockchip,pins = |
| /* eth0_rxclk_m1 */ |
| <2 RK_PB5 3 &pcfg_pull_none>, |
| /* eth0_txclk_m1 */ |
| <2 RK_PB3 3 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| eth0m1_rgmii_bus: eth0m1-rgmii_bus { |
| rockchip,pins = |
| /* eth0_rxd2_m1 */ |
| <2 RK_PB7 3 &pcfg_pull_none>, |
| /* eth0_rxd3_m1 */ |
| <2 RK_PB6 3 &pcfg_pull_none>, |
| /* eth0_txd2_m1 */ |
| <2 RK_PB4 3 &pcfg_pull_none>, |
| /* eth0_txd3_m1 */ |
| <2 RK_PB2 3 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| eth0m1_mclk: eth0m1-mclk { |
| rockchip,pins = |
| /* eth0m1_mclk */ |
| <2 RK_PD6 3 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| eth0m1_ppsclk: eth0m1-ppsclk { |
| rockchip,pins = |
| /* eth0m1_ppsclk */ |
| <2 RK_PC1 3 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| eth0m1_ppstrig: eth0m1-ppstrig { |
| rockchip,pins = |
| /* eth0m1_ppstrig */ |
| <2 RK_PC2 3 &pcfg_pull_none>; |
| }; |
| }; |
| |
| eth1 { |
| /omit-if-no-ref/ |
| eth1m0_miim: eth1m0-miim { |
| rockchip,pins = |
| /* eth1_mdc_m0 */ |
| <2 RK_PD4 2 &pcfg_pull_none>, |
| /* eth1_mdio_m0 */ |
| <2 RK_PD5 2 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| eth1m0_rx_bus2: eth1m0-rx_bus2 { |
| rockchip,pins = |
| /* eth1_rxctl_m0 */ |
| <2 RK_PD3 2 &pcfg_pull_none>, |
| /* eth1_rxd0_m0 */ |
| <2 RK_PD1 2 &pcfg_pull_none>, |
| /* eth1_rxd1_m0 */ |
| <2 RK_PD2 2 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| eth1m0_tx_bus2: eth1m0-tx_bus2 { |
| rockchip,pins = |
| /* eth1_txctl_m0 */ |
| <2 RK_PD0 2 &pcfg_pull_none>, |
| /* eth1_txd0_m0 */ |
| <2 RK_PC6 2 &pcfg_pull_none>, |
| /* eth1_txd1_m0 */ |
| <2 RK_PC7 2 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| eth1m0_rgmii_clk: eth1m0-rgmii_clk { |
| rockchip,pins = |
| /* eth1_rxclk_m0 */ |
| <2 RK_PC2 2 &pcfg_pull_none>, |
| /* eth1_txclk_m0 */ |
| <2 RK_PC5 2 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| eth1m0_rgmii_bus: eth1m0-rgmii_bus { |
| rockchip,pins = |
| /* eth1_rxd2_m0 */ |
| <2 RK_PC0 2 &pcfg_pull_none>, |
| /* eth1_rxd3_m0 */ |
| <2 RK_PC1 2 &pcfg_pull_none>, |
| /* eth1_txd2_m0 */ |
| <2 RK_PC3 2 &pcfg_pull_none>, |
| /* eth1_txd3_m0 */ |
| <2 RK_PC4 2 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| eth1m0_mclk: eth1m0-mclk { |
| rockchip,pins = |
| /* eth1m0_mclk */ |
| <2 RK_PD7 2 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| eth1m0_ppsclk: eth1m0-ppsclk { |
| rockchip,pins = |
| /* eth1m0_ppsclk */ |
| <3 RK_PA2 2 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| eth1m0_ppstrig: eth1m0-ppstrig { |
| rockchip,pins = |
| /* eth1m0_ppstrig */ |
| <3 RK_PA1 2 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| eth1m1_miim: eth1m1-miim { |
| rockchip,pins = |
| /* eth1_mdc_m1 */ |
| <1 RK_PD2 1 &pcfg_pull_none>, |
| /* eth1_mdio_m1 */ |
| <1 RK_PD3 1 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| eth1m1_rx_bus2: eth1m1-rx_bus2 { |
| rockchip,pins = |
| /* eth1_rxctl_m1 */ |
| <1 RK_PD1 1 &pcfg_pull_none>, |
| /* eth1_rxd0_m1 */ |
| <1 RK_PC7 1 &pcfg_pull_none>, |
| /* eth1_rxd1_m1 */ |
| <1 RK_PD0 1 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| eth1m1_tx_bus2: eth1m1-tx_bus2 { |
| rockchip,pins = |
| /* eth1_txctl_m1 */ |
| <1 RK_PC6 1 &pcfg_pull_none>, |
| /* eth1_txd0_m1 */ |
| <1 RK_PC4 1 &pcfg_pull_none>, |
| /* eth1_txd1_m1 */ |
| <1 RK_PC5 1 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| eth1m1_rgmii_clk: eth1m1-rgmii_clk { |
| rockchip,pins = |
| /* eth1_rxclk_m1 */ |
| <1 RK_PB6 1 &pcfg_pull_none>, |
| /* eth1_txclk_m1 */ |
| <1 RK_PC1 1 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| eth1m1_rgmii_bus: eth1m1-rgmii_bus { |
| rockchip,pins = |
| /* eth1_rxd2_m1 */ |
| <1 RK_PB4 1 &pcfg_pull_none>, |
| /* eth1_rxd3_m1 */ |
| <1 RK_PB5 1 &pcfg_pull_none>, |
| /* eth1_txd2_m1 */ |
| <1 RK_PB7 1 &pcfg_pull_none>, |
| /* eth1_txd3_m1 */ |
| <1 RK_PC0 1 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| eth1m1_mclk: eth1m1-mclk { |
| rockchip,pins = |
| /* eth1m1_mclk */ |
| <1 RK_PD4 1 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| eth1m1_ppsclk: eth1m1-ppsclk { |
| rockchip,pins = |
| /* eth1m1_ppsclk */ |
| <1 RK_PC2 1 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| eth1m1_ppstrig: eth1m1-ppstrig { |
| rockchip,pins = |
| /* eth1m1_ppstrig */ |
| <1 RK_PC3 1 &pcfg_pull_none>; |
| }; |
| }; |
| |
| eth0_ptp { |
| /omit-if-no-ref/ |
| eth0m0_ptp_refclk: eth0m0-ptp-refclk { |
| rockchip,pins = |
| /* eth0m0_ptp_refclk */ |
| <3 RK_PC1 3 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| eth0m1_ptp_refclk: eth0m1-ptp-refclk { |
| rockchip,pins = |
| /* eth0m1_ptp_refclk */ |
| <2 RK_PC0 3 &pcfg_pull_none>; |
| }; |
| }; |
| |
| eth0_testrxclk { |
| /omit-if-no-ref/ |
| eth0_testrxclkm0_test: eth0_testrxclkm0-test { |
| rockchip,pins = |
| /* eth0_testrxclk_out_m0 */ |
| <3 RK_PC7 3 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| eth0_testrxclkm1_test: eth0_testrxclkm1-test { |
| rockchip,pins = |
| /* eth0_testrxclk_out_m1 */ |
| <2 RK_PC5 6 &pcfg_pull_none>; |
| }; |
| }; |
| |
| eth0_testrxd { |
| /omit-if-no-ref/ |
| eth0_testrxdm0_test: eth0_testrxdm0-test { |
| rockchip,pins = |
| /* eth0_testrxd_out_m0 */ |
| <3 RK_PD0 3 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| eth0_testrxdm1_test: eth0_testrxdm1-test { |
| rockchip,pins = |
| /* eth0_testrxd_out_m1 */ |
| <2 RK_PC4 6 &pcfg_pull_none>; |
| }; |
| }; |
| |
| eth1_ptp { |
| /omit-if-no-ref/ |
| eth1m0_ptp_refclk: eth1m0-ptp-refclk { |
| rockchip,pins = |
| /* eth1m0_ptp_refclk */ |
| <3 RK_PA3 2 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| eth1m1_ptp_refclk: eth1m1-ptp-refclk { |
| rockchip,pins = |
| /* eth1m1_ptp_refclk */ |
| <2 RK_PB6 2 &pcfg_pull_none>; |
| }; |
| }; |
| |
| eth1_testrxclk { |
| /omit-if-no-ref/ |
| eth1_testrxclkm0_test: eth1_testrxclkm0-test { |
| rockchip,pins = |
| /* eth1_testrxclk_out_m0 */ |
| <3 RK_PA1 6 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| eth1_testrxclkm1_test: eth1_testrxclkm1-test { |
| rockchip,pins = |
| /* eth1_testrxclk_out_m1 */ |
| <1 RK_PC3 6 &pcfg_pull_none>; |
| }; |
| }; |
| |
| eth1_testrxd { |
| /omit-if-no-ref/ |
| eth1_testrxdm0_test: eth1_testrxdm0-test { |
| rockchip,pins = |
| /* eth1_testrxd_out_m0 */ |
| <3 RK_PA0 6 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| eth1_testrxdm1_test: eth1_testrxdm1-test { |
| rockchip,pins = |
| /* eth1_testrxd_out_m1 */ |
| <1 RK_PC2 6 &pcfg_pull_none>; |
| }; |
| }; |
| |
| eth_clk0_25m { |
| /omit-if-no-ref/ |
| ethm0_clk0_25m_out: ethm0-clk0-25m-out { |
| rockchip,pins = |
| /* ethm0_clk0_25m_out */ |
| <3 RK_PA4 3 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| ethm1_clk0_25m_out: ethm1-clk0-25m-out { |
| rockchip,pins = |
| /* ethm1_clk0_25m_out */ |
| <2 RK_PD7 3 &pcfg_pull_none>; |
| }; |
| }; |
| |
| eth_clk1_25m { |
| /omit-if-no-ref/ |
| ethm0_clk1_25m_out: ethm0-clk1-25m-out { |
| rockchip,pins = |
| /* ethm0_clk1_25m_out */ |
| <2 RK_PD6 2 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| ethm1_clk1_25m_out: ethm1-clk1-25m-out { |
| rockchip,pins = |
| /* ethm1_clk1_25m_out */ |
| <1 RK_PD5 1 &pcfg_pull_none>; |
| }; |
| }; |
| |
| flexbus0 { |
| /omit-if-no-ref/ |
| flexbus0m0_csn: flexbus0m0-csn { |
| rockchip,pins = |
| /* flexbus0_csn_m0 */ |
| <3 RK_PA4 8 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| flexbus0m0_d13: flexbus0m0-d13 { |
| rockchip,pins = |
| /* flexbus0_d13_m0 */ |
| <4 RK_PA0 6 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| flexbus0m0_d14: flexbus0m0-d14 { |
| rockchip,pins = |
| /* flexbus0_d14_m0 */ |
| <4 RK_PA1 6 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| flexbus0m0_d15: flexbus0m0-d15 { |
| rockchip,pins = |
| /* flexbus0_d15_m0 */ |
| <3 RK_PD7 6 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| flexbus0m1_csn: flexbus0m1-csn { |
| rockchip,pins = |
| /* flexbus0_csn_m1 */ |
| <4 RK_PA1 8 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| flexbus0m1_d13: flexbus0m1-d13 { |
| rockchip,pins = |
| /* flexbus0_d13_m1 */ |
| <4 RK_PA4 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| flexbus0m1_d14: flexbus0m1-d14 { |
| rockchip,pins = |
| /* flexbus0_d14_m1 */ |
| <4 RK_PA6 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| flexbus0m1_d15: flexbus0m1-d15 { |
| rockchip,pins = |
| /* flexbus0_d15_m1 */ |
| <4 RK_PB5 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| flexbus0m2_csn: flexbus0m2-csn { |
| rockchip,pins = |
| /* flexbus0_csn_m2 */ |
| <3 RK_PC3 8 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| flexbus0m3_csn: flexbus0m3-csn { |
| rockchip,pins = |
| /* flexbus0_csn_m3 */ |
| <3 RK_PD2 8 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| flexbus0m4_csn: flexbus0m4-csn { |
| rockchip,pins = |
| /* flexbus0_csn_m4 */ |
| <4 RK_PB4 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| flexbus0_clk: flexbus0-clk { |
| rockchip,pins = |
| /* flexbus0_clk */ |
| <3 RK_PB6 6 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| flexbus0_d10: flexbus0-d10 { |
| rockchip,pins = |
| /* flexbus0_d10 */ |
| <3 RK_PC3 6 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| flexbus0_d11: flexbus0-d11 { |
| rockchip,pins = |
| /* flexbus0_d11 */ |
| <3 RK_PD1 6 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| flexbus0_d12: flexbus0-d12 { |
| rockchip,pins = |
| /* flexbus0_d12 */ |
| <3 RK_PD2 6 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| flexbus0_d0: flexbus0-d0 { |
| rockchip,pins = |
| /* flexbus0_d0 */ |
| <3 RK_PB5 6 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| flexbus0_d1: flexbus0-d1 { |
| rockchip,pins = |
| /* flexbus0_d1 */ |
| <3 RK_PB4 6 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| flexbus0_d2: flexbus0-d2 { |
| rockchip,pins = |
| /* flexbus0_d2 */ |
| <3 RK_PB3 6 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| flexbus0_d3: flexbus0-d3 { |
| rockchip,pins = |
| /* flexbus0_d3 */ |
| <3 RK_PB2 6 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| flexbus0_d4: flexbus0-d4 { |
| rockchip,pins = |
| /* flexbus0_d4 */ |
| <3 RK_PB1 6 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| flexbus0_d5: flexbus0-d5 { |
| rockchip,pins = |
| /* flexbus0_d5 */ |
| <3 RK_PA7 6 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| flexbus0_d6: flexbus0-d6 { |
| rockchip,pins = |
| /* flexbus0_d6 */ |
| <3 RK_PA6 6 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| flexbus0_d7: flexbus0-d7 { |
| rockchip,pins = |
| /* flexbus0_d7 */ |
| <3 RK_PA5 6 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| flexbus0_d8: flexbus0-d8 { |
| rockchip,pins = |
| /* flexbus0_d8 */ |
| <3 RK_PB0 6 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| flexbus0_d9: flexbus0-d9 { |
| rockchip,pins = |
| /* flexbus0_d9 */ |
| <3 RK_PC2 6 &pcfg_pull_none>; |
| }; |
| }; |
| |
| flexbus1 { |
| /omit-if-no-ref/ |
| flexbus1m0_csn: flexbus1m0-csn { |
| rockchip,pins = |
| /* flexbus1_csn_m0 */ |
| <3 RK_PB7 8 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| flexbus1m0_d12: flexbus1m0-d12 { |
| rockchip,pins = |
| /* flexbus1_d12_m0 */ |
| <3 RK_PD7 7 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| flexbus1m0_d13: flexbus1m0-d13 { |
| rockchip,pins = |
| /* flexbus1_d13_m0 */ |
| <4 RK_PA1 7 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| flexbus1m0_d14: flexbus1m0-d14 { |
| rockchip,pins = |
| /* flexbus1_d14_m0 */ |
| <4 RK_PA0 7 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| flexbus1m0_d15: flexbus1m0-d15 { |
| rockchip,pins = |
| /* flexbus1_d15_m0 */ |
| <3 RK_PD2 7 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| flexbus1m1_csn: flexbus1m1-csn { |
| rockchip,pins = |
| /* flexbus1_csn_m1 */ |
| <3 RK_PD7 8 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| flexbus1m1_d12: flexbus1m1-d12 { |
| rockchip,pins = |
| /* flexbus1_d12_m1 */ |
| <4 RK_PA5 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| flexbus1m1_d13: flexbus1m1-d13 { |
| rockchip,pins = |
| /* flexbus1_d13_m1 */ |
| <4 RK_PB0 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| flexbus1m1_d14: flexbus1m1-d14 { |
| rockchip,pins = |
| /* flexbus1_d14_m1 */ |
| <4 RK_PB1 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| flexbus1m1_d15: flexbus1m1-d15 { |
| rockchip,pins = |
| /* flexbus1_d15_m1 */ |
| <4 RK_PB2 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| flexbus1m2_csn: flexbus1m2-csn { |
| rockchip,pins = |
| /* flexbus1_csn_m2 */ |
| <3 RK_PD1 8 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| flexbus1m3_csn: flexbus1m3-csn { |
| rockchip,pins = |
| /* flexbus1_csn_m3 */ |
| <4 RK_PA0 8 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| flexbus1m4_csn: flexbus1m4-csn { |
| rockchip,pins = |
| /* flexbus1_csn_m4 */ |
| <4 RK_PA3 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| flexbus1_clk: flexbus1-clk { |
| rockchip,pins = |
| /* flexbus1_clk */ |
| <3 RK_PD6 6 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| flexbus1_d10: flexbus1-d10 { |
| rockchip,pins = |
| /* flexbus1_d10 */ |
| <3 RK_PB7 6 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| flexbus1_d11: flexbus1-d11 { |
| rockchip,pins = |
| /* flexbus1_d11 */ |
| <3 RK_PA4 6 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| flexbus1_d0: flexbus1-d0 { |
| rockchip,pins = |
| /* flexbus1_d0 */ |
| <3 RK_PD5 6 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| flexbus1_d1: flexbus1-d1 { |
| rockchip,pins = |
| /* flexbus1_d1 */ |
| <3 RK_PD4 6 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| flexbus1_d2: flexbus1-d2 { |
| rockchip,pins = |
| /* flexbus1_d2 */ |
| <3 RK_PD3 6 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| flexbus1_d3: flexbus1-d3 { |
| rockchip,pins = |
| /* flexbus1_d3 */ |
| <3 RK_PD0 6 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| flexbus1_d4: flexbus1-d4 { |
| rockchip,pins = |
| /* flexbus1_d4 */ |
| <3 RK_PC7 6 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| flexbus1_d5: flexbus1-d5 { |
| rockchip,pins = |
| /* flexbus1_d5 */ |
| <3 RK_PC6 6 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| flexbus1_d6: flexbus1-d6 { |
| rockchip,pins = |
| /* flexbus1_d6 */ |
| <3 RK_PC5 6 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| flexbus1_d7: flexbus1-d7 { |
| rockchip,pins = |
| /* flexbus1_d7 */ |
| <3 RK_PC4 6 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| flexbus1_d8: flexbus1-d8 { |
| rockchip,pins = |
| /* flexbus1_d8 */ |
| <3 RK_PC1 6 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| flexbus1_d9: flexbus1-d9 { |
| rockchip,pins = |
| /* flexbus1_d9 */ |
| <3 RK_PC0 6 &pcfg_pull_none>; |
| }; |
| }; |
| |
| flexbus0_testclk { |
| /omit-if-no-ref/ |
| flexbus0_testclk_testclk: flexbus0_testclk-testclk { |
| rockchip,pins = |
| /* flexbus0_testclk_out */ |
| <2 RK_PA3 6 &pcfg_pull_none>; |
| }; |
| }; |
| |
| flexbus0_testdata { |
| /omit-if-no-ref/ |
| flexbus0_testdata_testdata: flexbus0_testdata-testdata { |
| rockchip,pins = |
| /* flexbus0_testdata_out */ |
| <2 RK_PA2 6 &pcfg_pull_none>; |
| }; |
| }; |
| |
| flexbus1_testclk { |
| /omit-if-no-ref/ |
| flexbus1_testclk_testclk: flexbus1_testclk-testclk { |
| rockchip,pins = |
| /* flexbus1_testclk_out */ |
| <2 RK_PA5 6 &pcfg_pull_none>; |
| }; |
| }; |
| |
| flexbus1_testdata { |
| /omit-if-no-ref/ |
| flexbus1_testdata_testdata: flexbus1_testdata-testdata { |
| rockchip,pins = |
| /* flexbus1_testdata_out */ |
| <2 RK_PA4 6 &pcfg_pull_none>; |
| }; |
| }; |
| |
| fspi0 { |
| /omit-if-no-ref/ |
| fspi0_pins: fspi0-pins { |
| rockchip,pins = |
| /* fspi0_clk */ |
| <1 RK_PB1 2 &pcfg_pull_none>, |
| /* fspi0_d0 */ |
| <1 RK_PA0 2 &pcfg_pull_none>, |
| /* fspi0_d1 */ |
| <1 RK_PA1 2 &pcfg_pull_none>, |
| /* fspi0_d2 */ |
| <1 RK_PA2 2 &pcfg_pull_none>, |
| /* fspi0_d3 */ |
| <1 RK_PA3 2 &pcfg_pull_none>, |
| /* fspi0_d4 */ |
| <1 RK_PA4 2 &pcfg_pull_none>, |
| /* fspi0_d5 */ |
| <1 RK_PA5 2 &pcfg_pull_none>, |
| /* fspi0_d6 */ |
| <1 RK_PA6 2 &pcfg_pull_none>, |
| /* fspi0_d7 */ |
| <1 RK_PA7 2 &pcfg_pull_none>, |
| /* fspi0_dqs */ |
| <1 RK_PB2 2 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| fspi0_csn0: fspi0-csn0 { |
| rockchip,pins = |
| /* fspi0_csn0 */ |
| <1 RK_PB3 2 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| fspi0_csn1: fspi0-csn1 { |
| rockchip,pins = |
| /* fspi0_csn1 */ |
| <1 RK_PB0 2 &pcfg_pull_none>; |
| }; |
| }; |
| |
| fspi1 { |
| /omit-if-no-ref/ |
| fspi1m0_pins: fspi1m0-pins { |
| rockchip,pins = |
| /* fspi1_clk_m0 */ |
| <2 RK_PA5 2 &pcfg_pull_none>, |
| /* fspi1_d0_m0 */ |
| <2 RK_PA0 2 &pcfg_pull_none>, |
| /* fspi1_d1_m0 */ |
| <2 RK_PA1 2 &pcfg_pull_none>, |
| /* fspi1_d2_m0 */ |
| <2 RK_PA2 2 &pcfg_pull_none>, |
| /* fspi1_d3_m0 */ |
| <2 RK_PA3 2 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| fspi1m0_csn0: fspi1m0-csn0 { |
| rockchip,pins = |
| /* fspi1m0_csn0 */ |
| <2 RK_PA4 2 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| fspi1m1_pins: fspi1m1-pins { |
| rockchip,pins = |
| /* fspi1_clk_m1 */ |
| <1 RK_PD5 3 &pcfg_pull_none>, |
| /* fspi1_d0_m1 */ |
| <1 RK_PC4 3 &pcfg_pull_none>, |
| /* fspi1_d1_m1 */ |
| <1 RK_PC5 3 &pcfg_pull_none>, |
| /* fspi1_d2_m1 */ |
| <1 RK_PC6 3 &pcfg_pull_none>, |
| /* fspi1_d3_m1 */ |
| <1 RK_PC7 3 &pcfg_pull_none>, |
| /* fspi1_d4_m1 */ |
| <1 RK_PD0 3 &pcfg_pull_none>, |
| /* fspi1_d5_m1 */ |
| <1 RK_PD1 3 &pcfg_pull_none>, |
| /* fspi1_d6_m1 */ |
| <1 RK_PD2 3 &pcfg_pull_none>, |
| /* fspi1_d7_m1 */ |
| <1 RK_PD3 3 &pcfg_pull_none>, |
| /* fspi1_dqs_m1 */ |
| <1 RK_PD4 3 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| fspi1m1_csn0: fspi1m1-csn0 { |
| rockchip,pins = |
| /* fspi1m1_csn0 */ |
| <1 RK_PC3 3 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| fspi1m1_csn1: fspi1m1-csn1 { |
| rockchip,pins = |
| /* fspi1m1_csn1 */ |
| <1 RK_PC2 3 &pcfg_pull_none>; |
| }; |
| }; |
| |
| fspi0_testclk { |
| /omit-if-no-ref/ |
| fspi0_testclk_test: fspi0_testclk-test { |
| rockchip,pins = |
| /* fspi0_testclk_out */ |
| <1 RK_PB0 6 &pcfg_pull_none>; |
| }; |
| }; |
| |
| fspi0_testdata { |
| /omit-if-no-ref/ |
| fspi0_testdata_test: fspi0_testdata-test { |
| rockchip,pins = |
| /* fspi0_testdata_out */ |
| <1 RK_PB7 6 &pcfg_pull_none>; |
| }; |
| }; |
| |
| fspi1_testclk { |
| /omit-if-no-ref/ |
| fspi1_testclkm1_test: fspi1_testclkm1-test { |
| rockchip,pins = |
| /* fspi1_testclk_out_m1 */ |
| <1 RK_PC1 7 &pcfg_pull_none>; |
| }; |
| }; |
| |
| fspi1_testdata { |
| /omit-if-no-ref/ |
| fspi1_testdatam1_test: fspi1_testdatam1-test { |
| rockchip,pins = |
| /* fspi1_testdata_out_m1 */ |
| <1 RK_PB7 7 &pcfg_pull_none>; |
| }; |
| }; |
| |
| gpu { |
| /omit-if-no-ref/ |
| gpu_pins: gpu-pins { |
| rockchip,pins = |
| /* gpu_avs */ |
| <0 RK_PD3 11 &pcfg_pull_none>; |
| }; |
| }; |
| |
| hdmi_tx { |
| /omit-if-no-ref/ |
| hdmi_txm0_pins: hdmi_txm0-pins { |
| rockchip,pins = |
| /* hdmi_tx_cec_m0 */ |
| <4 RK_PC0 9 &pcfg_pull_none>, |
| /* hdmi_tx_hpdin_m0 */ |
| <4 RK_PC1 9 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| hdmi_txm1_pins: hdmi_txm1-pins { |
| rockchip,pins = |
| /* hdmi_tx_cec_m1 */ |
| <0 RK_PC3 9 &pcfg_pull_none>, |
| /* hdmi_tx_hpdin_m1 */ |
| <0 RK_PB6 9 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| hdmi_tx_scl: hdmi-tx-scl { |
| rockchip,pins = |
| /* hdmi_tx_scl */ |
| <4 RK_PC2 9 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| hdmi_tx_sda: hdmi-tx-sda { |
| rockchip,pins = |
| /* hdmi_tx_sda */ |
| <4 RK_PC3 9 &pcfg_pull_none>; |
| }; |
| }; |
| |
| i2c0 { |
| /omit-if-no-ref/ |
| i2c0m0_xfer: i2c0m0-xfer { |
| rockchip,pins = |
| /* i2c0_scl_m0 */ |
| <0 RK_PB0 11 &pcfg_pull_none_smt>, |
| /* i2c0_sda_m0 */ |
| <0 RK_PB1 11 &pcfg_pull_none_smt>; |
| }; |
| |
| /omit-if-no-ref/ |
| i2c0m1_xfer: i2c0m1-xfer { |
| rockchip,pins = |
| /* i2c0_scl_m1 */ |
| <0 RK_PC1 9 &pcfg_pull_none_smt>, |
| /* i2c0_sda_m1 */ |
| <0 RK_PC2 9 &pcfg_pull_none_smt>; |
| }; |
| }; |
| |
| i2c1 { |
| /omit-if-no-ref/ |
| i2c1m0_xfer: i2c1m0-xfer { |
| rockchip,pins = |
| /* i2c1_scl_m0 */ |
| <0 RK_PB2 11 &pcfg_pull_none_smt>, |
| /* i2c1_sda_m0 */ |
| <0 RK_PB3 11 &pcfg_pull_none_smt>; |
| }; |
| |
| /omit-if-no-ref/ |
| i2c1m1_xfer: i2c1m1-xfer { |
| rockchip,pins = |
| /* i2c1_scl_m1 */ |
| <0 RK_PB4 9 &pcfg_pull_none_smt>, |
| /* i2c1_sda_m1 */ |
| <0 RK_PB5 9 &pcfg_pull_none_smt>; |
| }; |
| }; |
| |
| i2c2 { |
| /omit-if-no-ref/ |
| i2c2m0_xfer: i2c2m0-xfer { |
| rockchip,pins = |
| /* i2c2_scl_m0 */ |
| <0 RK_PB7 9 &pcfg_pull_none_smt>, |
| /* i2c2_sda_m0 */ |
| <0 RK_PC0 9 &pcfg_pull_none_smt>; |
| }; |
| |
| /omit-if-no-ref/ |
| i2c2m1_xfer: i2c2m1-xfer { |
| rockchip,pins = |
| /* i2c2_scl_m1 */ |
| <1 RK_PA0 10 &pcfg_pull_none_smt>, |
| /* i2c2_sda_m1 */ |
| <1 RK_PA1 10 &pcfg_pull_none_smt>; |
| }; |
| |
| /omit-if-no-ref/ |
| i2c2m2_xfer: i2c2m2-xfer { |
| rockchip,pins = |
| /* i2c2_scl_m2 */ |
| <4 RK_PA3 11 &pcfg_pull_none_smt>, |
| /* i2c2_sda_m2 */ |
| <4 RK_PA5 11 &pcfg_pull_none_smt>; |
| }; |
| |
| /omit-if-no-ref/ |
| i2c2m3_xfer: i2c2m3-xfer { |
| rockchip,pins = |
| /* i2c2_scl_m3 */ |
| <4 RK_PC2 11 &pcfg_pull_none_smt>, |
| /* i2c2_sda_m3 */ |
| <4 RK_PC3 11 &pcfg_pull_none_smt>; |
| }; |
| }; |
| |
| i2c3 { |
| /omit-if-no-ref/ |
| i2c3m0_xfer: i2c3m0-xfer { |
| rockchip,pins = |
| /* i2c3_scl_m0 */ |
| <4 RK_PB5 11 &pcfg_pull_none_smt>, |
| /* i2c3_sda_m0 */ |
| <4 RK_PB4 11 &pcfg_pull_none_smt>; |
| }; |
| |
| /omit-if-no-ref/ |
| i2c3m1_xfer: i2c3m1-xfer { |
| rockchip,pins = |
| /* i2c3_scl_m1 */ |
| <0 RK_PC6 9 &pcfg_pull_none_smt>, |
| /* i2c3_sda_m1 */ |
| <0 RK_PC7 9 &pcfg_pull_none_smt>; |
| }; |
| |
| /omit-if-no-ref/ |
| i2c3m2_xfer: i2c3m2-xfer { |
| rockchip,pins = |
| /* i2c3_scl_m2 */ |
| <3 RK_PD4 11 &pcfg_pull_none_smt>, |
| /* i2c3_sda_m2 */ |
| <3 RK_PD5 11 &pcfg_pull_none_smt>; |
| }; |
| |
| /omit-if-no-ref/ |
| i2c3m3_xfer: i2c3m3-xfer { |
| rockchip,pins = |
| /* i2c3_scl_m3 */ |
| <4 RK_PC4 11 &pcfg_pull_none_smt>, |
| /* i2c3_sda_m3 */ |
| <4 RK_PC5 11 &pcfg_pull_none_smt>; |
| }; |
| }; |
| |
| i2c4 { |
| /omit-if-no-ref/ |
| i2c4m0_xfer: i2c4m0-xfer { |
| rockchip,pins = |
| /* i2c4_scl_m0 */ |
| <0 RK_PD2 9 &pcfg_pull_none_smt>, |
| /* i2c4_sda_m0 */ |
| <0 RK_PD3 9 &pcfg_pull_none_smt>; |
| }; |
| |
| /omit-if-no-ref/ |
| i2c4m1_xfer: i2c4m1-xfer { |
| rockchip,pins = |
| /* i2c4_scl_m1 */ |
| <4 RK_PA4 11 &pcfg_pull_none_smt>, |
| /* i2c4_sda_m1 */ |
| <4 RK_PA6 11 &pcfg_pull_none_smt>; |
| }; |
| |
| /omit-if-no-ref/ |
| i2c4m2_xfer: i2c4m2-xfer { |
| rockchip,pins = |
| /* i2c4_scl_m2 */ |
| <2 RK_PA6 11 &pcfg_pull_none_smt>, |
| /* i2c4_sda_m2 */ |
| <2 RK_PA7 11 &pcfg_pull_none_smt>; |
| }; |
| |
| /omit-if-no-ref/ |
| i2c4m3_xfer: i2c4m3-xfer { |
| rockchip,pins = |
| /* i2c4_scl_m3 */ |
| <3 RK_PC0 11 &pcfg_pull_none_smt>, |
| /* i2c4_sda_m3 */ |
| <3 RK_PB7 11 &pcfg_pull_none_smt>; |
| }; |
| }; |
| |
| i2c5 { |
| /omit-if-no-ref/ |
| i2c5m0_xfer: i2c5m0-xfer { |
| rockchip,pins = |
| /* i2c5_scl_m0 */ |
| <2 RK_PA5 11 &pcfg_pull_none_smt>, |
| /* i2c5_sda_m0 */ |
| <2 RK_PA4 11 &pcfg_pull_none_smt>; |
| }; |
| |
| /omit-if-no-ref/ |
| i2c5m1_xfer: i2c5m1-xfer { |
| rockchip,pins = |
| /* i2c5_scl_m1 */ |
| <1 RK_PD4 10 &pcfg_pull_none_smt>, |
| /* i2c5_sda_m1 */ |
| <1 RK_PD5 10 &pcfg_pull_none_smt>; |
| }; |
| |
| /omit-if-no-ref/ |
| i2c5m2_xfer: i2c5m2-xfer { |
| rockchip,pins = |
| /* i2c5_scl_m2 */ |
| <2 RK_PC6 11 &pcfg_pull_none_smt>, |
| /* i2c5_sda_m2 */ |
| <2 RK_PC7 11 &pcfg_pull_none_smt>; |
| }; |
| |
| /omit-if-no-ref/ |
| i2c5m3_xfer: i2c5m3-xfer { |
| rockchip,pins = |
| /* i2c5_scl_m3 */ |
| <3 RK_PC4 11 &pcfg_pull_none_smt>, |
| /* i2c5_sda_m3 */ |
| <3 RK_PC1 11 &pcfg_pull_none_smt>; |
| }; |
| }; |
| |
| i2c6 { |
| /omit-if-no-ref/ |
| i2c6m0_xfer: i2c6m0-xfer { |
| rockchip,pins = |
| /* i2c6_scl_m0 */ |
| <0 RK_PA2 11 &pcfg_pull_none_smt>, |
| /* i2c6_sda_m0 */ |
| <0 RK_PA5 11 &pcfg_pull_none_smt>; |
| }; |
| |
| /omit-if-no-ref/ |
| i2c6m1_xfer: i2c6m1-xfer { |
| rockchip,pins = |
| /* i2c6_scl_m1 */ |
| <1 RK_PC2 10 &pcfg_pull_none_smt>, |
| /* i2c6_sda_m1 */ |
| <1 RK_PC3 10 &pcfg_pull_none_smt>; |
| }; |
| |
| /omit-if-no-ref/ |
| i2c6m2_xfer: i2c6m2-xfer { |
| rockchip,pins = |
| /* i2c6_scl_m2 */ |
| <2 RK_PD0 11 &pcfg_pull_none_smt>, |
| /* i2c6_sda_m2 */ |
| <2 RK_PD1 11 &pcfg_pull_none_smt>; |
| }; |
| |
| /omit-if-no-ref/ |
| i2c6m3_xfer: i2c6m3-xfer { |
| rockchip,pins = |
| /* i2c6_scl_m3 */ |
| <4 RK_PC6 11 &pcfg_pull_none_smt>, |
| /* i2c6_sda_m3 */ |
| <4 RK_PC7 11 &pcfg_pull_none_smt>; |
| }; |
| }; |
| |
| i2c7 { |
| /omit-if-no-ref/ |
| i2c7m0_xfer: i2c7m0-xfer { |
| rockchip,pins = |
| /* i2c7_scl_m0 */ |
| <1 RK_PB0 10 &pcfg_pull_none_smt>, |
| /* i2c7_sda_m0 */ |
| <1 RK_PB3 10 &pcfg_pull_none_smt>; |
| }; |
| |
| /omit-if-no-ref/ |
| i2c7m1_xfer: i2c7m1-xfer { |
| rockchip,pins = |
| /* i2c7_scl_m1 */ |
| <3 RK_PA0 11 &pcfg_pull_none_smt>, |
| /* i2c7_sda_m1 */ |
| <3 RK_PA1 11 &pcfg_pull_none_smt>; |
| }; |
| |
| /omit-if-no-ref/ |
| i2c7m2_xfer: i2c7m2-xfer { |
| rockchip,pins = |
| /* i2c7_scl_m2 */ |
| <4 RK_PA0 11 &pcfg_pull_none_smt>, |
| /* i2c7_sda_m2 */ |
| <4 RK_PA1 11 &pcfg_pull_none_smt>; |
| }; |
| |
| /omit-if-no-ref/ |
| i2c7m3_xfer: i2c7m3-xfer { |
| rockchip,pins = |
| /* i2c7_scl_m3 */ |
| <4 RK_PC0 11 &pcfg_pull_none_smt>, |
| /* i2c7_sda_m3 */ |
| <4 RK_PC1 11 &pcfg_pull_none_smt>; |
| }; |
| }; |
| |
| i2c8 { |
| /omit-if-no-ref/ |
| i2c8m0_xfer: i2c8m0-xfer { |
| rockchip,pins = |
| /* i2c8_scl_m0 */ |
| <2 RK_PA0 11 &pcfg_pull_none_smt>, |
| /* i2c8_sda_m0 */ |
| <2 RK_PA1 11 &pcfg_pull_none_smt>; |
| }; |
| |
| /omit-if-no-ref/ |
| i2c8m1_xfer: i2c8m1-xfer { |
| rockchip,pins = |
| /* i2c8_scl_m1 */ |
| <1 RK_PC6 10 &pcfg_pull_none_smt>, |
| /* i2c8_sda_m1 */ |
| <1 RK_PC7 10 &pcfg_pull_none_smt>; |
| }; |
| |
| /omit-if-no-ref/ |
| i2c8m2_xfer: i2c8m2-xfer { |
| rockchip,pins = |
| /* i2c8_scl_m2 */ |
| <2 RK_PB6 11 &pcfg_pull_none_smt>, |
| /* i2c8_sda_m2 */ |
| <2 RK_PB7 11 &pcfg_pull_none_smt>; |
| }; |
| |
| /omit-if-no-ref/ |
| i2c8m3_xfer: i2c8m3-xfer { |
| rockchip,pins = |
| /* i2c8_scl_m3 */ |
| <3 RK_PB3 11 &pcfg_pull_none_smt>, |
| /* i2c8_sda_m3 */ |
| <3 RK_PB2 11 &pcfg_pull_none_smt>; |
| }; |
| }; |
| |
| i2c9 { |
| /omit-if-no-ref/ |
| i2c9m0_xfer: i2c9m0-xfer { |
| rockchip,pins = |
| /* i2c9_scl_m0 */ |
| <1 RK_PA5 10 &pcfg_pull_none_smt>, |
| /* i2c9_sda_m0 */ |
| <1 RK_PA6 10 &pcfg_pull_none_smt>; |
| }; |
| |
| /omit-if-no-ref/ |
| i2c9m1_xfer: i2c9m1-xfer { |
| rockchip,pins = |
| /* i2c9_scl_m1 */ |
| <1 RK_PB5 10 &pcfg_pull_none_smt>, |
| /* i2c9_sda_m1 */ |
| <1 RK_PB4 10 &pcfg_pull_none_smt>; |
| }; |
| |
| /omit-if-no-ref/ |
| i2c9m2_xfer: i2c9m2-xfer { |
| rockchip,pins = |
| /* i2c9_scl_m2 */ |
| <2 RK_PD5 11 &pcfg_pull_none_smt>, |
| /* i2c9_sda_m2 */ |
| <2 RK_PD4 11 &pcfg_pull_none_smt>; |
| }; |
| |
| /omit-if-no-ref/ |
| i2c9m3_xfer: i2c9m3-xfer { |
| rockchip,pins = |
| /* i2c9_scl_m3 */ |
| <3 RK_PC2 11 &pcfg_pull_none_smt>, |
| /* i2c9_sda_m3 */ |
| <3 RK_PC3 11 &pcfg_pull_none_smt>; |
| }; |
| }; |
| |
| i3c0 { |
| /omit-if-no-ref/ |
| i3c0m0_xfer: i3c0m0-xfer { |
| rockchip,pins = |
| /* i3c0_scl_m0 */ |
| <0 RK_PC1 11 &pcfg_pull_none_smt>, |
| /* i3c0_sda_m0 */ |
| <0 RK_PC2 11 &pcfg_pull_none_smt>; |
| }; |
| |
| /omit-if-no-ref/ |
| i3c0m1_xfer: i3c0m1-xfer { |
| rockchip,pins = |
| /* i3c0_scl_m1 */ |
| <1 RK_PD2 10 &pcfg_pull_none_smt>, |
| /* i3c0_sda_m1 */ |
| <1 RK_PD3 10 &pcfg_pull_none_smt>; |
| }; |
| }; |
| |
| i3c1 { |
| /omit-if-no-ref/ |
| i3c1m0_xfer: i3c1m0-xfer { |
| rockchip,pins = |
| /* i3c1_scl_m0 */ |
| <2 RK_PD2 12 &pcfg_pull_none_smt>, |
| /* i3c1_sda_m0 */ |
| <2 RK_PD3 12 &pcfg_pull_none_smt>; |
| }; |
| |
| /omit-if-no-ref/ |
| i3c1m1_xfer: i3c1m1-xfer { |
| rockchip,pins = |
| /* i3c1_scl_m1 */ |
| <2 RK_PA2 14 &pcfg_pull_none_smt>, |
| /* i3c1_sda_m1 */ |
| <2 RK_PA3 14 &pcfg_pull_none_smt>; |
| }; |
| |
| /omit-if-no-ref/ |
| i3c1m2_xfer: i3c1m2-xfer { |
| rockchip,pins = |
| /* i3c1_scl_m2 */ |
| <3 RK_PD3 11 &pcfg_pull_none_smt>, |
| /* i3c1_sda_m2 */ |
| <3 RK_PD2 11 &pcfg_pull_none_smt>; |
| }; |
| }; |
| |
| i3c0_sda { |
| /omit-if-no-ref/ |
| i3c0_sdam0_pu: i3c0_sdam0-pu { |
| rockchip,pins = |
| /* i3c0_sda_pu_m0 */ |
| <0 RK_PC5 11 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| i3c0_sdam1_pu: i3c0_sdam1-pu { |
| rockchip,pins = |
| /* i3c0_sda_pu_m1 */ |
| <1 RK_PD1 10 &pcfg_pull_none>; |
| }; |
| }; |
| |
| i3c1_sda { |
| /omit-if-no-ref/ |
| i3c1_sdam0_pu: i3c1_sdam0-pu { |
| rockchip,pins = |
| /* i3c1_sda_pu_m0 */ |
| <2 RK_PD6 12 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| i3c1_sdam1_pu: i3c1_sdam1-pu { |
| rockchip,pins = |
| /* i3c1_sda_pu_m1 */ |
| <2 RK_PA5 14 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| i3c1_sdam2_pu: i3c1_sdam2-pu { |
| rockchip,pins = |
| /* i3c1_sda_pu_m2 */ |
| <3 RK_PD1 11 &pcfg_pull_none>; |
| }; |
| }; |
| |
| isp_flash { |
| /omit-if-no-ref/ |
| isp_flashm0_pins: isp_flashm0-pins { |
| rockchip,pins = |
| /* isp_flash_trigout_m0 */ |
| <2 RK_PD5 1 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| isp_flashm1_pins: isp_flashm1-pins { |
| rockchip,pins = |
| /* isp_flash_trigout_m1 */ |
| <4 RK_PC5 1 &pcfg_pull_none>; |
| }; |
| }; |
| |
| isp_prelight { |
| /omit-if-no-ref/ |
| isp_prelightm0_pins: isp_prelightm0-pins { |
| rockchip,pins = |
| /* isp_prelight_trig_m0 */ |
| <2 RK_PD4 1 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| isp_prelightm1_pins: isp_prelightm1-pins { |
| rockchip,pins = |
| /* isp_prelight_trig_m1 */ |
| <4 RK_PC4 1 &pcfg_pull_none>; |
| }; |
| }; |
| |
| jtag { |
| /omit-if-no-ref/ |
| jtagm0_pins: jtagm0-pins { |
| rockchip,pins = |
| /* jtag_tck_m0 */ |
| <2 RK_PA2 9 &pcfg_pull_none>, |
| /* jtag_tms_m0 */ |
| <2 RK_PA3 9 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| jtagm1_pins: jtagm1-pins { |
| rockchip,pins = |
| /* jtag_tck_m1 */ |
| <0 RK_PD4 10 &pcfg_pull_none>, |
| /* jtag_tms_m1 */ |
| <0 RK_PD5 10 &pcfg_pull_none>; |
| }; |
| }; |
| |
| mipi { |
| /omit-if-no-ref/ |
| mipim0_pins: mipim0-pins { |
| rockchip,pins = |
| /* mipi_te_m0 */ |
| <4 RK_PB2 11 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| mipim1_pins: mipim1-pins { |
| rockchip,pins = |
| /* mipi_te_m1 */ |
| <3 RK_PA2 12 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| mipim2_pins: mipim2-pins { |
| rockchip,pins = |
| /* mipi_te_m2 */ |
| <4 RK_PA0 12 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| mipim3_pins: mipim3-pins { |
| rockchip,pins = |
| /* mipi_te_m3 */ |
| <1 RK_PB3 11 &pcfg_pull_none>; |
| }; |
| }; |
| |
| npu { |
| /omit-if-no-ref/ |
| npu_pins: npu-pins { |
| rockchip,pins = |
| /* npu_avs */ |
| <0 RK_PB7 11 &pcfg_pull_none>; |
| }; |
| }; |
| |
| pcie0 { |
| /omit-if-no-ref/ |
| pcie0m0_pins: pcie0m0-pins { |
| rockchip,pins = |
| /* pcie21_port0_clkreq_m0 */ |
| <2 RK_PB2 11 &pcfg_pull_up>; |
| }; |
| |
| /omit-if-no-ref/ |
| pcie0m1_pins: pcie0m1-pins { |
| rockchip,pins = |
| /* pcie0_clkreq_m1 */ |
| <1 RK_PB6 12 &pcfg_pull_up>; |
| }; |
| |
| /omit-if-no-ref/ |
| pcie0m2_pins: pcie0m2-pins { |
| rockchip,pins = |
| /* pcie0_clkreq_m2 */ |
| <4 RK_PB5 12 &pcfg_pull_up>; |
| }; |
| |
| /omit-if-no-ref/ |
| pcie0m3_pins: pcie0m3-pins { |
| rockchip,pins = |
| /* pcie0_clkreq_m3 */ |
| <4 RK_PC6 9 &pcfg_pull_up>; |
| }; |
| |
| /omit-if-no-ref/ |
| pcie0_buttonrst: pcie21-port0-buttonrst { |
| rockchip,pins = |
| /* pcie0_buttonrst */ |
| <1 RK_PC4 12 &pcfg_pull_none>; |
| }; |
| }; |
| |
| pcie1 { |
| /omit-if-no-ref/ |
| pcie1m0_pins: pcie1m0-pins { |
| rockchip,pins = |
| /* pcie1_clkreq_m0 */ |
| <2 RK_PB3 11 &pcfg_pull_up>; |
| }; |
| |
| /omit-if-no-ref/ |
| pcie1m1_pins: pcie1m1-pins { |
| rockchip,pins = |
| /* pcie1_clkreq_m1 */ |
| <1 RK_PB4 12 &pcfg_pull_up>; |
| }; |
| |
| /omit-if-no-ref/ |
| pcie1m2_pins: pcie1m2-pins { |
| rockchip,pins = |
| /* pcie1_clkreq_m2 */ |
| <4 RK_PA5 12 &pcfg_pull_up>; |
| }; |
| |
| /omit-if-no-ref/ |
| pcie1m3_pins: pcie1m3-pins { |
| rockchip,pins = |
| /* pcie1_clkreq_m3 */ |
| <4 RK_PC1 10 &pcfg_pull_up>; |
| }; |
| |
| /omit-if-no-ref/ |
| pcie1_buttonrst: pcie21-port1-buttonrst { |
| rockchip,pins = |
| /* pcie1_buttonrst */ |
| <1 RK_PC5 12 &pcfg_pull_none>; |
| }; |
| }; |
| |
| pdm0 { |
| /omit-if-no-ref/ |
| pdm0m0_clk0: pdm0m0-clk0 { |
| rockchip,pins = |
| /* pdm0_clk0_m0 */ |
| <0 RK_PC4 3 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pdm0m0_clk1: pdm0m0-clk1 { |
| rockchip,pins = |
| /* pdm0_clk1_m0 */ |
| <0 RK_PC3 3 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pdm0m0_sdi0: pdm0m0-sdi0 { |
| rockchip,pins = |
| /* pdm0_sdi0_m0 */ |
| <0 RK_PD0 3 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pdm0m0_sdi1: pdm0m0-sdi1 { |
| rockchip,pins = |
| /* pdm0_sdi1_m0 */ |
| <0 RK_PD1 3 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pdm0m0_sdi2: pdm0m0-sdi2 { |
| rockchip,pins = |
| /* pdm0_sdi2_m0 */ |
| <0 RK_PD2 3 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pdm0m0_sdi3: pdm0m0-sdi3 { |
| rockchip,pins = |
| /* pdm0_sdi3_m0 */ |
| <0 RK_PD3 3 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pdm0m1_clk0: pdm0m1-clk0 { |
| rockchip,pins = |
| /* pdm0_clk0_m1 */ |
| <1 RK_PB1 5 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pdm0m1_clk1: pdm0m1-clk1 { |
| rockchip,pins = |
| /* pdm0_clk1_m1 */ |
| <1 RK_PA6 5 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pdm0m1_sdi0: pdm0m1-sdi0 { |
| rockchip,pins = |
| /* pdm0_sdi0_m1 */ |
| <1 RK_PB2 5 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pdm0m1_sdi1: pdm0m1-sdi1 { |
| rockchip,pins = |
| /* pdm0_sdi1_m1 */ |
| <1 RK_PA3 5 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pdm0m1_sdi2: pdm0m1-sdi2 { |
| rockchip,pins = |
| /* pdm0_sdi2_m1 */ |
| <1 RK_PA5 5 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pdm0m1_sdi3: pdm0m1-sdi3 { |
| rockchip,pins = |
| /* pdm0_sdi3_m1 */ |
| <1 RK_PA2 5 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pdm0m2_clk0: pdm0m2-clk0 { |
| rockchip,pins = |
| /* pdm0_clk0_m2 */ |
| <1 RK_PC1 5 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pdm0m2_clk1: pdm0m2-clk1 { |
| rockchip,pins = |
| /* pdm0_clk1_m2 */ |
| <1 RK_PD5 5 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pdm0m2_sdi0: pdm0m2-sdi0 { |
| rockchip,pins = |
| /* pdm0_sdi0_m2 */ |
| <1 RK_PC6 5 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pdm0m2_sdi1: pdm0m2-sdi1 { |
| rockchip,pins = |
| /* pdm0_sdi1_m2 */ |
| <1 RK_PC7 5 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pdm0m2_sdi2: pdm0m2-sdi2 { |
| rockchip,pins = |
| /* pdm0_sdi2_m2 */ |
| <1 RK_PC0 5 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pdm0m2_sdi3: pdm0m2-sdi3 { |
| rockchip,pins = |
| /* pdm0_sdi3_m2 */ |
| <1 RK_PD4 5 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pdm0m3_clk0: pdm0m3-clk0 { |
| rockchip,pins = |
| /* pdm0_clk0_m3 */ |
| <2 RK_PB5 5 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pdm0m3_clk1: pdm0m3-clk1 { |
| rockchip,pins = |
| /* pdm0_clk1_m3 */ |
| <2 RK_PB3 5 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pdm0m3_sdi0: pdm0m3-sdi0 { |
| rockchip,pins = |
| /* pdm0_sdi0_m3 */ |
| <2 RK_PB4 5 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pdm0m3_sdi1: pdm0m3-sdi1 { |
| rockchip,pins = |
| /* pdm0_sdi1_m3 */ |
| <2 RK_PB2 5 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pdm0m3_sdi2: pdm0m3-sdi2 { |
| rockchip,pins = |
| /* pdm0_sdi2_m3 */ |
| <2 RK_PB1 5 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pdm0m3_sdi3: pdm0m3-sdi3 { |
| rockchip,pins = |
| /* pdm0_sdi3_m3 */ |
| <2 RK_PB0 5 &pcfg_pull_none>; |
| }; |
| }; |
| |
| pdm1 { |
| /omit-if-no-ref/ |
| pdm1m0_clk0: pdm1m0-clk0 { |
| rockchip,pins = |
| /* pdm1_clk0_m0 */ |
| <2 RK_PC5 5 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pdm1m0_clk1: pdm1m0-clk1 { |
| rockchip,pins = |
| /* pdm1_clk1_m0 */ |
| <2 RK_PC1 5 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pdm1m0_sdi0: pdm1m0-sdi0 { |
| rockchip,pins = |
| /* pdm1_sdi0_m0 */ |
| <2 RK_PC4 5 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pdm1m0_sdi1: pdm1m0-sdi1 { |
| rockchip,pins = |
| /* pdm1_sdi1_m0 */ |
| <2 RK_PC0 5 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pdm1m0_sdi2: pdm1m0-sdi2 { |
| rockchip,pins = |
| /* pdm1_sdi2_m0 */ |
| <2 RK_PC2 5 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pdm1m0_sdi3: pdm1m0-sdi3 { |
| rockchip,pins = |
| /* pdm1_sdi3_m0 */ |
| <2 RK_PC3 5 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pdm1m1_clk0: pdm1m1-clk0 { |
| rockchip,pins = |
| /* pdm1_clk0_m1 */ |
| <4 RK_PA6 3 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pdm1m1_clk1: pdm1m1-clk1 { |
| rockchip,pins = |
| /* pdm1_clk1_m1 */ |
| <4 RK_PB0 3 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pdm1m1_sdi0: pdm1m1-sdi0 { |
| rockchip,pins = |
| /* pdm1_sdi0_m1 */ |
| <4 RK_PB3 3 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pdm1m1_sdi1: pdm1m1-sdi1 { |
| rockchip,pins = |
| /* pdm1_sdi1_m1 */ |
| <4 RK_PB2 3 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pdm1m1_sdi2: pdm1m1-sdi2 { |
| rockchip,pins = |
| /* pdm1_sdi2_m1 */ |
| <4 RK_PB1 3 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pdm1m1_sdi3: pdm1m1-sdi3 { |
| rockchip,pins = |
| /* pdm1_sdi3_m1 */ |
| <4 RK_PA4 3 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pdm1m2_clk0: pdm1m2-clk0 { |
| rockchip,pins = |
| /* pdm1_clk0_m2 */ |
| <3 RK_PB1 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pdm1m2_clk1: pdm1m2-clk1 { |
| rockchip,pins = |
| /* pdm1_clk1_m2 */ |
| <3 RK_PA7 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pdm1m2_sdi0: pdm1m2-sdi0 { |
| rockchip,pins = |
| /* pdm1_sdi0_m2 */ |
| <3 RK_PB3 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pdm1m2_sdi1: pdm1m2-sdi1 { |
| rockchip,pins = |
| /* pdm1_sdi1_m2 */ |
| <3 RK_PB2 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pdm1m2_sdi2: pdm1m2-sdi2 { |
| rockchip,pins = |
| /* pdm1_sdi2_m2 */ |
| <3 RK_PA6 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pdm1m2_sdi3: pdm1m2-sdi3 { |
| rockchip,pins = |
| /* pdm1_sdi3_m2 */ |
| <3 RK_PA5 4 &pcfg_pull_none>; |
| }; |
| }; |
| |
| pmu_debug_test { |
| /omit-if-no-ref/ |
| pmu_debug_test_pins: pmu_debug_test-pins { |
| rockchip,pins = |
| /* pmu_debug_test_out */ |
| <0 RK_PB0 2 &pcfg_pull_none>; |
| }; |
| }; |
| |
| pwm0 { |
| /omit-if-no-ref/ |
| pwm0m0_ch0: pwm0m0-ch0 { |
| rockchip,pins = |
| /* pwm0_ch0_m0 */ |
| <0 RK_PC4 12 &pcfg_pull_none_drv_level_2>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm0m0_ch1: pwm0m0-ch1 { |
| rockchip,pins = |
| /* pwm0_ch1_m0 */ |
| <0 RK_PC3 12 &pcfg_pull_none_drv_level_2>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm0m1_ch0: pwm0m1-ch0 { |
| rockchip,pins = |
| /* pwm0_ch0_m1 */ |
| <1 RK_PC0 13 &pcfg_pull_none_drv_level_2>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm0m1_ch1: pwm0m1-ch1 { |
| rockchip,pins = |
| /* pwm0_ch1_m1 */ |
| <4 RK_PC1 14 &pcfg_pull_none_drv_level_2>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm0m2_ch0: pwm0m2-ch0 { |
| rockchip,pins = |
| /* pwm0_ch0_m2 */ |
| <2 RK_PC3 13 &pcfg_pull_none_drv_level_2>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm0m2_ch1: pwm0m2-ch1 { |
| rockchip,pins = |
| /* pwm0_ch1_m2 */ |
| <2 RK_PC7 13 &pcfg_pull_none_drv_level_2>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm0m3_ch0: pwm0m3-ch0 { |
| rockchip,pins = |
| /* pwm0_ch0_m3 */ |
| <3 RK_PB0 12 &pcfg_pull_none_drv_level_2>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm0m3_ch1: pwm0m3-ch1 { |
| rockchip,pins = |
| /* pwm0_ch1_m3 */ |
| <3 RK_PB6 12 &pcfg_pull_none_drv_level_2>; |
| }; |
| }; |
| |
| pwm1 { |
| /omit-if-no-ref/ |
| pwm1m0_ch0: pwm1m0-ch0 { |
| rockchip,pins = |
| /* pwm1_ch0_m0 */ |
| <0 RK_PB4 12 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm1m0_ch1: pwm1m0-ch1 { |
| rockchip,pins = |
| /* pwm1_ch1_m0 */ |
| <0 RK_PB5 12 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm1m0_ch2: pwm1m0-ch2 { |
| rockchip,pins = |
| /* pwm1_ch2_m0 */ |
| <0 RK_PB6 12 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm1m0_ch3: pwm1m0-ch3 { |
| rockchip,pins = |
| /* pwm1_ch3_m0 */ |
| <0 RK_PC0 12 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm1m0_ch4: pwm1m0-ch4 { |
| rockchip,pins = |
| /* pwm1_ch4_m0 */ |
| <0 RK_PB7 12 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm1m0_ch5: pwm1m0-ch5 { |
| rockchip,pins = |
| /* pwm1_ch5_m0 */ |
| <0 RK_PD2 12 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm1m1_ch0: pwm1m1-ch0 { |
| rockchip,pins = |
| /* pwm1_ch0_m1 */ |
| <1 RK_PB4 13 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm1m1_ch1: pwm1m1-ch1 { |
| rockchip,pins = |
| /* pwm1_ch1_m1 */ |
| <1 RK_PB5 13 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm1m1_ch2: pwm1m1-ch2 { |
| rockchip,pins = |
| /* pwm1_ch2_m1 */ |
| <1 RK_PC2 13 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm1m1_ch3: pwm1m1-ch3 { |
| rockchip,pins = |
| /* pwm1_ch3_m1 */ |
| <1 RK_PD2 13 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm1m1_ch4: pwm1m1-ch4 { |
| rockchip,pins = |
| /* pwm1_ch4_m1 */ |
| <1 RK_PD3 13 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm1m1_ch5: pwm1m1-ch5 { |
| rockchip,pins = |
| /* pwm1_ch5_m1 */ |
| <4 RK_PC0 14 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm1m2_ch0: pwm1m2-ch0 { |
| rockchip,pins = |
| /* pwm1_ch0_m2 */ |
| <2 RK_PC0 13 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm1m2_ch1: pwm1m2-ch1 { |
| rockchip,pins = |
| /* pwm1_ch1_m2 */ |
| <2 RK_PC1 13 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm1m2_ch2: pwm1m2-ch2 { |
| rockchip,pins = |
| /* pwm1_ch2_m2 */ |
| <2 RK_PC2 13 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm1m2_ch3: pwm1m2-ch3 { |
| rockchip,pins = |
| /* pwm1_ch3_m2 */ |
| <2 RK_PC4 13 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm1m2_ch4: pwm1m2-ch4 { |
| rockchip,pins = |
| /* pwm1_ch4_m2 */ |
| <2 RK_PC5 13 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm1m2_ch5: pwm1m2-ch5 { |
| rockchip,pins = |
| /* pwm1_ch5_m2 */ |
| <2 RK_PC6 13 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm1m3_ch0: pwm1m3-ch0 { |
| rockchip,pins = |
| /* pwm1_ch0_m3 */ |
| <3 RK_PA4 12 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm1m3_ch1: pwm1m3-ch1 { |
| rockchip,pins = |
| /* pwm1_ch1_m3 */ |
| <3 RK_PA5 12 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm1m3_ch2: pwm1m3-ch2 { |
| rockchip,pins = |
| /* pwm1_ch2_m3 */ |
| <3 RK_PA6 12 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm1m3_ch3: pwm1m3-ch3 { |
| rockchip,pins = |
| /* pwm1_ch3_m3 */ |
| <3 RK_PB1 12 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm1m3_ch4: pwm1m3-ch4 { |
| rockchip,pins = |
| /* pwm1_ch4_m3 */ |
| <3 RK_PB4 12 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm1m3_ch5: pwm1m3-ch5 { |
| rockchip,pins = |
| /* pwm1_ch5_m3 */ |
| <3 RK_PB5 12 &pcfg_pull_none>; |
| }; |
| }; |
| |
| pwm2 { |
| /omit-if-no-ref/ |
| pwm2m0_ch0: pwm2m0-ch0 { |
| rockchip,pins = |
| /* pwm2_ch0_m0 */ |
| <0 RK_PD3 12 &pcfg_pull_none_drv_level_2>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm2m0_ch1: pwm2m0-ch1 { |
| rockchip,pins = |
| /* pwm2_ch1_m0 */ |
| <1 RK_PB3 12 &pcfg_pull_none_drv_level_2>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm2m0_ch2: pwm2m0-ch2 { |
| rockchip,pins = |
| /* pwm2_ch2_m0 */ |
| <2 RK_PA0 14 &pcfg_pull_none_drv_level_2>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm2m0_ch3: pwm2m0-ch3 { |
| rockchip,pins = |
| /* pwm2_ch3_m0 */ |
| <2 RK_PA1 14 &pcfg_pull_none_drv_level_2>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm2m0_ch4: pwm2m0-ch4 { |
| rockchip,pins = |
| /* pwm2_ch4_m0 */ |
| <2 RK_PA4 14 &pcfg_pull_none_drv_level_2>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm2m0_ch5: pwm2m0-ch5 { |
| rockchip,pins = |
| /* pwm2_ch5_m0 */ |
| <4 RK_PA2 13 &pcfg_pull_none_drv_level_2>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm2m0_ch6: pwm2m0-ch6 { |
| rockchip,pins = |
| /* pwm2_ch6_m0 */ |
| <4 RK_PA7 13 &pcfg_pull_none_drv_level_2>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm2m0_ch7: pwm2m0-ch7 { |
| rockchip,pins = |
| /* pwm2_ch7_m0 */ |
| <4 RK_PB3 13 &pcfg_pull_none_drv_level_2>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm2m1_ch0: pwm2m1-ch0 { |
| rockchip,pins = |
| /* pwm2_ch0_m1 */ |
| <4 RK_PC2 14 &pcfg_pull_none_drv_level_2>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm2m1_ch1: pwm2m1-ch1 { |
| rockchip,pins = |
| /* pwm2_ch1_m1 */ |
| <4 RK_PC3 14 &pcfg_pull_none_drv_level_2>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm2m1_ch2: pwm2m1-ch2 { |
| rockchip,pins = |
| /* pwm2_ch2_m1 */ |
| <4 RK_PC6 14 &pcfg_pull_none_drv_level_2>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm2m1_ch3: pwm2m1-ch3 { |
| rockchip,pins = |
| /* pwm2_ch3_m1 */ |
| <4 RK_PC7 14 &pcfg_pull_none_drv_level_2>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm2m1_ch4: pwm2m1-ch4 { |
| rockchip,pins = |
| /* pwm2_ch4_m1 */ |
| <4 RK_PA3 13 &pcfg_pull_none_drv_level_2>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm2m1_ch5: pwm2m1-ch5 { |
| rockchip,pins = |
| /* pwm2_ch5_m1 */ |
| <4 RK_PC5 14 &pcfg_pull_none_drv_level_2>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm2m1_ch6: pwm2m1-ch6 { |
| rockchip,pins = |
| /* pwm2_ch6_m1 */ |
| <4 RK_PC4 14 &pcfg_pull_none_drv_level_2>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm2m1_ch7: pwm2m1-ch7 { |
| rockchip,pins = |
| /* pwm2_ch7_m1 */ |
| <1 RK_PB1 12 &pcfg_pull_none_drv_level_2>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm2m2_ch0: pwm2m2-ch0 { |
| rockchip,pins = |
| /* pwm2_ch0_m2 */ |
| <2 RK_PD0 13 &pcfg_pull_none_drv_level_2>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm2m2_ch1: pwm2m2-ch1 { |
| rockchip,pins = |
| /* pwm2_ch1_m2 */ |
| <2 RK_PD1 13 &pcfg_pull_none_drv_level_2>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm2m2_ch2: pwm2m2-ch2 { |
| rockchip,pins = |
| /* pwm2_ch2_m2 */ |
| <2 RK_PD2 13 &pcfg_pull_none_drv_level_2>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm2m2_ch3: pwm2m2-ch3 { |
| rockchip,pins = |
| /* pwm2_ch3_m2 */ |
| <2 RK_PD3 13 &pcfg_pull_none_drv_level_2>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm2m2_ch4: pwm2m2-ch4 { |
| rockchip,pins = |
| /* pwm2_ch4_m2 */ |
| <2 RK_PD4 13 &pcfg_pull_none_drv_level_2>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm2m2_ch5: pwm2m2-ch5 { |
| rockchip,pins = |
| /* pwm2_ch5_m2 */ |
| <2 RK_PD5 13 &pcfg_pull_none_drv_level_2>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm2m2_ch6: pwm2m2-ch6 { |
| rockchip,pins = |
| /* pwm2_ch6_m2 */ |
| <2 RK_PD6 13 &pcfg_pull_none_drv_level_2>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm2m2_ch7: pwm2m2-ch7 { |
| rockchip,pins = |
| /* pwm2_ch7_m2 */ |
| <2 RK_PD7 13 &pcfg_pull_none_drv_level_2>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm2m3_ch0: pwm2m3-ch0 { |
| rockchip,pins = |
| /* pwm2_ch0_m3 */ |
| <3 RK_PC2 12 &pcfg_pull_none_drv_level_2>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm2m3_ch1: pwm2m3-ch1 { |
| rockchip,pins = |
| /* pwm2_ch1_m3 */ |
| <3 RK_PC3 12 &pcfg_pull_none_drv_level_2>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm2m3_ch2: pwm2m3-ch2 { |
| rockchip,pins = |
| /* pwm2_ch2_m3 */ |
| <3 RK_PC5 12 &pcfg_pull_none_drv_level_2>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm2m3_ch3: pwm2m3-ch3 { |
| rockchip,pins = |
| /* pwm2_ch3_m3 */ |
| <3 RK_PD0 12 &pcfg_pull_none_drv_level_2>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm2m3_ch4: pwm2m3-ch4 { |
| rockchip,pins = |
| /* pwm2_ch4_m3 */ |
| <3 RK_PD2 12 &pcfg_pull_none_drv_level_2>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm2m3_ch5: pwm2m3-ch5 { |
| rockchip,pins = |
| /* pwm2_ch5_m3 */ |
| <3 RK_PD3 12 &pcfg_pull_none_drv_level_2>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm2m3_ch6: pwm2m3-ch6 { |
| rockchip,pins = |
| /* pwm2_ch6_m3 */ |
| <3 RK_PD6 12 &pcfg_pull_none_drv_level_2>; |
| }; |
| |
| /omit-if-no-ref/ |
| pwm2m3_ch7: pwm2m3-ch7 { |
| rockchip,pins = |
| /* pwm2_ch7_m3 */ |
| <3 RK_PD7 12 &pcfg_pull_none_drv_level_2>; |
| }; |
| }; |
| |
| ref_clk0 { |
| /omit-if-no-ref/ |
| ref_clk0_clk0: ref_clk0-clk0 { |
| rockchip,pins = |
| /* ref_clk0_out */ |
| <0 RK_PA0 1 &pcfg_pull_none>; |
| }; |
| }; |
| |
| ref_clk1 { |
| /omit-if-no-ref/ |
| ref_clk1_clk1: ref_clk1-clk1 { |
| rockchip,pins = |
| /* ref_clk1_out */ |
| <0 RK_PB4 1 &pcfg_pull_none>; |
| }; |
| }; |
| |
| ref_clk2 { |
| /omit-if-no-ref/ |
| ref_clk2_clk2: ref_clk2-clk2 { |
| rockchip,pins = |
| /* ref_clk2_out */ |
| <0 RK_PB5 1 &pcfg_pull_none>; |
| }; |
| }; |
| |
| sai0 { |
| /omit-if-no-ref/ |
| sai0m0_lrck: sai0m0-lrck { |
| rockchip,pins = |
| /* sai0_lrck_m0 */ |
| <2 RK_PB7 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai0m0_mclk: sai0m0-mclk { |
| rockchip,pins = |
| /* sai0_mclk_m0 */ |
| <2 RK_PB5 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai0m0_sclk: sai0m0-sclk { |
| rockchip,pins = |
| /* sai0_sclk_m0 */ |
| <2 RK_PB6 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai0m0_sdi0: sai0m0-sdi0 { |
| rockchip,pins = |
| /* sai0_sdi0_m0 */ |
| <2 RK_PB0 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai0m0_sdi1: sai0m0-sdi1 { |
| rockchip,pins = |
| /* sai0_sdi1_m0 */ |
| <2 RK_PB1 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai0m0_sdi2: sai0m0-sdi2 { |
| rockchip,pins = |
| /* sai0_sdi2_m0 */ |
| <2 RK_PB2 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai0m0_sdi3: sai0m0-sdi3 { |
| rockchip,pins = |
| /* sai0_sdi3_m0 */ |
| <2 RK_PB4 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai0m0_sdo0: sai0m0-sdo0 { |
| rockchip,pins = |
| /* sai0_sdo0_m0 */ |
| <2 RK_PA6 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai0m0_sdo1: sai0m0-sdo1 { |
| rockchip,pins = |
| /* sai0_sdo1_m0 */ |
| <2 RK_PA7 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai0m0_sdo2: sai0m0-sdo2 { |
| rockchip,pins = |
| /* sai0_sdo2_m0 */ |
| <2 RK_PB3 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai0m0_sdo3: sai0m0-sdo3 { |
| rockchip,pins = |
| /* sai0_sdo3_m0 */ |
| <2 RK_PD7 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai0m1_lrck: sai0m1-lrck { |
| rockchip,pins = |
| /* sai0_lrck_m1 */ |
| <0 RK_PC7 1 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai0m1_mclk: sai0m1-mclk { |
| rockchip,pins = |
| /* sai0_mclk_m1 */ |
| <0 RK_PC4 1 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai0m1_sclk: sai0m1-sclk { |
| rockchip,pins = |
| /* sai0_sclk_m1 */ |
| <0 RK_PC6 1 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai0m1_sdi0: sai0m1-sdi0 { |
| rockchip,pins = |
| /* sai0_sdi0_m1 */ |
| <0 RK_PD0 1 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai0m1_sdi1: sai0m1-sdi1 { |
| rockchip,pins = |
| /* sai0_sdi1_m1 */ |
| <0 RK_PD1 1 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai0m1_sdi2: sai0m1-sdi2 { |
| rockchip,pins = |
| /* sai0_sdi2_m1 */ |
| <0 RK_PD2 1 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai0m1_sdi3: sai0m1-sdi3 { |
| rockchip,pins = |
| /* sai0_sdi3_m1 */ |
| <0 RK_PD3 1 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai0m1_sdo0: sai0m1-sdo0 { |
| rockchip,pins = |
| /* sai0_sdo0_m1 */ |
| <0 RK_PC5 1 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai0m1_sdo1: sai0m1-sdo1 { |
| rockchip,pins = |
| /* sai0_sdo1_m1 */ |
| <0 RK_PD3 2 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai0m1_sdo2: sai0m1-sdo2 { |
| rockchip,pins = |
| /* sai0_sdo2_m1 */ |
| <0 RK_PD2 2 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai0m1_sdo3: sai0m1-sdo3 { |
| rockchip,pins = |
| /* sai0_sdo3_m1 */ |
| <0 RK_PD1 2 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai0m2_lrck: sai0m2-lrck { |
| rockchip,pins = |
| /* sai0_lrck_m2 */ |
| <1 RK_PA1 3 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai0m2_mclk: sai0m2-mclk { |
| rockchip,pins = |
| /* sai0_mclk_m2 */ |
| <1 RK_PA4 3 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai0m2_sclk: sai0m2-sclk { |
| rockchip,pins = |
| /* sai0_sclk_m2 */ |
| <1 RK_PA0 3 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai0m2_sdi0: sai0m2-sdi0 { |
| rockchip,pins = |
| /* sai0_sdi0_m2 */ |
| <1 RK_PB2 3 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai0m2_sdi1: sai0m2-sdi1 { |
| rockchip,pins = |
| /* sai0_sdi1_m2 */ |
| <1 RK_PB1 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai0m2_sdi2: sai0m2-sdi2 { |
| rockchip,pins = |
| /* sai0_sdi2_m2 */ |
| <1 RK_PA3 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai0m2_sdi3: sai0m2-sdi3 { |
| rockchip,pins = |
| /* sai0_sdi3_m2 */ |
| <1 RK_PA2 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai0m2_sdo0: sai0m2-sdo0 { |
| rockchip,pins = |
| /* sai0_sdo0_m2 */ |
| <1 RK_PA7 3 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai0m2_sdo1: sai0m2-sdo1 { |
| rockchip,pins = |
| /* sai0_sdo1_m2 */ |
| <1 RK_PA2 3 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai0m2_sdo2: sai0m2-sdo2 { |
| rockchip,pins = |
| /* sai0_sdo2_m2 */ |
| <1 RK_PA3 3 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai0m2_sdo3: sai0m2-sdo3 { |
| rockchip,pins = |
| /* sai0_sdo3_m2 */ |
| <1 RK_PB1 3 &pcfg_pull_none>; |
| }; |
| }; |
| |
| sai1 { |
| /omit-if-no-ref/ |
| sai1m0_lrck: sai1m0-lrck { |
| rockchip,pins = |
| /* sai1_lrck_m0 */ |
| <4 RK_PA5 1 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai1m0_mclk: sai1m0-mclk { |
| rockchip,pins = |
| /* sai1_mclk_m0 */ |
| <4 RK_PA2 1 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai1m0_sclk: sai1m0-sclk { |
| rockchip,pins = |
| /* sai1_sclk_m0 */ |
| <4 RK_PA3 1 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai1m0_sdi0: sai1m0-sdi0 { |
| rockchip,pins = |
| /* sai1_sdi0_m0 */ |
| <4 RK_PB3 1 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai1m0_sdi1: sai1m0-sdi1 { |
| rockchip,pins = |
| /* sai1_sdi1_m0 */ |
| <4 RK_PB2 2 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai1m0_sdi2: sai1m0-sdi2 { |
| rockchip,pins = |
| /* sai1_sdi2_m0 */ |
| <4 RK_PB1 2 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai1m0_sdi3: sai1m0-sdi3 { |
| rockchip,pins = |
| /* sai1_sdi3_m0 */ |
| <4 RK_PB0 2 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai1m0_sdo0: sai1m0-sdo0 { |
| rockchip,pins = |
| /* sai1_sdo0_m0 */ |
| <4 RK_PA7 1 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai1m0_sdo1: sai1m0-sdo1 { |
| rockchip,pins = |
| /* sai1_sdo1_m0 */ |
| <4 RK_PB0 1 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai1m0_sdo2: sai1m0-sdo2 { |
| rockchip,pins = |
| /* sai1_sdo2_m0 */ |
| <4 RK_PB1 1 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai1m0_sdo3: sai1m0-sdo3 { |
| rockchip,pins = |
| /* sai1_sdo3_m0 */ |
| <4 RK_PB2 1 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai1m1_lrck: sai1m1-lrck { |
| rockchip,pins = |
| /* sai1_lrck_m1 */ |
| <3 RK_PC6 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai1m1_mclk: sai1m1-mclk { |
| rockchip,pins = |
| /* sai1_mclk_m1 */ |
| <3 RK_PD0 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai1m1_sclk: sai1m1-sclk { |
| rockchip,pins = |
| /* sai1_sclk_m1 */ |
| <3 RK_PC7 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai1m1_sdi0: sai1m1-sdi0 { |
| rockchip,pins = |
| /* sai1_sdi0_m1 */ |
| <3 RK_PB7 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai1m1_sdi1: sai1m1-sdi1 { |
| rockchip,pins = |
| /* sai1_sdi1_m1 */ |
| <3 RK_PD4 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai1m1_sdi2: sai1m1-sdi2 { |
| rockchip,pins = |
| /* sai1_sdi2_m1 */ |
| <3 RK_PD5 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai1m1_sdi3: sai1m1-sdi3 { |
| rockchip,pins = |
| /* sai1_sdi3_m1 */ |
| <3 RK_PD6 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai1m1_sdo0: sai1m1-sdo0 { |
| rockchip,pins = |
| /* sai1_sdo0_m1 */ |
| <3 RK_PC5 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai1m1_sdo1: sai1m1-sdo1 { |
| rockchip,pins = |
| /* sai1_sdo1_m1 */ |
| <3 RK_PC4 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai1m1_sdo2: sai1m1-sdo2 { |
| rockchip,pins = |
| /* sai1_sdo2_m1 */ |
| <3 RK_PC1 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai1m1_sdo3: sai1m1-sdo3 { |
| rockchip,pins = |
| /* sai1_sdo3_m1 */ |
| <3 RK_PC0 4 &pcfg_pull_none>; |
| }; |
| }; |
| |
| sai2 { |
| /omit-if-no-ref/ |
| sai2m0_lrck: sai2m0-lrck { |
| rockchip,pins = |
| /* sai2_lrck_m0 */ |
| <1 RK_PD2 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai2m0_mclk: sai2m0-mclk { |
| rockchip,pins = |
| /* sai2_mclk_m0 */ |
| <1 RK_PD4 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai2m0_sclk: sai2m0-sclk { |
| rockchip,pins = |
| /* sai2_sclk_m0 */ |
| <1 RK_PD1 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai2m0_sdi: sai2m0-sdi { |
| rockchip,pins = |
| /* sai2m0_sdi */ |
| <1 RK_PD3 4 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| sai2m0_sdo: sai2m0-sdo { |
| rockchip,pins = |
| /* sai2m0_sdo */ |
| <1 RK_PD0 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai2m1_lrck: sai2m1-lrck { |
| rockchip,pins = |
| /* sai2_lrck_m1 */ |
| <2 RK_PC3 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai2m1_mclk: sai2m1-mclk { |
| rockchip,pins = |
| /* sai2_mclk_m1 */ |
| <2 RK_PC1 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai2m1_sclk: sai2m1-sclk { |
| rockchip,pins = |
| /* sai2_sclk_m1 */ |
| <2 RK_PC2 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai2m1_sdi: sai2m1-sdi { |
| rockchip,pins = |
| /* sai2m1_sdi */ |
| <2 RK_PC5 4 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| sai2m1_sdo: sai2m1-sdo { |
| rockchip,pins = |
| /* sai2m1_sdo */ |
| <2 RK_PC4 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai2m2_lrck: sai2m2-lrck { |
| rockchip,pins = |
| /* sai2_lrck_m2 */ |
| <3 RK_PC3 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai2m2_mclk: sai2m2-mclk { |
| rockchip,pins = |
| /* sai2_mclk_m2 */ |
| <3 RK_PD1 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai2m2_sclk: sai2m2-sclk { |
| rockchip,pins = |
| /* sai2_sclk_m2 */ |
| <3 RK_PC2 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai2m2_sdi: sai2m2-sdi { |
| rockchip,pins = |
| /* sai2m2_sdi */ |
| <3 RK_PD2 4 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| sai2m2_sdo: sai2m2-sdo { |
| rockchip,pins = |
| /* sai2m2_sdo */ |
| <3 RK_PD3 4 &pcfg_pull_none>; |
| }; |
| }; |
| |
| sai3 { |
| /omit-if-no-ref/ |
| sai3m0_lrck: sai3m0-lrck { |
| rockchip,pins = |
| /* sai3_lrck_m0 */ |
| <1 RK_PA6 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai3m0_mclk: sai3m0-mclk { |
| rockchip,pins = |
| /* sai3_mclk_m0 */ |
| <1 RK_PA4 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai3m0_sclk: sai3m0-sclk { |
| rockchip,pins = |
| /* sai3_sclk_m0 */ |
| <1 RK_PA5 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai3m0_sdi: sai3m0-sdi { |
| rockchip,pins = |
| /* sai3m0_sdi */ |
| <1 RK_PA7 4 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| sai3m0_sdo: sai3m0-sdo { |
| rockchip,pins = |
| /* sai3m0_sdo */ |
| <1 RK_PB2 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai3m1_lrck: sai3m1-lrck { |
| rockchip,pins = |
| /* sai3_lrck_m1 */ |
| <1 RK_PB5 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai3m1_mclk: sai3m1-mclk { |
| rockchip,pins = |
| /* sai3_mclk_m1 */ |
| <1 RK_PC1 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai3m1_sclk: sai3m1-sclk { |
| rockchip,pins = |
| /* sai3_sclk_m1 */ |
| <1 RK_PB4 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai3m1_sdi: sai3m1-sdi { |
| rockchip,pins = |
| /* sai3m1_sdi */ |
| <1 RK_PB7 4 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| sai3m1_sdo: sai3m1-sdo { |
| rockchip,pins = |
| /* sai3m1_sdo */ |
| <1 RK_PB6 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai3m2_lrck: sai3m2-lrck { |
| rockchip,pins = |
| /* sai3_lrck_m2 */ |
| <3 RK_PA1 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai3m2_mclk: sai3m2-mclk { |
| rockchip,pins = |
| /* sai3_mclk_m2 */ |
| <2 RK_PD6 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai3m2_sclk: sai3m2-sclk { |
| rockchip,pins = |
| /* sai3_sclk_m2 */ |
| <3 RK_PA0 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai3m2_sdi: sai3m2-sdi { |
| rockchip,pins = |
| /* sai3m2_sdi */ |
| <3 RK_PA3 4 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| sai3m2_sdo: sai3m2-sdo { |
| rockchip,pins = |
| /* sai3m2_sdo */ |
| <3 RK_PA2 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai3m3_lrck: sai3m3-lrck { |
| rockchip,pins = |
| /* sai3_lrck_m3 */ |
| <2 RK_PA2 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai3m3_mclk: sai3m3-mclk { |
| rockchip,pins = |
| /* sai3_mclk_m3 */ |
| <2 RK_PA1 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai3m3_sclk: sai3m3-sclk { |
| rockchip,pins = |
| /* sai3_sclk_m3 */ |
| <2 RK_PA5 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai3m3_sdi: sai3m3-sdi { |
| rockchip,pins = |
| /* sai3m3_sdi */ |
| <2 RK_PA3 4 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| sai3m3_sdo: sai3m3-sdo { |
| rockchip,pins = |
| /* sai3m3_sdo */ |
| <2 RK_PA4 4 &pcfg_pull_none>; |
| }; |
| }; |
| |
| sai4 { |
| /omit-if-no-ref/ |
| sai4m0_lrck: sai4m0-lrck { |
| rockchip,pins = |
| /* sai4_lrck_m0 */ |
| <4 RK_PA6 2 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai4m0_mclk: sai4m0-mclk { |
| rockchip,pins = |
| /* sai4_mclk_m0 */ |
| <4 RK_PA2 2 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai4m0_sclk: sai4m0-sclk { |
| rockchip,pins = |
| /* sai4_sclk_m0 */ |
| <4 RK_PA4 2 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai4m0_sdi: sai4m0-sdi { |
| rockchip,pins = |
| /* sai4m0_sdi */ |
| <4 RK_PA7 2 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| sai4m0_sdo: sai4m0-sdo { |
| rockchip,pins = |
| /* sai4m0_sdo */ |
| <4 RK_PB3 2 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai4m1_lrck: sai4m1-lrck { |
| rockchip,pins = |
| /* sai4_lrck_m1 */ |
| <4 RK_PA0 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai4m1_mclk: sai4m1-mclk { |
| rockchip,pins = |
| /* sai4_mclk_m1 */ |
| <3 RK_PB0 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai4m1_sclk: sai4m1-sclk { |
| rockchip,pins = |
| /* sai4_sclk_m1 */ |
| <3 RK_PD7 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai4m1_sdi: sai4m1-sdi { |
| rockchip,pins = |
| /* sai4m1_sdi */ |
| <3 RK_PA4 4 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| sai4m1_sdo: sai4m1-sdo { |
| rockchip,pins = |
| /* sai4m1_sdo */ |
| <4 RK_PA1 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai4m2_lrck: sai4m2-lrck { |
| rockchip,pins = |
| /* sai4_lrck_m2 */ |
| <4 RK_PC4 2 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai4m2_mclk: sai4m2-mclk { |
| rockchip,pins = |
| /* sai4_mclk_m2 */ |
| <4 RK_PC0 2 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai4m2_sclk: sai4m2-sclk { |
| rockchip,pins = |
| /* sai4_sclk_m2 */ |
| <4 RK_PC7 2 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai4m2_sdi: sai4m2-sdi { |
| rockchip,pins = |
| /* sai4m2_sdi */ |
| <4 RK_PC6 2 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| sai4m2_sdo: sai4m2-sdo { |
| rockchip,pins = |
| /* sai4m2_sdo */ |
| <4 RK_PC5 2 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai4m3_lrck: sai4m3-lrck { |
| rockchip,pins = |
| /* sai4_lrck_m3 */ |
| <2 RK_PC7 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai4m3_mclk: sai4m3-mclk { |
| rockchip,pins = |
| /* sai4_mclk_m3 */ |
| <2 RK_PD2 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai4m3_sclk: sai4m3-sclk { |
| rockchip,pins = |
| /* sai4_sclk_m3 */ |
| <2 RK_PC6 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sai4m3_sdi: sai4m3-sdi { |
| rockchip,pins = |
| /* sai4m3_sdi */ |
| <2 RK_PD0 4 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| sai4m3_sdo: sai4m3-sdo { |
| rockchip,pins = |
| /* sai4m3_sdo */ |
| <2 RK_PD1 4 &pcfg_pull_none>; |
| }; |
| }; |
| |
| sata30 { |
| /omit-if-no-ref/ |
| sata30_sata: sata30-sata { |
| rockchip,pins = |
| /* sata30_cpdet */ |
| <1 RK_PC7 12 &pcfg_pull_none>, |
| /* sata30_cppod */ |
| <1 RK_PC6 12 &pcfg_pull_none>, |
| /* sata30_mpswit */ |
| <1 RK_PD5 12 &pcfg_pull_none>; |
| }; |
| }; |
| |
| sata30_port0 { |
| /omit-if-no-ref/ |
| sata30_port0m0_port0: sata30_port0m0-port0 { |
| rockchip,pins = |
| /* sata30_port0_actled_m0 */ |
| <2 RK_PB4 12 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sata30_port0m1_port0: sata30_port0m1-port0 { |
| rockchip,pins = |
| /* sata30_port0_actled_m1 */ |
| <4 RK_PC6 10 &pcfg_pull_none>; |
| }; |
| }; |
| |
| sata30_port1 { |
| /omit-if-no-ref/ |
| sata30_port1m0_port1: sata30_port1m0-port1 { |
| rockchip,pins = |
| /* sata30_port1_actled_m0 */ |
| <2 RK_PB5 12 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sata30_port1m1_port1: sata30_port1m1-port1 { |
| rockchip,pins = |
| /* sata30_port1_actled_m1 */ |
| <4 RK_PC5 10 &pcfg_pull_none>; |
| }; |
| }; |
| |
| sdmmc0 { |
| /omit-if-no-ref/ |
| sdmmc0_bus4: sdmmc0-bus4 { |
| rockchip,pins = |
| /* sdmmc0_d0 */ |
| <2 RK_PA0 1 &pcfg_pull_up_drv_level_3>, |
| /* sdmmc0_d1 */ |
| <2 RK_PA1 1 &pcfg_pull_up_drv_level_3>, |
| /* sdmmc0_d2 */ |
| <2 RK_PA2 1 &pcfg_pull_up_drv_level_3>, |
| /* sdmmc0_d3 */ |
| <2 RK_PA3 1 &pcfg_pull_up_drv_level_3>; |
| }; |
| |
| /omit-if-no-ref/ |
| sdmmc0_clk: sdmmc0-clk { |
| rockchip,pins = |
| /* sdmmc0_clk */ |
| <2 RK_PA5 1 &pcfg_pull_up_drv_level_3>; |
| }; |
| |
| /omit-if-no-ref/ |
| sdmmc0_cmd: sdmmc0-cmd { |
| rockchip,pins = |
| /* sdmmc0_cmd */ |
| <2 RK_PA4 1 &pcfg_pull_up_drv_level_3>; |
| }; |
| |
| /omit-if-no-ref/ |
| sdmmc0_det: sdmmc0-det { |
| rockchip,pins = |
| /* sdmmc0_detn */ |
| <0 RK_PA7 1 &pcfg_pull_up>; |
| }; |
| |
| /omit-if-no-ref/ |
| sdmmc0_pwren: sdmmc0-pwren { |
| rockchip,pins = |
| /* sdmmc0_pwren */ |
| <0 RK_PB6 1 &pcfg_pull_none>; |
| }; |
| }; |
| |
| sdmmc1 { |
| /omit-if-no-ref/ |
| sdmmc1m0_bus4: sdmmc1m0-bus4 { |
| rockchip,pins = |
| /* sdmmc1_d0_m0 */ |
| <1 RK_PB4 2 &pcfg_pull_up_drv_level_2>, |
| /* sdmmc1_d1_m0 */ |
| <1 RK_PB5 2 &pcfg_pull_up_drv_level_2>, |
| /* sdmmc1_d2_m0 */ |
| <1 RK_PB6 2 &pcfg_pull_up_drv_level_2>, |
| /* sdmmc1_d3_m0 */ |
| <1 RK_PB7 2 &pcfg_pull_up_drv_level_2>; |
| }; |
| |
| /omit-if-no-ref/ |
| sdmmc1m0_clk: sdmmc1m0-clk { |
| rockchip,pins = |
| /* sdmmc1_clk_m0 */ |
| <1 RK_PC1 2 &pcfg_pull_up_drv_level_2>; |
| }; |
| |
| /omit-if-no-ref/ |
| sdmmc1m0_cmd: sdmmc1m0-cmd { |
| rockchip,pins = |
| /* sdmmc1_cmd_m0 */ |
| <1 RK_PC0 2 &pcfg_pull_up_drv_level_2>; |
| }; |
| |
| /omit-if-no-ref/ |
| sdmmc1m0_det: sdmmc1m0-det { |
| rockchip,pins = |
| /* sdmmc1_detn_m0 */ |
| <1 RK_PC3 2 &pcfg_pull_up>; |
| }; |
| |
| /omit-if-no-ref/ |
| sdmmc1m0_pwren: sdmmc1m0-pwren { |
| rockchip,pins = |
| /* sdmmc1m0_pwren */ |
| <1 RK_PC2 2 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sdmmc1m1_bus4: sdmmc1m1-bus4 { |
| rockchip,pins = |
| /* sdmmc1_d0_m1 */ |
| <2 RK_PA6 2 &pcfg_pull_up_drv_level_2>, |
| /* sdmmc1_d1_m1 */ |
| <2 RK_PA7 2 &pcfg_pull_up_drv_level_2>, |
| /* sdmmc1_d2_m1 */ |
| <2 RK_PB0 2 &pcfg_pull_up_drv_level_2>, |
| /* sdmmc1_d3_m1 */ |
| <2 RK_PB1 2 &pcfg_pull_up_drv_level_2>; |
| }; |
| |
| /omit-if-no-ref/ |
| sdmmc1m1_clk: sdmmc1m1-clk { |
| rockchip,pins = |
| /* sdmmc1_clk_m1 */ |
| <2 RK_PB3 2 &pcfg_pull_up_drv_level_2>; |
| }; |
| |
| /omit-if-no-ref/ |
| sdmmc1m1_cmd: sdmmc1m1-cmd { |
| rockchip,pins = |
| /* sdmmc1_cmd_m1 */ |
| <2 RK_PB2 2 &pcfg_pull_up_drv_level_2>; |
| }; |
| |
| /omit-if-no-ref/ |
| sdmmc1m1_det: sdmmc1m1-det { |
| rockchip,pins = |
| /* sdmmc1_detn_m1 */ |
| <2 RK_PB5 2 &pcfg_pull_up>; |
| }; |
| |
| /omit-if-no-ref/ |
| sdmmc1m1_pwren: sdmmc1m1-pwren { |
| rockchip,pins = |
| /* sdmmc1m1_pwren */ |
| <2 RK_PB4 2 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| sdmmc1m2_det: sdmmc1m2-det { |
| rockchip,pins = |
| /* sdmmc1_detn_m2 */ |
| <0 RK_PB6 2 &pcfg_pull_up>; |
| }; |
| }; |
| |
| sdmmc0_testclk { |
| /omit-if-no-ref/ |
| sdmmc0_testclk_test: sdmmc0_testclk-test { |
| rockchip,pins = |
| /* sdmmc0_testclk_out */ |
| <1 RK_PC4 6 &pcfg_pull_none>; |
| }; |
| }; |
| |
| sdmmc0_testdata { |
| /omit-if-no-ref/ |
| sdmmc0_testdata_test: sdmmc0_testdata-test { |
| rockchip,pins = |
| /* sdmmc0_testdata_out */ |
| <1 RK_PC5 6 &pcfg_pull_none>; |
| }; |
| }; |
| |
| sdmmc1_testclk { |
| /omit-if-no-ref/ |
| sdmmc1_testclkm0_test: sdmmc1_testclkm0-test { |
| rockchip,pins = |
| /* sdmmc1_testclk_out_m0 */ |
| <1 RK_PC4 5 &pcfg_pull_none>; |
| }; |
| }; |
| |
| sdmmc1_testdata { |
| /omit-if-no-ref/ |
| sdmmc1_testdatam0_test: sdmmc1_testdatam0-test { |
| rockchip,pins = |
| /* sdmmc1_testdata_out_m0 */ |
| <1 RK_PC5 5 &pcfg_pull_none>; |
| }; |
| }; |
| |
| spdif { |
| /omit-if-no-ref/ |
| spdifm0_rx0: spdifm0-rx0 { |
| rockchip,pins = |
| /* spdif_rx0_m0 */ |
| <4 RK_PB4 1 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| spdifm0_rx1: spdifm0-rx1 { |
| rockchip,pins = |
| /* spdif_rx1_m0 */ |
| <3 RK_PB4 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| spdifm0_tx0: spdifm0-tx0 { |
| rockchip,pins = |
| /* spdif_tx0_m0 */ |
| <4 RK_PB5 1 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| spdifm0_tx1: spdifm0-tx1 { |
| rockchip,pins = |
| /* spdif_tx1_m0 */ |
| <3 RK_PB5 4 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| spdifm1_rx0: spdifm1-rx0 { |
| rockchip,pins = |
| /* spdif_rx0_m1 */ |
| <4 RK_PA0 2 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| spdifm1_rx1: spdifm1-rx1 { |
| rockchip,pins = |
| /* spdif_rx1_m1 */ |
| <3 RK_PA2 5 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| spdifm1_tx0: spdifm1-tx0 { |
| rockchip,pins = |
| /* spdif_tx0_m1 */ |
| <4 RK_PA1 2 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| spdifm1_tx1: spdifm1-tx1 { |
| rockchip,pins = |
| /* spdif_tx1_m1 */ |
| <3 RK_PA3 5 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| spdifm2_rx0: spdifm2-rx0 { |
| rockchip,pins = |
| /* spdif_rx0_m2 */ |
| <2 RK_PD6 5 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| spdifm2_rx1: spdifm2-rx1 { |
| rockchip,pins = |
| /* spdif_rx1_m2 */ |
| <1 RK_PD4 6 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| spdifm2_tx0: spdifm2-tx0 { |
| rockchip,pins = |
| /* spdif_tx0_m2 */ |
| <2 RK_PD7 5 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| spdifm2_tx1: spdifm2-tx1 { |
| rockchip,pins = |
| /* spdif_tx1_m2 */ |
| <1 RK_PD5 6 &pcfg_pull_none>; |
| }; |
| }; |
| |
| spi0 { |
| /omit-if-no-ref/ |
| spi0m0_pins: spi0m0-pins { |
| rockchip,pins = |
| /* spi0_clk_m0 */ |
| <0 RK_PC7 11 &pcfg_pull_none>, |
| /* spi0_miso_m0 */ |
| <0 RK_PD1 11 &pcfg_pull_none>, |
| /* spi0_mosi_m0 */ |
| <0 RK_PD0 11 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| spi0m0_csn0: spi0m0-csn0 { |
| rockchip,pins = |
| /* spi0m0_csn0 */ |
| <0 RK_PC6 11 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| spi0m0_csn1: spi0m0-csn1 { |
| rockchip,pins = |
| /* spi0m0_csn1 */ |
| <0 RK_PC3 11 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| spi0m1_pins: spi0m1-pins { |
| rockchip,pins = |
| /* spi0_clk_m1 */ |
| <2 RK_PA5 12 &pcfg_pull_none>, |
| /* spi0_miso_m1 */ |
| <2 RK_PA1 12 &pcfg_pull_none>, |
| /* spi0_mosi_m1 */ |
| <2 RK_PA0 12 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| spi0m1_csn0: spi0m1-csn0 { |
| rockchip,pins = |
| /* spi0m1_csn0 */ |
| <2 RK_PA4 12 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| spi0m1_csn1: spi0m1-csn1 { |
| rockchip,pins = |
| /* spi0m1_csn1 */ |
| <2 RK_PA2 12 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| spi0m2_pins: spi0m2-pins { |
| rockchip,pins = |
| /* spi0_clk_m2 */ |
| <1 RK_PA7 9 &pcfg_pull_none>, |
| /* spi0_miso_m2 */ |
| <1 RK_PA6 9 &pcfg_pull_none>, |
| /* spi0_mosi_m2 */ |
| <1 RK_PA5 9 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| spi0m2_csn0: spi0m2-csn0 { |
| rockchip,pins = |
| /* spi0m2_csn0 */ |
| <1 RK_PA4 9 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| spi0m2_csn1: spi0m2-csn1 { |
| rockchip,pins = |
| /* spi0m2_csn1 */ |
| <1 RK_PB2 9 &pcfg_pull_none>; |
| }; |
| }; |
| |
| spi1 { |
| /omit-if-no-ref/ |
| spi1m0_pins: spi1m0-pins { |
| rockchip,pins = |
| /* spi1_clk_m0 */ |
| <1 RK_PB4 11 &pcfg_pull_none>, |
| /* spi1_miso_m0 */ |
| <1 RK_PB6 11 &pcfg_pull_none>, |
| /* spi1_mosi_m0 */ |
| <1 RK_PB5 11 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| spi1m0_csn0: spi1m0-csn0 { |
| rockchip,pins = |
| /* spi1m0_csn0 */ |
| <1 RK_PB7 11 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| spi1m0_csn1: spi1m0-csn1 { |
| rockchip,pins = |
| /* spi1m0_csn1 */ |
| <1 RK_PC0 11 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| spi1m1_pins: spi1m1-pins { |
| rockchip,pins = |
| /* spi1_clk_m1 */ |
| <2 RK_PC5 10 &pcfg_pull_none>, |
| /* spi1_miso_m1 */ |
| <2 RK_PC3 10 &pcfg_pull_none>, |
| /* spi1_mosi_m1 */ |
| <2 RK_PC2 10 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| spi1m1_csn0: spi1m1-csn0 { |
| rockchip,pins = |
| /* spi1m1_csn0 */ |
| <2 RK_PC4 10 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| spi1m1_csn1: spi1m1-csn1 { |
| rockchip,pins = |
| /* spi1m1_csn1 */ |
| <2 RK_PC1 10 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| spi1m2_pins: spi1m2-pins { |
| rockchip,pins = |
| /* spi1_clk_m2 */ |
| <3 RK_PC7 10 &pcfg_pull_none>, |
| /* spi1_miso_m2 */ |
| <3 RK_PC5 10 &pcfg_pull_none>, |
| /* spi1_mosi_m2 */ |
| <3 RK_PC6 10 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| spi1m2_csn0: spi1m2-csn0 { |
| rockchip,pins = |
| /* spi1m2_csn0 */ |
| <3 RK_PD0 10 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| spi1m2_csn1: spi1m2-csn1 { |
| rockchip,pins = |
| /* spi1m2_csn1 */ |
| <4 RK_PA0 10 &pcfg_pull_none>; |
| }; |
| }; |
| |
| spi2 { |
| /omit-if-no-ref/ |
| spi2m0_pins: spi2m0-pins { |
| rockchip,pins = |
| /* spi2_clk_m0 */ |
| <0 RK_PB2 9 &pcfg_pull_none>, |
| /* spi2_miso_m0 */ |
| <0 RK_PB1 9 &pcfg_pull_none>, |
| /* spi2_mosi_m0 */ |
| <0 RK_PB3 9 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| spi2m0_csn0: spi2m0-csn0 { |
| rockchip,pins = |
| /* spi2m0_csn0 */ |
| <0 RK_PB0 9 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| spi2m0_csn1: spi2m0-csn1 { |
| rockchip,pins = |
| /* spi2m0_csn1 */ |
| <0 RK_PA7 9 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| spi2m1_pins: spi2m1-pins { |
| rockchip,pins = |
| /* spi2_clk_m1 */ |
| <1 RK_PD5 11 &pcfg_pull_none>, |
| /* spi2_miso_m1 */ |
| <1 RK_PC5 11 &pcfg_pull_none>, |
| /* spi2_mosi_m1 */ |
| <1 RK_PC4 11 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| spi2m1_csn0: spi2m1-csn0 { |
| rockchip,pins = |
| /* spi2m1_csn0 */ |
| <1 RK_PC3 11 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| spi2m1_csn1: spi2m1-csn1 { |
| rockchip,pins = |
| /* spi2m1_csn1 */ |
| <1 RK_PC2 11 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| spi2m2_pins: spi2m2-pins { |
| rockchip,pins = |
| /* spi2_clk_m2 */ |
| <3 RK_PA4 10 &pcfg_pull_none>, |
| /* spi2_miso_m2 */ |
| <3 RK_PC1 10 &pcfg_pull_none>, |
| /* spi2_mosi_m2 */ |
| <3 RK_PB0 10 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| spi2m2_csn0: spi2m2-csn0 { |
| rockchip,pins = |
| /* spi2m2_csn0 */ |
| <3 RK_PC4 10 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| spi2m2_csn1: spi2m2-csn1 { |
| rockchip,pins = |
| /* spi2m2_csn1 */ |
| <3 RK_PA5 10 &pcfg_pull_none>; |
| }; |
| }; |
| |
| spi3 { |
| /omit-if-no-ref/ |
| spi3m0_pins: spi3m0-pins { |
| rockchip,pins = |
| /* spi3_clk_m0 */ |
| <3 RK_PA0 10 &pcfg_pull_none>, |
| /* spi3_miso_m0 */ |
| <3 RK_PA2 10 &pcfg_pull_none>, |
| /* spi3_mosi_m0 */ |
| <3 RK_PA1 10 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| spi3m0_csn0: spi3m0-csn0 { |
| rockchip,pins = |
| /* spi3m0_csn0 */ |
| <3 RK_PA3 10 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| spi3m0_csn1: spi3m0-csn1 { |
| rockchip,pins = |
| /* spi3m0_csn1 */ |
| <2 RK_PD7 10 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| spi3m1_pins: spi3m1-pins { |
| rockchip,pins = |
| /* spi3_clk_m1 */ |
| <3 RK_PD4 10 &pcfg_pull_none>, |
| /* spi3_miso_m1 */ |
| <3 RK_PD5 10 &pcfg_pull_none>, |
| /* spi3_mosi_m1 */ |
| <3 RK_PD6 10 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| spi3m1_csn0: spi3m1-csn0 { |
| rockchip,pins = |
| /* spi3m1_csn0 */ |
| <3 RK_PB6 10 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| spi3m1_csn1: spi3m1-csn1 { |
| rockchip,pins = |
| /* spi3m1_csn1 */ |
| <3 RK_PD7 10 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| spi3m2_pins: spi3m2-pins { |
| rockchip,pins = |
| /* spi3_clk_m2 */ |
| <4 RK_PA7 9 &pcfg_pull_none>, |
| /* spi3_miso_m2 */ |
| <4 RK_PA6 9 &pcfg_pull_none>, |
| /* spi3_mosi_m2 */ |
| <4 RK_PA4 9 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| spi3m2_csn0: spi3m2-csn0 { |
| rockchip,pins = |
| /* spi3m2_csn0 */ |
| <4 RK_PA3 9 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| spi3m2_csn1: spi3m2-csn1 { |
| rockchip,pins = |
| /* spi3m2_csn1 */ |
| <4 RK_PB3 10 &pcfg_pull_none>; |
| }; |
| }; |
| |
| spi4 { |
| /omit-if-no-ref/ |
| spi4m0_pins: spi4m0-pins { |
| rockchip,pins = |
| /* spi4_clk_m0 */ |
| <4 RK_PC7 12 &pcfg_pull_none>, |
| /* spi4_miso_m0 */ |
| <4 RK_PC6 12 &pcfg_pull_none>, |
| /* spi4_mosi_m0 */ |
| <4 RK_PC5 12 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| spi4m0_csn0: spi4m0-csn0 { |
| rockchip,pins = |
| /* spi4m0_csn0 */ |
| <4 RK_PC4 12 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| spi4m0_csn1: spi4m0-csn1 { |
| rockchip,pins = |
| /* spi4m0_csn1 */ |
| <4 RK_PC0 12 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| spi4m1_pins: spi4m1-pins { |
| rockchip,pins = |
| /* spi4_clk_m1 */ |
| <3 RK_PD1 10 &pcfg_pull_none>, |
| /* spi4_miso_m1 */ |
| <3 RK_PC2 10 &pcfg_pull_none>, |
| /* spi4_mosi_m1 */ |
| <3 RK_PC3 10 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| spi4m1_csn0: spi4m1-csn0 { |
| rockchip,pins = |
| /* spi4m1_csn0 */ |
| <3 RK_PB1 10 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| spi4m1_csn1: spi4m1-csn1 { |
| rockchip,pins = |
| /* spi4m1_csn1 */ |
| <3 RK_PD2 10 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| spi4m2_pins: spi4m2-pins { |
| rockchip,pins = |
| /* spi4_clk_m2 */ |
| <4 RK_PB0 9 &pcfg_pull_none>, |
| /* spi4_miso_m2 */ |
| <4 RK_PB2 9 &pcfg_pull_none>, |
| /* spi4_mosi_m2 */ |
| <4 RK_PB1 9 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| spi4m2_csn0: spi4m2-csn0 { |
| rockchip,pins = |
| /* spi4m2_csn0 */ |
| <4 RK_PB3 9 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| spi4m2_csn1: spi4m2-csn1 { |
| rockchip,pins = |
| /* spi4m2_csn1 */ |
| <4 RK_PA5 9 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| spi4m3_pins: spi4m3-pins { |
| rockchip,pins = |
| /* spi4_clk_m3 */ |
| <2 RK_PB3 10 &pcfg_pull_none>, |
| /* spi4_miso_m3 */ |
| <2 RK_PB5 10 &pcfg_pull_none>, |
| /* spi4_mosi_m3 */ |
| <2 RK_PB4 10 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| spi4m3_csn0: spi4m3-csn0 { |
| rockchip,pins = |
| /* spi4m3_csn0 */ |
| <2 RK_PB2 10 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| spi4m3_csn1: spi4m3-csn1 { |
| rockchip,pins = |
| /* spi4m3_csn1 */ |
| <2 RK_PA6 10 &pcfg_pull_none>; |
| }; |
| }; |
| |
| test_clk { |
| /omit-if-no-ref/ |
| test_clk_pins: test_clk-pins { |
| rockchip,pins = |
| /* test_clk_out */ |
| <2 RK_PA5 5 &pcfg_pull_none>; |
| }; |
| }; |
| |
| tsadc { |
| /omit-if-no-ref/ |
| tsadcm0_pins: tsadcm0-pins { |
| rockchip,pins = |
| /* tsadc_ctrl_m0 */ |
| <0 RK_PA1 9 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| tsadcm1_pins: tsadcm1-pins { |
| rockchip,pins = |
| /* tsadc_ctrl_m1 */ |
| <0 RK_PA3 10 &pcfg_pull_none>; |
| }; |
| }; |
| |
| tsadc_ctrl { |
| /omit-if-no-ref/ |
| tsadc_ctrl_pins: tsadc_ctrl-pins { |
| rockchip,pins = |
| /* tsadc_ctrl_org */ |
| <0 RK_PA1 10 &pcfg_pull_none>; |
| }; |
| }; |
| |
| uart0 { |
| /omit-if-no-ref/ |
| uart0m0_xfer: uart0m0-xfer { |
| rockchip,pins = |
| /* uart0_rx_m0 */ |
| <0 RK_PD5 9 &pcfg_pull_up>, |
| /* uart0_tx_m0 */ |
| <0 RK_PD4 9 &pcfg_pull_up>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart0m1_xfer: uart0m1-xfer { |
| rockchip,pins = |
| /* uart0_rx_m1 */ |
| <2 RK_PA0 9 &pcfg_pull_up>, |
| /* uart0_tx_m1 */ |
| <2 RK_PA1 9 &pcfg_pull_up>; |
| }; |
| }; |
| |
| uart1 { |
| /omit-if-no-ref/ |
| uart1m0_xfer: uart1m0-xfer { |
| rockchip,pins = |
| /* uart1_rx_m0 */ |
| <0 RK_PC0 10 &pcfg_pull_up>, |
| /* uart1_tx_m0 */ |
| <0 RK_PB7 10 &pcfg_pull_up>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart1m0_ctsn: uart1m0-ctsn { |
| rockchip,pins = |
| /* uart1m0_ctsn */ |
| <0 RK_PD2 13 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| uart1m0_rtsn: uart1m0-rtsn { |
| rockchip,pins = |
| /* uart1m0_rtsn */ |
| <0 RK_PD3 13 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart1m1_xfer: uart1m1-xfer { |
| rockchip,pins = |
| /* uart1_rx_m1 */ |
| <2 RK_PB1 9 &pcfg_pull_up>, |
| /* uart1_tx_m1 */ |
| <2 RK_PB0 9 &pcfg_pull_up>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart1m1_ctsn: uart1m1-ctsn { |
| rockchip,pins = |
| /* uart1m1_ctsn */ |
| <2 RK_PB2 9 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| uart1m1_rtsn: uart1m1-rtsn { |
| rockchip,pins = |
| /* uart1m1_rtsn */ |
| <2 RK_PB3 9 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart1m2_xfer: uart1m2-xfer { |
| rockchip,pins = |
| /* uart1_rx_m2 */ |
| <3 RK_PA6 9 &pcfg_pull_up>, |
| /* uart1_tx_m2 */ |
| <3 RK_PA7 9 &pcfg_pull_up>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart1m2_ctsn: uart1m2-ctsn { |
| rockchip,pins = |
| /* uart1m2_ctsn */ |
| <3 RK_PA4 9 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| uart1m2_rtsn: uart1m2-rtsn { |
| rockchip,pins = |
| /* uart1m2_rtsn */ |
| <3 RK_PA5 9 &pcfg_pull_none>; |
| }; |
| }; |
| |
| uart2 { |
| /omit-if-no-ref/ |
| uart2m0_xfer: uart2m0-xfer { |
| rockchip,pins = |
| /* uart2_rx_m0 */ |
| <1 RK_PC7 9 &pcfg_pull_up>, |
| /* uart2_tx_m0 */ |
| <1 RK_PC6 9 &pcfg_pull_up>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart2m0_ctsn: uart2m0-ctsn { |
| rockchip,pins = |
| /* uart2m0_ctsn */ |
| <1 RK_PC5 10 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| uart2m0_rtsn: uart2m0-rtsn { |
| rockchip,pins = |
| /* uart2m0_rtsn */ |
| <1 RK_PC4 10 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart2m1_xfer: uart2m1-xfer { |
| rockchip,pins = |
| /* uart2_rx_m1 */ |
| <4 RK_PB4 10 &pcfg_pull_up>, |
| /* uart2_tx_m1 */ |
| <4 RK_PB5 10 &pcfg_pull_up>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart2m1_ctsn: uart2m1-ctsn { |
| rockchip,pins = |
| /* uart2m1_ctsn */ |
| <4 RK_PB1 12 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| uart2m1_rtsn: uart2m1-rtsn { |
| rockchip,pins = |
| /* uart2m1_rtsn */ |
| <4 RK_PB0 12 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart2m2_xfer: uart2m2-xfer { |
| rockchip,pins = |
| /* uart2_rx_m2 */ |
| <3 RK_PB7 9 &pcfg_pull_up>, |
| /* uart2_tx_m2 */ |
| <3 RK_PC0 9 &pcfg_pull_up>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart2m2_ctsn: uart2m2-ctsn { |
| rockchip,pins = |
| /* uart2m2_ctsn */ |
| <3 RK_PD3 9 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| uart2m2_rtsn: uart2m2-rtsn { |
| rockchip,pins = |
| /* uart2m2_rtsn */ |
| <3 RK_PD2 9 &pcfg_pull_none>; |
| }; |
| }; |
| |
| uart3 { |
| /omit-if-no-ref/ |
| uart3m0_xfer: uart3m0-xfer { |
| rockchip,pins = |
| /* uart3_rx_m0 */ |
| <3 RK_PA1 9 &pcfg_pull_up>, |
| /* uart3_tx_m0 */ |
| <3 RK_PA0 9 &pcfg_pull_up>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart3m0_ctsn: uart3m0-ctsn { |
| rockchip,pins = |
| /* uart3m0_ctsn */ |
| <3 RK_PA2 9 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| uart3m0_rtsn: uart3m0-rtsn { |
| rockchip,pins = |
| /* uart3m0_rtsn */ |
| <3 RK_PA3 9 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart3m1_xfer: uart3m1-xfer { |
| rockchip,pins = |
| /* uart3_rx_m1 */ |
| <4 RK_PA1 9 &pcfg_pull_up>, |
| /* uart3_tx_m1 */ |
| <4 RK_PA0 9 &pcfg_pull_up>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart3m1_ctsn: uart3m1-ctsn { |
| rockchip,pins = |
| /* uart3m1_ctsn */ |
| <3 RK_PB7 10 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| uart3m1_rtsn: uart3m1-rtsn { |
| rockchip,pins = |
| /* uart3m1_rtsn */ |
| <3 RK_PC0 10 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart3m2_xfer: uart3m2-xfer { |
| rockchip,pins = |
| /* uart3_rx_m2 */ |
| <1 RK_PC1 9 &pcfg_pull_up>, |
| /* uart3_tx_m2 */ |
| <1 RK_PC0 9 &pcfg_pull_up>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart3m2_ctsn: uart3m2-ctsn { |
| rockchip,pins = |
| /* uart3m2_ctsn */ |
| <1 RK_PB6 9 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| uart3m2_rtsn: uart3m2-rtsn { |
| rockchip,pins = |
| /* uart3m2_rtsn */ |
| <1 RK_PB7 9 &pcfg_pull_none>; |
| }; |
| }; |
| |
| uart4 { |
| /omit-if-no-ref/ |
| uart4m0_xfer: uart4m0-xfer { |
| rockchip,pins = |
| /* uart4_rx_m0 */ |
| <2 RK_PD1 9 &pcfg_pull_up>, |
| /* uart4_tx_m0 */ |
| <2 RK_PD0 9 &pcfg_pull_up>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart4m0_ctsn: uart4m0-ctsn { |
| rockchip,pins = |
| /* uart4m0_ctsn */ |
| <2 RK_PC6 9 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| uart4m0_rtsn: uart4m0-rtsn { |
| rockchip,pins = |
| /* uart4m0_rtsn */ |
| <2 RK_PC7 9 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart4m1_xfer: uart4m1-xfer { |
| rockchip,pins = |
| /* uart4_rx_m1 */ |
| <1 RK_PC5 9 &pcfg_pull_up>, |
| /* uart4_tx_m1 */ |
| <1 RK_PC4 9 &pcfg_pull_up>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart4m1_ctsn: uart4m1-ctsn { |
| rockchip,pins = |
| /* uart4m1_ctsn */ |
| <1 RK_PC3 9 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| uart4m1_rtsn: uart4m1-rtsn { |
| rockchip,pins = |
| /* uart4m1_rtsn */ |
| <1 RK_PC2 9 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart4m2_xfer: uart4m2-xfer { |
| rockchip,pins = |
| /* uart4_rx_m2 */ |
| <0 RK_PB5 10 &pcfg_pull_up>, |
| /* uart4_tx_m2 */ |
| <0 RK_PB4 10 &pcfg_pull_up>; |
| }; |
| }; |
| |
| uart5 { |
| /omit-if-no-ref/ |
| uart5m0_xfer: uart5m0-xfer { |
| rockchip,pins = |
| /* uart5_rx_m0 */ |
| <3 RK_PD4 9 &pcfg_pull_up>, |
| /* uart5_tx_m0 */ |
| <3 RK_PD5 9 &pcfg_pull_up>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart5m0_ctsn: uart5m0-ctsn { |
| rockchip,pins = |
| /* uart5m0_ctsn */ |
| <3 RK_PD6 9 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| uart5m0_rtsn: uart5m0-rtsn { |
| rockchip,pins = |
| /* uart5m0_rtsn */ |
| <3 RK_PD7 9 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart5m1_xfer: uart5m1-xfer { |
| rockchip,pins = |
| /* uart5_rx_m1 */ |
| <4 RK_PB1 10 &pcfg_pull_up>, |
| /* uart5_tx_m1 */ |
| <4 RK_PB0 10 &pcfg_pull_up>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart5m1_ctsn: uart5m1-ctsn { |
| rockchip,pins = |
| /* uart5m1_ctsn */ |
| <4 RK_PA5 10 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| uart5m1_rtsn: uart5m1-rtsn { |
| rockchip,pins = |
| /* uart5m1_rtsn */ |
| <4 RK_PA3 10 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart5m2_xfer: uart5m2-xfer { |
| rockchip,pins = |
| /* uart5_rx_m2 */ |
| <2 RK_PA4 9 &pcfg_pull_up>, |
| /* uart5_tx_m2 */ |
| <2 RK_PA5 9 &pcfg_pull_up>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart5m2_ctsn: uart5m2-ctsn { |
| rockchip,pins = |
| /* uart5m2_ctsn */ |
| <2 RK_PA3 10 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| uart5m2_rtsn: uart5m2-rtsn { |
| rockchip,pins = |
| /* uart5m2_rtsn */ |
| <2 RK_PA2 10 &pcfg_pull_none>; |
| }; |
| }; |
| |
| uart6 { |
| /omit-if-no-ref/ |
| uart6m0_xfer: uart6m0-xfer { |
| rockchip,pins = |
| /* uart6_rx_m0 */ |
| <4 RK_PA6 10 &pcfg_pull_up>, |
| /* uart6_tx_m0 */ |
| <4 RK_PA4 10 &pcfg_pull_up>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart6m0_ctsn: uart6m0-ctsn { |
| rockchip,pins = |
| /* uart6m0_ctsn */ |
| <4 RK_PB1 11 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| uart6m0_rtsn: uart6m0-rtsn { |
| rockchip,pins = |
| /* uart6m0_rtsn */ |
| <4 RK_PB0 11 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart6m1_xfer: uart6m1-xfer { |
| rockchip,pins = |
| /* uart6_rx_m1 */ |
| <2 RK_PD3 9 &pcfg_pull_up>, |
| /* uart6_tx_m1 */ |
| <2 RK_PD2 9 &pcfg_pull_up>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart6m1_ctsn: uart6m1-ctsn { |
| rockchip,pins = |
| /* uart6m1_ctsn */ |
| <2 RK_PD5 9 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| uart6m1_rtsn: uart6m1-rtsn { |
| rockchip,pins = |
| /* uart6m1_rtsn */ |
| <2 RK_PD4 9 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart6m2_xfer: uart6m2-xfer { |
| rockchip,pins = |
| /* uart6_rx_m2 */ |
| <1 RK_PB3 9 &pcfg_pull_up>, |
| /* uart6_tx_m2 */ |
| <1 RK_PB0 9 &pcfg_pull_up>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart6m2_ctsn: uart6m2-ctsn { |
| rockchip,pins = |
| /* uart6m2_ctsn */ |
| <1 RK_PA3 10 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| uart6m2_rtsn: uart6m2-rtsn { |
| rockchip,pins = |
| /* uart6m2_rtsn */ |
| <1 RK_PA2 10 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart6m3_xfer: uart6m3-xfer { |
| rockchip,pins = |
| /* uart6_rx_m3 */ |
| <4 RK_PC5 13 &pcfg_pull_up>, |
| /* uart6_tx_m3 */ |
| <4 RK_PC4 13 &pcfg_pull_up>; |
| }; |
| }; |
| |
| uart7 { |
| /omit-if-no-ref/ |
| uart7m0_xfer: uart7m0-xfer { |
| rockchip,pins = |
| /* uart7_rx_m0 */ |
| <2 RK_PB7 9 &pcfg_pull_up>, |
| /* uart7_tx_m0 */ |
| <2 RK_PB6 9 &pcfg_pull_up>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart7m0_ctsn: uart7m0-ctsn { |
| rockchip,pins = |
| /* uart7m0_ctsn */ |
| <2 RK_PB4 9 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| uart7m0_rtsn: uart7m0-rtsn { |
| rockchip,pins = |
| /* uart7m0_rtsn */ |
| <2 RK_PB5 9 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart7m1_xfer: uart7m1-xfer { |
| rockchip,pins = |
| /* uart7_rx_m1 */ |
| <1 RK_PA3 9 &pcfg_pull_up>, |
| /* uart7_tx_m1 */ |
| <1 RK_PA2 9 &pcfg_pull_up>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart7m1_ctsn: uart7m1-ctsn { |
| rockchip,pins = |
| /* uart7m1_ctsn */ |
| <1 RK_PA1 9 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| uart7m1_rtsn: uart7m1-rtsn { |
| rockchip,pins = |
| /* uart7m1_rtsn */ |
| <1 RK_PA0 9 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart7m2_xfer: uart7m2-xfer { |
| rockchip,pins = |
| /* uart7_rx_m2 */ |
| <2 RK_PA0 10 &pcfg_pull_up>, |
| /* uart7_tx_m2 */ |
| <2 RK_PA1 10 &pcfg_pull_up>; |
| }; |
| }; |
| |
| uart8 { |
| /omit-if-no-ref/ |
| uart8m0_xfer: uart8m0-xfer { |
| rockchip,pins = |
| /* uart8_rx_m0 */ |
| <3 RK_PC5 9 &pcfg_pull_up>, |
| /* uart8_tx_m0 */ |
| <3 RK_PC6 9 &pcfg_pull_up>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart8m0_ctsn: uart8m0-ctsn { |
| rockchip,pins = |
| /* uart8m0_ctsn */ |
| <3 RK_PD0 9 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| uart8m0_rtsn: uart8m0-rtsn { |
| rockchip,pins = |
| /* uart8m0_rtsn */ |
| <3 RK_PC7 9 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart8m1_xfer: uart8m1-xfer { |
| rockchip,pins = |
| /* uart8_rx_m1 */ |
| <2 RK_PA7 9 &pcfg_pull_up>, |
| /* uart8_tx_m1 */ |
| <2 RK_PA6 9 &pcfg_pull_up>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart8m1_ctsn: uart8m1-ctsn { |
| rockchip,pins = |
| /* uart8m1_ctsn */ |
| <2 RK_PB7 10 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| uart8m1_rtsn: uart8m1-rtsn { |
| rockchip,pins = |
| /* uart8m1_rtsn */ |
| <2 RK_PB6 10 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart8m2_xfer: uart8m2-xfer { |
| rockchip,pins = |
| /* uart8_rx_m2 */ |
| <0 RK_PC2 10 &pcfg_pull_up>, |
| /* uart8_tx_m2 */ |
| <0 RK_PC1 10 &pcfg_pull_up>; |
| }; |
| }; |
| |
| uart9 { |
| /omit-if-no-ref/ |
| uart9m0_xfer: uart9m0-xfer { |
| rockchip,pins = |
| /* uart9_rx_m0 */ |
| <2 RK_PC0 9 &pcfg_pull_up>, |
| /* uart9_tx_m0 */ |
| <2 RK_PC1 9 &pcfg_pull_up>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart9m0_ctsn: uart9m0-ctsn { |
| rockchip,pins = |
| /* uart9m0_ctsn */ |
| <2 RK_PD7 9 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| uart9m0_rtsn: uart9m0-rtsn { |
| rockchip,pins = |
| /* uart9m0_rtsn */ |
| <2 RK_PD6 9 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart9m1_xfer: uart9m1-xfer { |
| rockchip,pins = |
| /* uart9_rx_m1 */ |
| <3 RK_PB2 9 &pcfg_pull_up>, |
| /* uart9_tx_m1 */ |
| <3 RK_PB3 9 &pcfg_pull_up>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart9m1_ctsn: uart9m1-ctsn { |
| rockchip,pins = |
| /* uart9m1_ctsn */ |
| <3 RK_PB5 9 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| uart9m1_rtsn: uart9m1-rtsn { |
| rockchip,pins = |
| /* uart9m1_rtsn */ |
| <3 RK_PB4 9 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart9m2_xfer: uart9m2-xfer { |
| rockchip,pins = |
| /* uart9_rx_m2 */ |
| <4 RK_PC3 13 &pcfg_pull_up>, |
| /* uart9_tx_m2 */ |
| <4 RK_PC2 13 &pcfg_pull_up>; |
| }; |
| }; |
| |
| uart10 { |
| /omit-if-no-ref/ |
| uart10m0_xfer: uart10m0-xfer { |
| rockchip,pins = |
| /* uart10_rx_m0 */ |
| <3 RK_PB0 9 &pcfg_pull_up>, |
| /* uart10_tx_m0 */ |
| <3 RK_PB1 9 &pcfg_pull_up>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart10m0_ctsn: uart10m0-ctsn { |
| rockchip,pins = |
| /* uart10m0_ctsn */ |
| <3 RK_PA6 10 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| uart10m0_rtsn: uart10m0-rtsn { |
| rockchip,pins = |
| /* uart10m0_rtsn */ |
| <3 RK_PA7 10 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart10m1_xfer: uart10m1-xfer { |
| rockchip,pins = |
| /* uart10_rx_m1 */ |
| <1 RK_PD1 9 &pcfg_pull_up>, |
| /* uart10_tx_m1 */ |
| <1 RK_PD0 9 &pcfg_pull_up>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart10m1_ctsn: uart10m1-ctsn { |
| rockchip,pins = |
| /* uart10m1_ctsn */ |
| <1 RK_PD5 9 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| uart10m1_rtsn: uart10m1-rtsn { |
| rockchip,pins = |
| /* uart10m1_rtsn */ |
| <1 RK_PD4 9 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart10m2_xfer: uart10m2-xfer { |
| rockchip,pins = |
| /* uart10_rx_m2 */ |
| <0 RK_PC5 10 &pcfg_pull_up>, |
| /* uart10_tx_m2 */ |
| <0 RK_PC4 10 &pcfg_pull_up>; |
| }; |
| }; |
| |
| uart11 { |
| /omit-if-no-ref/ |
| uart11m0_xfer: uart11m0-xfer { |
| rockchip,pins = |
| /* uart11_rx_m0 */ |
| <3 RK_PC1 9 &pcfg_pull_up>, |
| /* uart11_tx_m0 */ |
| <3 RK_PC4 9 &pcfg_pull_up>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart11m0_ctsn: uart11m0-ctsn { |
| rockchip,pins = |
| /* uart11m0_ctsn */ |
| <3 RK_PC3 9 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| uart11m0_rtsn: uart11m0-rtsn { |
| rockchip,pins = |
| /* uart11m0_rtsn */ |
| <3 RK_PC2 9 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart11m1_xfer: uart11m1-xfer { |
| rockchip,pins = |
| /* uart11_rx_m1 */ |
| <2 RK_PC5 9 &pcfg_pull_up>, |
| /* uart11_tx_m1 */ |
| <2 RK_PC4 9 &pcfg_pull_up>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart11m1_ctsn: uart11m1-ctsn { |
| rockchip,pins = |
| /* uart11m1_ctsn */ |
| <2 RK_PC2 9 &pcfg_pull_none>; |
| }; |
| /omit-if-no-ref/ |
| uart11m1_rtsn: uart11m1-rtsn { |
| rockchip,pins = |
| /* uart11m1_rtsn */ |
| <2 RK_PC3 9 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| uart11m2_xfer: uart11m2-xfer { |
| rockchip,pins = |
| /* uart11_rx_m2 */ |
| <4 RK_PC1 13 &pcfg_pull_up>, |
| /* uart11_tx_m2 */ |
| <4 RK_PC0 13 &pcfg_pull_up>; |
| }; |
| }; |
| |
| ufs { |
| /omit-if-no-ref/ |
| ufs_refclk: ufs-refclk { |
| rockchip,pins = |
| /* ufs_refclk */ |
| <4 RK_PD1 1 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| ufs_rst: ufs-rst { |
| rockchip,pins = |
| /* ufs_rstn */ |
| <4 RK_PD0 1 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| ufs_rstgpio: ufs-rstgpio { |
| rockchip,pins = |
| /* ufs_rstn */ |
| <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_down>; |
| }; |
| }; |
| |
| ufs_testdata0 { |
| /omit-if-no-ref/ |
| ufs_testdata0_test: ufs_testdata0-test { |
| rockchip,pins = |
| /* ufs_testdata0_out */ |
| <4 RK_PC4 4 &pcfg_pull_none>; |
| }; |
| }; |
| |
| ufs_testdata1 { |
| /omit-if-no-ref/ |
| ufs_testdata1_test: ufs_testdata1-test { |
| rockchip,pins = |
| /* ufs_testdata1_out */ |
| <4 RK_PC5 4 &pcfg_pull_none>; |
| }; |
| }; |
| |
| ufs_testdata2 { |
| /omit-if-no-ref/ |
| ufs_testdata2_test: ufs_testdata2-test { |
| rockchip,pins = |
| /* ufs_testdata2_out */ |
| <4 RK_PC6 4 &pcfg_pull_none>; |
| }; |
| }; |
| |
| ufs_testdata3 { |
| /omit-if-no-ref/ |
| ufs_testdata3_test: ufs_testdata3-test { |
| rockchip,pins = |
| /* ufs_testdata3_out */ |
| <4 RK_PC7 4 &pcfg_pull_none>; |
| }; |
| }; |
| |
| vi_cif { |
| /omit-if-no-ref/ |
| vi_cif_pins: vi_cif-pins { |
| rockchip,pins = |
| /* vi_cif_clki */ |
| <3 RK_PA3 1 &pcfg_pull_none>, |
| /* vi_cif_clko */ |
| <3 RK_PA2 1 &pcfg_pull_none>, |
| /* vi_cif_d0 */ |
| <2 RK_PC5 1 &pcfg_pull_none>, |
| /* vi_cif_d1 */ |
| <2 RK_PC4 1 &pcfg_pull_none>, |
| /* vi_cif_d2 */ |
| <2 RK_PC3 1 &pcfg_pull_none>, |
| /* vi_cif_d3 */ |
| <2 RK_PC2 1 &pcfg_pull_none>, |
| /* vi_cif_d4 */ |
| <2 RK_PC1 1 &pcfg_pull_none>, |
| /* vi_cif_d5 */ |
| <2 RK_PC0 1 &pcfg_pull_none>, |
| /* vi_cif_d6 */ |
| <2 RK_PB7 1 &pcfg_pull_none>, |
| /* vi_cif_d7 */ |
| <2 RK_PB6 1 &pcfg_pull_none>, |
| /* vi_cif_d8 */ |
| <2 RK_PB5 1 &pcfg_pull_none>, |
| /* vi_cif_d9 */ |
| <2 RK_PB4 1 &pcfg_pull_none>, |
| /* vi_cif_d10 */ |
| <2 RK_PB3 1 &pcfg_pull_none>, |
| /* vi_cif_d11 */ |
| <2 RK_PB2 1 &pcfg_pull_none>, |
| /* vi_cif_d12 */ |
| <2 RK_PB1 1 &pcfg_pull_none>, |
| /* vi_cif_d13 */ |
| <2 RK_PB0 1 &pcfg_pull_none>, |
| /* vi_cif_d14 */ |
| <2 RK_PA7 1 &pcfg_pull_none>, |
| /* vi_cif_d15 */ |
| <2 RK_PA6 1 &pcfg_pull_none>, |
| /* vi_cif_href */ |
| <3 RK_PA0 1 &pcfg_pull_none>, |
| /* vi_cif_vsync */ |
| <3 RK_PA1 1 &pcfg_pull_none>; |
| }; |
| }; |
| |
| vo_lcdc { |
| /omit-if-no-ref/ |
| vo_lcdc_pins: vo_lcdc-pins { |
| rockchip,pins = |
| /* vo_lcdc_clk */ |
| <3 RK_PD7 1 &pcfg_pull_none>, |
| /* vo_lcdc_d0 */ |
| <3 RK_PD3 1 &pcfg_pull_none>, |
| /* vo_lcdc_d1 */ |
| <3 RK_PD2 1 &pcfg_pull_none>, |
| /* vo_lcdc_d2 */ |
| <3 RK_PD1 1 &pcfg_pull_none>, |
| /* vo_lcdc_d3 */ |
| <3 RK_PD0 1 &pcfg_pull_none>, |
| /* vo_lcdc_d4 */ |
| <3 RK_PC7 1 &pcfg_pull_none>, |
| /* vo_lcdc_d5 */ |
| <3 RK_PC6 1 &pcfg_pull_none>, |
| /* vo_lcdc_d6 */ |
| <3 RK_PC5 1 &pcfg_pull_none>, |
| /* vo_lcdc_d7 */ |
| <3 RK_PC4 1 &pcfg_pull_none>, |
| /* vo_lcdc_d8 */ |
| <3 RK_PC3 1 &pcfg_pull_none>, |
| /* vo_lcdc_d9 */ |
| <3 RK_PC2 1 &pcfg_pull_none>, |
| /* vo_lcdc_d10 */ |
| <3 RK_PC1 1 &pcfg_pull_none>, |
| /* vo_lcdc_d11 */ |
| <3 RK_PC0 1 &pcfg_pull_none>, |
| /* vo_lcdc_d12 */ |
| <3 RK_PB7 1 &pcfg_pull_none>, |
| /* vo_lcdc_d13 */ |
| <3 RK_PB6 1 &pcfg_pull_none>, |
| /* vo_lcdc_d14 */ |
| <3 RK_PB5 1 &pcfg_pull_none>, |
| /* vo_lcdc_d15 */ |
| <3 RK_PB4 1 &pcfg_pull_none>, |
| /* vo_lcdc_d16 */ |
| <3 RK_PB3 1 &pcfg_pull_none>, |
| /* vo_lcdc_d17 */ |
| <3 RK_PB2 1 &pcfg_pull_none>, |
| /* vo_lcdc_d18 */ |
| <3 RK_PB1 1 &pcfg_pull_none>, |
| /* vo_lcdc_d19 */ |
| <3 RK_PB0 1 &pcfg_pull_none>, |
| /* vo_lcdc_d20 */ |
| <3 RK_PA7 1 &pcfg_pull_none>, |
| /* vo_lcdc_d21 */ |
| <3 RK_PA6 1 &pcfg_pull_none>, |
| /* vo_lcdc_d22 */ |
| <3 RK_PA5 1 &pcfg_pull_none>, |
| /* vo_lcdc_d23 */ |
| <3 RK_PA4 1 &pcfg_pull_none>, |
| /* vo_lcdc_den */ |
| <3 RK_PD4 1 &pcfg_pull_none>, |
| /* vo_lcdc_hsync */ |
| <3 RK_PD5 1 &pcfg_pull_none>, |
| /* vo_lcdc_vsync */ |
| <3 RK_PD6 1 &pcfg_pull_none>; |
| }; |
| }; |
| |
| vo_post { |
| /omit-if-no-ref/ |
| vo_post_pins: vo_post-pins { |
| rockchip,pins = |
| /* vo_post_empty */ |
| <4 RK_PA1 1 &pcfg_pull_none>; |
| }; |
| }; |
| |
| vp0_sync { |
| /omit-if-no-ref/ |
| vp0_sync_pins: vp0_sync-pins { |
| rockchip,pins = |
| /* vp0_sync_out */ |
| <4 RK_PC5 3 &pcfg_pull_none>; |
| }; |
| }; |
| |
| vp1_sync { |
| /omit-if-no-ref/ |
| vp1_sync_pins: vp1_sync-pins { |
| rockchip,pins = |
| /* vp1_sync_out */ |
| <4 RK_PC6 3 &pcfg_pull_none>; |
| }; |
| }; |
| |
| vp2_sync { |
| /omit-if-no-ref/ |
| vp2_sync_pins: vp2_sync-pins { |
| rockchip,pins = |
| /* vp2_sync_out */ |
| <4 RK_PC7 3 &pcfg_pull_none>; |
| }; |
| }; |
| }; |
| |
| /* |
| * This part is edited handly. |
| */ |
| &pinctrl { |
| pmic { |
| /omit-if-no-ref/ |
| pmic_pins: pmic-pins { |
| rockchip,pins = |
| /* pmic_int */ |
| <0 RK_PA6 9 &pcfg_pull_up>, |
| /* pmic_sleep */ |
| <0 RK_PA4 9 &pcfg_pull_none>; |
| }; |
| }; |
| |
| vo { |
| /omit-if-no-ref/ |
| bt1120_pins: bt1120-pins { |
| rockchip,pins = |
| /* vo_lcdc_clk */ |
| <3 RK_PD7 1 &pcfg_pull_none>, |
| /* vo_lcdc_d3 */ |
| <3 RK_PD0 1 &pcfg_pull_none>, |
| /* vo_lcdc_d4 */ |
| <3 RK_PC7 1 &pcfg_pull_none>, |
| /* vo_lcdc_d5 */ |
| <3 RK_PC6 1 &pcfg_pull_none>, |
| /* vo_lcdc_d6 */ |
| <3 RK_PC5 1 &pcfg_pull_none>, |
| /* vo_lcdc_d7 */ |
| <3 RK_PC4 1 &pcfg_pull_none>, |
| /* vo_lcdc_d10 */ |
| <3 RK_PC1 1 &pcfg_pull_none>, |
| /* vo_lcdc_d11 */ |
| <3 RK_PC0 1 &pcfg_pull_none>, |
| /* vo_lcdc_d12 */ |
| <3 RK_PB7 1 &pcfg_pull_none>, |
| /* vo_lcdc_d13 */ |
| <3 RK_PB6 1 &pcfg_pull_none>, |
| /* vo_lcdc_d14 */ |
| <3 RK_PB5 1 &pcfg_pull_none>, |
| /* vo_lcdc_d15 */ |
| <3 RK_PB4 1 &pcfg_pull_none>, |
| /* vo_lcdc_d19 */ |
| <3 RK_PB0 1 &pcfg_pull_none>, |
| /* vo_lcdc_d20 */ |
| <3 RK_PA7 1 &pcfg_pull_none>, |
| /* vo_lcdc_d21 */ |
| <3 RK_PA6 1 &pcfg_pull_none>, |
| /* vo_lcdc_d22 */ |
| <3 RK_PA5 1 &pcfg_pull_none>, |
| /* vo_lcdc_d23 */ |
| <3 RK_PA4 1 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| bt656_pins: bt656-pins { |
| rockchip,pins = |
| /* vo_lcdc_clk */ |
| <3 RK_PD7 1 &pcfg_pull_none>, |
| /* vo_lcdc_d3 */ |
| <3 RK_PD0 1 &pcfg_pull_none>, |
| /* vo_lcdc_d4 */ |
| <3 RK_PC7 1 &pcfg_pull_none>, |
| /* vo_lcdc_d5 */ |
| <3 RK_PC6 1 &pcfg_pull_none>, |
| /* vo_lcdc_d6 */ |
| <3 RK_PC5 1 &pcfg_pull_none>, |
| /* vo_lcdc_d7 */ |
| <3 RK_PC4 1 &pcfg_pull_none>, |
| /* vo_lcdc_d10 */ |
| <3 RK_PC1 1 &pcfg_pull_none>, |
| /* vo_lcdc_d11 */ |
| <3 RK_PC0 1 &pcfg_pull_none>, |
| /* vo_lcdc_d12 */ |
| <3 RK_PB7 1 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| rgb3x8_pins_m0: rgb3x8-pins-m0 { |
| rockchip,pins = |
| /* vo_lcdc_clk */ |
| <3 RK_PD7 1 &pcfg_pull_none>, |
| /* vo_lcdc_d3 */ |
| <3 RK_PD0 1 &pcfg_pull_none>, |
| /* vo_lcdc_d4 */ |
| <3 RK_PC7 1 &pcfg_pull_none>, |
| /* vo_lcdc_d5 */ |
| <3 RK_PC6 1 &pcfg_pull_none>, |
| /* vo_lcdc_d6 */ |
| <3 RK_PC5 1 &pcfg_pull_none>, |
| /* vo_lcdc_d7 */ |
| <3 RK_PC4 1 &pcfg_pull_none>, |
| /* vo_lcdc_d10 */ |
| <3 RK_PC1 1 &pcfg_pull_none>, |
| /* vo_lcdc_d11 */ |
| <3 RK_PC0 1 &pcfg_pull_none>, |
| /* vo_lcdc_d12 */ |
| <3 RK_PB7 1 &pcfg_pull_none>, |
| /* vo_lcdc_den */ |
| <3 RK_PD4 1 &pcfg_pull_none>, |
| /* vo_lcdc_hsync */ |
| <3 RK_PD5 1 &pcfg_pull_none>, |
| /* vo_lcdc_vsync */ |
| <3 RK_PD6 1 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| rgb3x8_pins_m1: rgb3x8-pins-m1 { |
| rockchip,pins = |
| /* vo_lcdc_clk */ |
| <3 RK_PD7 1 &pcfg_pull_none>, |
| /* vo_lcdc_d13 */ |
| <3 RK_PB6 1 &pcfg_pull_none>, |
| /* vo_lcdc_d14 */ |
| <3 RK_PB5 1 &pcfg_pull_none>, |
| /* vo_lcdc_d15 */ |
| <3 RK_PB4 1 &pcfg_pull_none>, |
| /* vo_lcdc_d19 */ |
| <3 RK_PB0 1 &pcfg_pull_none>, |
| /* vo_lcdc_d20 */ |
| <3 RK_PA7 1 &pcfg_pull_none>, |
| /* vo_lcdc_d21 */ |
| <3 RK_PA6 1 &pcfg_pull_none>, |
| /* vo_lcdc_d22 */ |
| <3 RK_PA5 1 &pcfg_pull_none>, |
| /* vo_lcdc_d23 */ |
| <3 RK_PA4 1 &pcfg_pull_none>, |
| /* vo_lcdc_den */ |
| <3 RK_PD4 1 &pcfg_pull_none>, |
| /* vo_lcdc_hsync */ |
| <3 RK_PD5 1 &pcfg_pull_none>, |
| /* vo_lcdc_vsync */ |
| <3 RK_PD6 1 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| rgb565_pins: rgb565-pins { |
| rockchip,pins = |
| /* vo_lcdc_clk */ |
| <3 RK_PD7 1 &pcfg_pull_none>, |
| /* vo_lcdc_d3 */ |
| <3 RK_PD0 1 &pcfg_pull_none>, |
| /* vo_lcdc_d4 */ |
| <3 RK_PC7 1 &pcfg_pull_none>, |
| /* vo_lcdc_d5 */ |
| <3 RK_PC6 1 &pcfg_pull_none>, |
| /* vo_lcdc_d6 */ |
| <3 RK_PC5 1 &pcfg_pull_none>, |
| /* vo_lcdc_d7 */ |
| <3 RK_PC4 1 &pcfg_pull_none>, |
| /* vo_lcdc_d10 */ |
| <3 RK_PC1 1 &pcfg_pull_none>, |
| /* vo_lcdc_d11 */ |
| <3 RK_PC0 1 &pcfg_pull_none>, |
| /* vo_lcdc_d12 */ |
| <3 RK_PB7 1 &pcfg_pull_none>, |
| /* vo_lcdc_d13 */ |
| <3 RK_PB6 1 &pcfg_pull_none>, |
| /* vo_lcdc_d14 */ |
| <3 RK_PB5 1 &pcfg_pull_none>, |
| /* vo_lcdc_d15 */ |
| <3 RK_PB4 1 &pcfg_pull_none>, |
| /* vo_lcdc_d19 */ |
| <3 RK_PB0 1 &pcfg_pull_none>, |
| /* vo_lcdc_d20 */ |
| <3 RK_PA7 1 &pcfg_pull_none>, |
| /* vo_lcdc_d21 */ |
| <3 RK_PA6 1 &pcfg_pull_none>, |
| /* vo_lcdc_d22 */ |
| <3 RK_PA5 1 &pcfg_pull_none>, |
| /* vo_lcdc_d23 */ |
| <3 RK_PA4 1 &pcfg_pull_none>, |
| /* vo_lcdc_den */ |
| <3 RK_PD4 1 &pcfg_pull_none>, |
| /* vo_lcdc_hsync */ |
| <3 RK_PD5 1 &pcfg_pull_none>, |
| /* vo_lcdc_vsync */ |
| <3 RK_PD6 1 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| rgb666_pins: rgb666-pins { |
| rockchip,pins = |
| /* vo_lcdc_clk */ |
| <3 RK_PD7 1 &pcfg_pull_none>, |
| /* vo_lcdc_d2 */ |
| <3 RK_PD1 1 &pcfg_pull_none>, |
| /* vo_lcdc_d3 */ |
| <3 RK_PD0 1 &pcfg_pull_none>, |
| /* vo_lcdc_d4 */ |
| <3 RK_PC7 1 &pcfg_pull_none>, |
| /* vo_lcdc_d5 */ |
| <3 RK_PC6 1 &pcfg_pull_none>, |
| /* vo_lcdc_d6 */ |
| <3 RK_PC5 1 &pcfg_pull_none>, |
| /* vo_lcdc_d7 */ |
| <3 RK_PC4 1 &pcfg_pull_none>, |
| /* vo_lcdc_d10 */ |
| <3 RK_PC1 1 &pcfg_pull_none>, |
| /* vo_lcdc_d11 */ |
| <3 RK_PC0 1 &pcfg_pull_none>, |
| /* vo_lcdc_d12 */ |
| <3 RK_PB7 1 &pcfg_pull_none>, |
| /* vo_lcdc_d13 */ |
| <3 RK_PB6 1 &pcfg_pull_none>, |
| /* vo_lcdc_d14 */ |
| <3 RK_PB5 1 &pcfg_pull_none>, |
| /* vo_lcdc_d15 */ |
| <3 RK_PB4 1 &pcfg_pull_none>, |
| /* vo_lcdc_d18 */ |
| <3 RK_PB1 1 &pcfg_pull_none>, |
| /* vo_lcdc_d19 */ |
| <3 RK_PB0 1 &pcfg_pull_none>, |
| /* vo_lcdc_d20 */ |
| <3 RK_PA7 1 &pcfg_pull_none>, |
| /* vo_lcdc_d21 */ |
| <3 RK_PA6 1 &pcfg_pull_none>, |
| /* vo_lcdc_d22 */ |
| <3 RK_PA5 1 &pcfg_pull_none>, |
| /* vo_lcdc_d23 */ |
| <3 RK_PA4 1 &pcfg_pull_none>, |
| /* vo_lcdc_den */ |
| <3 RK_PD4 1 &pcfg_pull_none>, |
| /* vo_lcdc_hsync */ |
| <3 RK_PD5 1 &pcfg_pull_none>, |
| /* vo_lcdc_vsync */ |
| <3 RK_PD6 1 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| rgb888_pins: rgb888-pins { |
| rockchip,pins = |
| /* vo_lcdc_clk */ |
| <3 RK_PD7 1 &pcfg_pull_none>, |
| /* vo_lcdc_d0 */ |
| <3 RK_PD3 1 &pcfg_pull_none>, |
| /* vo_lcdc_d1 */ |
| <3 RK_PD2 1 &pcfg_pull_none>, |
| /* vo_lcdc_d2 */ |
| <3 RK_PD1 1 &pcfg_pull_none>, |
| /* vo_lcdc_d3 */ |
| <3 RK_PD0 1 &pcfg_pull_none>, |
| /* vo_lcdc_d4 */ |
| <3 RK_PC7 1 &pcfg_pull_none>, |
| /* vo_lcdc_d5 */ |
| <3 RK_PC6 1 &pcfg_pull_none>, |
| /* vo_lcdc_d6 */ |
| <3 RK_PC5 1 &pcfg_pull_none>, |
| /* vo_lcdc_d7 */ |
| <3 RK_PC4 1 &pcfg_pull_none>, |
| /* vo_lcdc_d8 */ |
| <3 RK_PC3 1 &pcfg_pull_none>, |
| /* vo_lcdc_d9 */ |
| <3 RK_PC2 1 &pcfg_pull_none>, |
| /* vo_lcdc_d10 */ |
| <3 RK_PC1 1 &pcfg_pull_none>, |
| /* vo_lcdc_d11 */ |
| <3 RK_PC0 1 &pcfg_pull_none>, |
| /* vo_lcdc_d12 */ |
| <3 RK_PB7 1 &pcfg_pull_none>, |
| /* vo_lcdc_d13 */ |
| <3 RK_PB6 1 &pcfg_pull_none>, |
| /* vo_lcdc_d14 */ |
| <3 RK_PB5 1 &pcfg_pull_none>, |
| /* vo_lcdc_d15 */ |
| <3 RK_PB4 1 &pcfg_pull_none>, |
| /* vo_lcdc_d16 */ |
| <3 RK_PB3 1 &pcfg_pull_none>, |
| /* vo_lcdc_d17 */ |
| <3 RK_PB2 1 &pcfg_pull_none>, |
| /* vo_lcdc_d18 */ |
| <3 RK_PB1 1 &pcfg_pull_none>, |
| /* vo_lcdc_d19 */ |
| <3 RK_PB0 1 &pcfg_pull_none>, |
| /* vo_lcdc_d20 */ |
| <3 RK_PA7 1 &pcfg_pull_none>, |
| /* vo_lcdc_d21 */ |
| <3 RK_PA6 1 &pcfg_pull_none>, |
| /* vo_lcdc_d22 */ |
| <3 RK_PA5 1 &pcfg_pull_none>, |
| /* vo_lcdc_d23 */ |
| <3 RK_PA4 1 &pcfg_pull_none>, |
| /* vo_lcdc_den */ |
| <3 RK_PD4 1 &pcfg_pull_none>, |
| /* vo_lcdc_hsync */ |
| <3 RK_PD5 1 &pcfg_pull_none>, |
| /* vo_lcdc_vsync */ |
| <3 RK_PD6 1 &pcfg_pull_none>; |
| }; |
| }; |
| |
| vo_ebc { |
| /omit-if-no-ref/ |
| vo_ebc_pins: vo_ebc-pins { |
| rockchip,pins = |
| /* vo_ebc_gdclk */ |
| <3 RK_PD5 2 &pcfg_pull_none>, |
| /* vo_ebc_gdoe */ |
| <3 RK_PA6 2 &pcfg_pull_none>, |
| /* vo_ebc_gdsp */ |
| <3 RK_PA5 2 &pcfg_pull_none>, |
| /* vo_ebc_sdce0 */ |
| <3 RK_PB3 2 &pcfg_pull_none>, |
| /* vo_ebc_sdclk */ |
| <3 RK_PD6 2 &pcfg_pull_none>, |
| /* vo_ebc_sddo0 */ |
| <3 RK_PD3 2 &pcfg_pull_none>, |
| /* vo_ebc_sddo1 */ |
| <3 RK_PD2 2 &pcfg_pull_none>, |
| /* vo_ebc_sddo2 */ |
| <3 RK_PD1 2 &pcfg_pull_none>, |
| /* vo_ebc_sddo3 */ |
| <3 RK_PD0 2 &pcfg_pull_none>, |
| /* vo_ebc_sddo4 */ |
| <3 RK_PC7 2 &pcfg_pull_none>, |
| /* vo_ebc_sddo5 */ |
| <3 RK_PC6 2 &pcfg_pull_none>, |
| /* vo_ebc_sddo6 */ |
| <3 RK_PC5 2 &pcfg_pull_none>, |
| /* vo_ebc_sddo7 */ |
| <3 RK_PC4 2 &pcfg_pull_none>, |
| /* vo_ebc_sddo8 */ |
| <3 RK_PC3 2 &pcfg_pull_none>, |
| /* vo_ebc_sddo9 */ |
| <3 RK_PC2 2 &pcfg_pull_none>, |
| /* vo_ebc_sddo10 */ |
| <3 RK_PC1 2 &pcfg_pull_none>, |
| /* vo_ebc_sddo11 */ |
| <3 RK_PC0 2 &pcfg_pull_none>, |
| /* vo_ebc_sddo12 */ |
| <3 RK_PB7 2 &pcfg_pull_none>, |
| /* vo_ebc_sddo13 */ |
| <3 RK_PB6 2 &pcfg_pull_none>, |
| /* vo_ebc_sddo14 */ |
| <3 RK_PB5 2 &pcfg_pull_none>, |
| /* vo_ebc_sddo15 */ |
| <3 RK_PB4 2 &pcfg_pull_none>, |
| /* vo_ebc_sdle */ |
| <3 RK_PD4 2 &pcfg_pull_none>, |
| /* vo_ebc_sdoe */ |
| <3 RK_PD7 2 &pcfg_pull_none>; |
| }; |
| |
| /omit-if-no-ref/ |
| vo_ebc_extern: vo_ebc-extern { |
| rockchip,pins = |
| /* vo_ebc_sdce1 */ |
| <3 RK_PB2 2 &pcfg_pull_none>, |
| /* vo_ebc_sdce2 */ |
| <3 RK_PB1 2 &pcfg_pull_none>, |
| /* vo_ebc_sdce3 */ |
| <3 RK_PB0 2 &pcfg_pull_none>, |
| /* vo_ebc_sdshr */ |
| <3 RK_PA4 2 &pcfg_pull_none>, |
| /* vo_ebc_vcom */ |
| <3 RK_PA7 2 &pcfg_pull_none>; |
| }; |
| }; |
| }; |