arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi - third_party/linux - Git at Google

 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
 /*
  * Device Tree Source for the R9A09G047E57 SMARC SoM board.
  *
  * Copyright (C) 2024 Renesas Electronics Corp.
  */

 /*
  * Please set the below switch position on the SoM and the corresponding macro
  * on the board DTS:
  *
  * Switch position SYS.1, Macro SW_SD0_DEV_SEL:
  *      0 - SD0 is connected to eMMC (default)
  *      1 - SD0 is connected to uSD0 card
  *
  * Switch position SYS.5, Macro SW_LCD_EN:
  *      0 - Select Misc. Signals routing
  *      1 - Select LCD
  *
  * Switch position BOOT.6, Macro SW_PDM_EN:
  *      0 - Select CAN routing
  *      1 - Select PDM
  */

 / {
 	compatible = "renesas,rzg3e-smarcm", "renesas,r9a09g047e57", "renesas,r9a09g047";

 	aliases {
 		ethernet0 = &eth0;
 		ethernet1 = &eth1;
 		i2c2 = &i2c2;
 		mmc0 = &sdhi0;
 		mmc2 = &sdhi2;
 	};

 	memory@48000000 {
 		device_type = "memory";
 		/* First 128MB is reserved for secure area. */
 		reg = <0x0 0x48000000 0x0 0xf8000000>;
 	};

 	reg_1p8v: regulator-1p8v {
 		compatible = "regulator-fixed";
 		regulator-name = "fixed-1.8V";
 		regulator-min-microvolt = <1800000>;
 		regulator-max-microvolt = <1800000>;
 		regulator-boot-on;
 		regulator-always-on;
 	};

 	reg_3p3v: regulator-3p3v {
 		compatible = "regulator-fixed";
 		regulator-name = "fixed-3.3V";
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
 		regulator-boot-on;
 		regulator-always-on;
 	};

 	reg_vdd0p8v_others: regulator-vdd0p8v-others {
 		compatible = "regulator-fixed";

 		regulator-name = "fixed-0.8V";
 		regulator-min-microvolt = <800000>;
 		regulator-max-microvolt = <800000>;
 		regulator-boot-on;
 		regulator-always-on;
 	};

 	/* 32.768kHz crystal */
 	x3: x3-clock {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
 		clock-frequency = <32768>;
 	};
 };

 &audio_extal_clk {
 	clock-frequency = <48000000>;
 };

 &eth0 {
 	phy-handle = <&phy0>;
 	phy-mode = "rgmii-id";

 	pinctrl-0 = <&eth0_pins>;
 	pinctrl-names = "default";
 	status = "okay";
 };

 &eth1 {
 	phy-handle = <&phy1>;
 	phy-mode = "rgmii-id";

 	pinctrl-0 = <&eth1_pins>;
 	pinctrl-names = "default";
 	status = "okay";
 };

 &gpu {
 	status = "okay";
 	mali-supply = <&reg_vdd0p8v_others>;
 };

 &i2c2 {
 	pinctrl-0 = <&i2c2_pins>;
 	pinctrl-names = "default";
 	clock-frequency = <400000>;
 	status = "okay";

 	raa215300: pmic@12 {
 		compatible = "renesas,raa215300";
 		reg = <0x12>, <0x6f>;
 		reg-names = "main", "rtc";
 		clocks = <&x3>;
 		clock-names = "xin";

 		pinctrl-0 = <&rtc_irq_pin>;
 		pinctrl-names = "default";

 		interrupts-extended = <&pinctrl RZG3E_GPIO(S, 1) IRQ_TYPE_EDGE_FALLING>;
 	};
 };

 &mdio0 {
 	phy0: ethernet-phy@7 {
 		compatible = "ethernet-phy-id0022.1640",
 			     "ethernet-phy-ieee802.3-c22";
 		reg = <7>;
 		interrupts-extended = <&icu 3 IRQ_TYPE_LEVEL_LOW>;
 		rxc-skew-psec = <1400>;
 		txc-skew-psec = <1400>;
 		rxdv-skew-psec = <0>;
 		txdv-skew-psec = <0>;
 		rxd0-skew-psec = <0>;
 		rxd1-skew-psec = <0>;
 		rxd2-skew-psec = <0>;
 		rxd3-skew-psec = <0>;
 		txd0-skew-psec = <0>;
 		txd1-skew-psec = <0>;
 		txd2-skew-psec = <0>;
 		txd3-skew-psec = <0>;
 	};
 };

 &mdio1 {
 	phy1: ethernet-phy@7 {
 		compatible = "ethernet-phy-id0022.1640",
 			     "ethernet-phy-ieee802.3-c22";
 		reg = <7>;
 		interrupts-extended = <&icu 16 IRQ_TYPE_LEVEL_LOW>;
 		rxc-skew-psec = <1400>;
 		txc-skew-psec = <1400>;
 		rxdv-skew-psec = <0>;
 		txdv-skew-psec = <0>;
 		rxd0-skew-psec = <0>;
 		rxd1-skew-psec = <0>;
 		rxd2-skew-psec = <0>;
 		rxd3-skew-psec = <0>;
 		txd0-skew-psec = <0>;
 		txd1-skew-psec = <0>;
 		txd2-skew-psec = <0>;
 		txd3-skew-psec = <0>;
 	};
 };

 &pinctrl {
 	eth0_pins: eth0 {
 		clk {
 			pinmux = <RZG3E_PORT_PINMUX(B, 1, 1)>; /* TXC */
 			output-enable;
 		};

 		ctrl {
 			pinmux = <RZG3E_PORT_PINMUX(A, 1, 1)>, /* MDC */
 				 <RZG3E_PORT_PINMUX(A, 0, 1)>, /* MDIO */
 				 <RZG3E_PORT_PINMUX(C, 2, 15)>, /* PHY_INTR (IRQ2) */
 				 <RZG3E_PORT_PINMUX(C, 1, 1)>, /* RXD3 */
 				 <RZG3E_PORT_PINMUX(C, 0, 1)>, /* RXD2 */
 				 <RZG3E_PORT_PINMUX(B, 7, 1)>, /* RXD1 */
 				 <RZG3E_PORT_PINMUX(B, 6, 1)>, /* RXD0 */
 				 <RZG3E_PORT_PINMUX(B, 0, 1)>, /* RXC */
 				 <RZG3E_PORT_PINMUX(A, 2, 1)>, /* RX_CTL */
 				 <RZG3E_PORT_PINMUX(B, 5, 1)>, /* TXD3 */
 				 <RZG3E_PORT_PINMUX(B, 4, 1)>, /* TXD2 */
 				 <RZG3E_PORT_PINMUX(B, 3, 1)>, /* TXD1 */
 				 <RZG3E_PORT_PINMUX(B, 2, 1)>, /* TXD0 */
 				 <RZG3E_PORT_PINMUX(A, 3, 1)>; /* TX_CTL */
 		};
 	};

 	eth1_pins: eth1 {
 		clk {
 			pinmux = <RZG3E_PORT_PINMUX(E, 1, 1)>; /* TXC */
 			output-enable;
 		};

 		ctrl {

 			pinmux = <RZG3E_PORT_PINMUX(D, 1, 1)>, /* MDC */
 				 <RZG3E_PORT_PINMUX(D, 0, 1)>, /* MDIO */
 				 <RZG3E_PORT_PINMUX(F, 2, 15)>, /* PHY_INTR (IRQ15) */
 				 <RZG3E_PORT_PINMUX(F, 1, 1)>, /* RXD3 */
 				 <RZG3E_PORT_PINMUX(F, 0, 1)>, /* RXD2 */
 				 <RZG3E_PORT_PINMUX(E, 7, 1)>, /* RXD1 */
 				 <RZG3E_PORT_PINMUX(E, 6, 1)>, /* RXD0 */
 				 <RZG3E_PORT_PINMUX(E, 0, 1)>, /* RXC */
 				 <RZG3E_PORT_PINMUX(D, 2, 1)>, /* RX_CTL */
 				 <RZG3E_PORT_PINMUX(E, 5, 1)>, /* TXD3 */
 				 <RZG3E_PORT_PINMUX(E, 4, 1)>, /* TXD2 */
 				 <RZG3E_PORT_PINMUX(E, 3, 1)>, /* TXD1 */
 				 <RZG3E_PORT_PINMUX(E, 2, 1)>, /* TXD0 */
 				 <RZG3E_PORT_PINMUX(D, 3, 1)>; /* TX_CTL */
 		};
 	};

 	i2c2_pins: i2c {
 		pinmux = <RZG3E_PORT_PINMUX(3, 4, 1)>, /* SCL2 */
 			 <RZG3E_PORT_PINMUX(3, 5, 1)>; /* SDA2 */
 	};

 	rtc_irq_pin: rtc-irq {
 		pins = "PS1";
 		bias-pull-up;
 	};

 	sdhi0_emmc_pins: sd0-emmc {
 		sd0-ctrl {
 			pins = "SD0CLK", "SD0CMD";
 			renesas,output-impedance = <3>;
 		};

 		sd0-data {
 			pins = "SD0DAT0", "SD0DAT1", "SD0DAT2", "SD0DAT3",
 			       "SD0DAT4", "SD0DAT5", "SD0DAT6", "SD0DAT7";
 			renesas,output-impedance = <3>;
 		};

 		sd0-rst {
 			pins = "SD0RSTN";
 			renesas,output-impedance = <3>;
 		};
 	};

 	sdhi0_usd_pins: sd0-usd {
 		sd0-cd {
 			pinmux = <RZG3E_PORT_PINMUX(5, 0, 8)>;
 		};

 		sd0-ctrl {
 			pins = "SD0CLK", "SD0CMD";
 			renesas,output-impedance = <3>;
 		};

 		sd0-data {
 			pins = "SD0DAT0", "SD0DAT1", "SD0DAT2", "SD0DAT3";
 			renesas,output-impedance = <3>;
 		};

 		sd0-iovs {
 			pins = "SD0IOVS";
 			renesas,output-impedance = <3>;
 		};

 		sd0-pwen {
 			pins = "SD0PWEN";
 			renesas,output-impedance = <3>;
 		};
 	};

 	sdhi2_pins: sd2 {
 		sd2-cd {
 			pinmux = <RZG3E_PORT_PINMUX(K, 0, 1)>; /* SD2CD */
 		};

 		sd2-ctrl {
 			pinmux = <RZG3E_PORT_PINMUX(H, 0, 1)>, /* SD2CLK */
 				 <RZG3E_PORT_PINMUX(H, 1, 1)>; /* SD2CMD */
 		};

 		sd2-data {
 			pinmux = <RZG3E_PORT_PINMUX(H, 2, 1)>, /* SD2DAT0 */
 				 <RZG3E_PORT_PINMUX(H, 3, 1)>, /* SD2DAT1 */
 				 <RZG3E_PORT_PINMUX(H, 4, 1)>, /* SD2DAT2 */
 				 <RZG3E_PORT_PINMUX(H, 5, 1)>; /* SD2DAT3 */
 		};

 		sd2-iovs {
 			pinmux = <RZG3E_PORT_PINMUX(K, 1, 1)>; /* SD2IOVS */
 		};

 		sd2-pwen {
 			pinmux = <RZG3E_PORT_PINMUX(K, 2, 1)>; /* SD2PWEN */
 		};
 	};

 	xspi_pins: xspi0 {
 		pinmux = <RZG3E_PORT_PINMUX(M, 0, 0)>, /* XSPI0_IO0 */
 			 <RZG3E_PORT_PINMUX(M, 1, 0)>, /* XSPI0_IO1 */
 			 <RZG3E_PORT_PINMUX(M, 2, 0)>, /* XSPI0_IO2 */
 			 <RZG3E_PORT_PINMUX(M, 3, 0)>, /* XSPI0_IO3 */
 			 <RZG3E_PORT_PINMUX(L, 0, 0)>, /* XSPI0_CKP */
 			 <RZG3E_PORT_PINMUX(L, 1, 0)>; /* XSPI0_CS0 */
 	};
 };

 &qextal_clk {
 	clock-frequency = <24000000>;
 };

 &rtxin_clk {
 	clock-frequency = <32768>;
 };

 #if (SW_SD0_DEV_SEL)
 &sdhi0 {
 	pinctrl-0 = <&sdhi0_usd_pins>;
 	pinctrl-1 = <&sdhi0_usd_pins>;
 	pinctrl-names = "default", "state_uhs";

 	vmmc-supply = <&reg_3p3v>;
 	vqmmc-supply = <&sdhi0_vqmmc>;
 	bus-width = <4>;
 	sd-uhs-sdr50;
 	sd-uhs-sdr104;
 	status = "okay";
 };

 &sdhi0_vqmmc {
 	status = "okay";
 };
 #else
 &sdhi0 {
 	pinctrl-0 = <&sdhi0_emmc_pins>;
 	pinctrl-1 = <&sdhi0_emmc_pins>;
 	pinctrl-names = "default", "state_uhs";

 	vmmc-supply = <&reg_3p3v>;
 	vqmmc-supply = <&reg_1p8v>;
 	bus-width = <8>;
 	mmc-hs200-1_8v;
 	non-removable;
 	fixed-emmc-driver-type = <1>;
 	status = "okay";
 };
 #endif

 &sdhi2 {
 	pinctrl-0 = <&sdhi2_pins>;
 	pinctrl-1 = <&sdhi2_pins>;
 	pinctrl-names = "default", "state_uhs";

 	vmmc-supply = <&reg_3p3v>;
 	vqmmc-supply = <&sdhi2_vqmmc>;
 	bus-width = <4>;
 	sd-uhs-sdr50;
 	sd-uhs-sdr104;
 	status = "okay";
 };

 &sdhi2_vqmmc {
 	status = "okay";
 };

 &wdt1 {
 	status = "okay";
 };

 &xspi {
 	pinctrl-0 = <&xspi_pins>;
 	pinctrl-names = "default";
 	status = "okay";

 	flash@0 {
 		compatible = "jedec,spi-nor";
 		reg = <0>;
 		vcc-supply = <&reg_1p8v>;
 		m25p,fast-read;
 		spi-max-frequency = <50000000>;
 		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>;

 		partitions {
 			compatible = "fixed-partitions";
 			#address-cells = <1>;
 			#size-cells = <1>;

 			partition@0 {
 				label = "bl2";
 				reg = <0x00000000 0x00060000>;
 			};

 			partition@60000 {
 				label = "fip";
 				reg = <0x00060000 0x007a0000>;
 			};

 			partition@800000 {
 				label = "user";
 				reg = <0x800000 0x800000>;
 			};
 		};
 	};
 };
	// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	/*
	* Device Tree Source for the R9A09G047E57 SMARC SoM board.
	*
	* Copyright (C) 2024 Renesas Electronics Corp.
	*/

	/*
	* Please set the below switch position on the SoM and the corresponding macro
	* on the board DTS:
	*
	* Switch position SYS.1, Macro SW_SD0_DEV_SEL:
	* 0 - SD0 is connected to eMMC (default)
	* 1 - SD0 is connected to uSD0 card
	*
	* Switch position SYS.5, Macro SW_LCD_EN:
	* 0 - Select Misc. Signals routing
	* 1 - Select LCD
	*
	* Switch position BOOT.6, Macro SW_PDM_EN:
	* 0 - Select CAN routing
	* 1 - Select PDM
	*/

	/ {
	compatible = "renesas,rzg3e-smarcm", "renesas,r9a09g047e57", "renesas,r9a09g047";

	aliases {
	ethernet0 = &eth0;
	ethernet1 = &eth1;
	i2c2 = &i2c2;
	mmc0 = &sdhi0;
	mmc2 = &sdhi2;
	};

	memory@48000000 {
	device_type = "memory";
	/* First 128MB is reserved for secure area. */
	reg = <0x0 0x48000000 0x0 0xf8000000>;
	};

	reg_1p8v: regulator-1p8v {
	compatible = "regulator-fixed";
	regulator-name = "fixed-1.8V";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
	regulator-boot-on;
	regulator-always-on;
	};

	reg_3p3v: regulator-3p3v {
	compatible = "regulator-fixed";
	regulator-name = "fixed-3.3V";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-boot-on;
	regulator-always-on;
	};

	reg_vdd0p8v_others: regulator-vdd0p8v-others {
	compatible = "regulator-fixed";

	regulator-name = "fixed-0.8V";
	regulator-min-microvolt = <800000>;
	regulator-max-microvolt = <800000>;
	regulator-boot-on;
	regulator-always-on;
	};

	/* 32.768kHz crystal */
	x3: x3-clock {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <32768>;
	};
	};

	&audio_extal_clk {
	clock-frequency = <48000000>;
	};

	&eth0 {
	phy-handle = <&phy0>;
	phy-mode = "rgmii-id";

	pinctrl-0 = <&eth0_pins>;
	pinctrl-names = "default";
	status = "okay";
	};

	&eth1 {
	phy-handle = <&phy1>;
	phy-mode = "rgmii-id";

	pinctrl-0 = <&eth1_pins>;
	pinctrl-names = "default";
	status = "okay";
	};

	&gpu {
	status = "okay";
	mali-supply = <&reg_vdd0p8v_others>;
	};

	&i2c2 {
	pinctrl-0 = <&i2c2_pins>;
	pinctrl-names = "default";
	clock-frequency = <400000>;
	status = "okay";

	raa215300: pmic@12 {
	compatible = "renesas,raa215300";
	reg = <0x12>, <0x6f>;
	reg-names = "main", "rtc";
	clocks = <&x3>;
	clock-names = "xin";

	pinctrl-0 = <&rtc_irq_pin>;
	pinctrl-names = "default";

	interrupts-extended = <&pinctrl RZG3E_GPIO(S, 1) IRQ_TYPE_EDGE_FALLING>;
	};
	};

	&mdio0 {
	phy0: ethernet-phy@7 {
	compatible = "ethernet-phy-id0022.1640",
	"ethernet-phy-ieee802.3-c22";
	reg = <7>;
	interrupts-extended = <&icu 3 IRQ_TYPE_LEVEL_LOW>;
	rxc-skew-psec = <1400>;
	txc-skew-psec = <1400>;
	rxdv-skew-psec = <0>;
	txdv-skew-psec = <0>;
	rxd0-skew-psec = <0>;
	rxd1-skew-psec = <0>;
	rxd2-skew-psec = <0>;
	rxd3-skew-psec = <0>;
	txd0-skew-psec = <0>;
	txd1-skew-psec = <0>;
	txd2-skew-psec = <0>;
	txd3-skew-psec = <0>;
	};
	};

	&mdio1 {
	phy1: ethernet-phy@7 {
	compatible = "ethernet-phy-id0022.1640",
	"ethernet-phy-ieee802.3-c22";
	reg = <7>;
	interrupts-extended = <&icu 16 IRQ_TYPE_LEVEL_LOW>;
	rxc-skew-psec = <1400>;
	txc-skew-psec = <1400>;
	rxdv-skew-psec = <0>;
	txdv-skew-psec = <0>;
	rxd0-skew-psec = <0>;
	rxd1-skew-psec = <0>;
	rxd2-skew-psec = <0>;
	rxd3-skew-psec = <0>;
	txd0-skew-psec = <0>;
	txd1-skew-psec = <0>;
	txd2-skew-psec = <0>;
	txd3-skew-psec = <0>;
	};
	};

	&pinctrl {
	eth0_pins: eth0 {
	clk {
	pinmux = <RZG3E_PORT_PINMUX(B, 1, 1)>; /* TXC */
	output-enable;
	};

	ctrl {
	pinmux = <RZG3E_PORT_PINMUX(A, 1, 1)>, /* MDC */
	<RZG3E_PORT_PINMUX(A, 0, 1)>, /* MDIO */
	<RZG3E_PORT_PINMUX(C, 2, 15)>, /* PHY_INTR (IRQ2) */
	<RZG3E_PORT_PINMUX(C, 1, 1)>, /* RXD3 */
	<RZG3E_PORT_PINMUX(C, 0, 1)>, /* RXD2 */
	<RZG3E_PORT_PINMUX(B, 7, 1)>, /* RXD1 */
	<RZG3E_PORT_PINMUX(B, 6, 1)>, /* RXD0 */
	<RZG3E_PORT_PINMUX(B, 0, 1)>, /* RXC */
	<RZG3E_PORT_PINMUX(A, 2, 1)>, /* RX_CTL */
	<RZG3E_PORT_PINMUX(B, 5, 1)>, /* TXD3 */
	<RZG3E_PORT_PINMUX(B, 4, 1)>, /* TXD2 */
	<RZG3E_PORT_PINMUX(B, 3, 1)>, /* TXD1 */
	<RZG3E_PORT_PINMUX(B, 2, 1)>, /* TXD0 */
	<RZG3E_PORT_PINMUX(A, 3, 1)>; /* TX_CTL */
	};
	};

	eth1_pins: eth1 {
	clk {
	pinmux = <RZG3E_PORT_PINMUX(E, 1, 1)>; /* TXC */
	output-enable;
	};

	ctrl {

	pinmux = <RZG3E_PORT_PINMUX(D, 1, 1)>, /* MDC */
	<RZG3E_PORT_PINMUX(D, 0, 1)>, /* MDIO */
	<RZG3E_PORT_PINMUX(F, 2, 15)>, /* PHY_INTR (IRQ15) */
	<RZG3E_PORT_PINMUX(F, 1, 1)>, /* RXD3 */
	<RZG3E_PORT_PINMUX(F, 0, 1)>, /* RXD2 */
	<RZG3E_PORT_PINMUX(E, 7, 1)>, /* RXD1 */
	<RZG3E_PORT_PINMUX(E, 6, 1)>, /* RXD0 */
	<RZG3E_PORT_PINMUX(E, 0, 1)>, /* RXC */
	<RZG3E_PORT_PINMUX(D, 2, 1)>, /* RX_CTL */
	<RZG3E_PORT_PINMUX(E, 5, 1)>, /* TXD3 */
	<RZG3E_PORT_PINMUX(E, 4, 1)>, /* TXD2 */
	<RZG3E_PORT_PINMUX(E, 3, 1)>, /* TXD1 */
	<RZG3E_PORT_PINMUX(E, 2, 1)>, /* TXD0 */
	<RZG3E_PORT_PINMUX(D, 3, 1)>; /* TX_CTL */
	};
	};

	i2c2_pins: i2c {
	pinmux = <RZG3E_PORT_PINMUX(3, 4, 1)>, /* SCL2 */
	<RZG3E_PORT_PINMUX(3, 5, 1)>; /* SDA2 */
	};

	rtc_irq_pin: rtc-irq {
	pins = "PS1";
	bias-pull-up;
	};

	sdhi0_emmc_pins: sd0-emmc {
	sd0-ctrl {
	pins = "SD0CLK", "SD0CMD";
	renesas,output-impedance = <3>;
	};

	sd0-data {
	pins = "SD0DAT0", "SD0DAT1", "SD0DAT2", "SD0DAT3",
	"SD0DAT4", "SD0DAT5", "SD0DAT6", "SD0DAT7";
	renesas,output-impedance = <3>;
	};

	sd0-rst {
	pins = "SD0RSTN";
	renesas,output-impedance = <3>;
	};
	};

	sdhi0_usd_pins: sd0-usd {
	sd0-cd {
	pinmux = <RZG3E_PORT_PINMUX(5, 0, 8)>;
	};

	sd0-ctrl {
	pins = "SD0CLK", "SD0CMD";
	renesas,output-impedance = <3>;
	};

	sd0-data {
	pins = "SD0DAT0", "SD0DAT1", "SD0DAT2", "SD0DAT3";
	renesas,output-impedance = <3>;
	};

	sd0-iovs {
	pins = "SD0IOVS";
	renesas,output-impedance = <3>;
	};

	sd0-pwen {
	pins = "SD0PWEN";
	renesas,output-impedance = <3>;
	};
	};

	sdhi2_pins: sd2 {
	sd2-cd {
	pinmux = <RZG3E_PORT_PINMUX(K, 0, 1)>; /* SD2CD */
	};

	sd2-ctrl {
	pinmux = <RZG3E_PORT_PINMUX(H, 0, 1)>, /* SD2CLK */
	<RZG3E_PORT_PINMUX(H, 1, 1)>; /* SD2CMD */
	};

	sd2-data {
	pinmux = <RZG3E_PORT_PINMUX(H, 2, 1)>, /* SD2DAT0 */
	<RZG3E_PORT_PINMUX(H, 3, 1)>, /* SD2DAT1 */
	<RZG3E_PORT_PINMUX(H, 4, 1)>, /* SD2DAT2 */
	<RZG3E_PORT_PINMUX(H, 5, 1)>; /* SD2DAT3 */
	};

	sd2-iovs {
	pinmux = <RZG3E_PORT_PINMUX(K, 1, 1)>; /* SD2IOVS */
	};

	sd2-pwen {
	pinmux = <RZG3E_PORT_PINMUX(K, 2, 1)>; /* SD2PWEN */
	};
	};

	xspi_pins: xspi0 {
	pinmux = <RZG3E_PORT_PINMUX(M, 0, 0)>, /* XSPI0_IO0 */
	<RZG3E_PORT_PINMUX(M, 1, 0)>, /* XSPI0_IO1 */
	<RZG3E_PORT_PINMUX(M, 2, 0)>, /* XSPI0_IO2 */
	<RZG3E_PORT_PINMUX(M, 3, 0)>, /* XSPI0_IO3 */
	<RZG3E_PORT_PINMUX(L, 0, 0)>, /* XSPI0_CKP */
	<RZG3E_PORT_PINMUX(L, 1, 0)>; /* XSPI0_CS0 */
	};
	};

	&qextal_clk {
	clock-frequency = <24000000>;
	};

	&rtxin_clk {
	clock-frequency = <32768>;
	};

	#if (SW_SD0_DEV_SEL)
	&sdhi0 {
	pinctrl-0 = <&sdhi0_usd_pins>;
	pinctrl-1 = <&sdhi0_usd_pins>;
	pinctrl-names = "default", "state_uhs";

	vmmc-supply = <&reg_3p3v>;
	vqmmc-supply = <&sdhi0_vqmmc>;
	bus-width = <4>;
	sd-uhs-sdr50;
	sd-uhs-sdr104;
	status = "okay";
	};

	&sdhi0_vqmmc {
	status = "okay";
	};
	#else
	&sdhi0 {
	pinctrl-0 = <&sdhi0_emmc_pins>;
	pinctrl-1 = <&sdhi0_emmc_pins>;
	pinctrl-names = "default", "state_uhs";

	vmmc-supply = <&reg_3p3v>;
	vqmmc-supply = <&reg_1p8v>;
	bus-width = <8>;
	mmc-hs200-1_8v;
	non-removable;
	fixed-emmc-driver-type = <1>;
	status = "okay";
	};
	#endif

	&sdhi2 {
	pinctrl-0 = <&sdhi2_pins>;
	pinctrl-1 = <&sdhi2_pins>;
	pinctrl-names = "default", "state_uhs";

	vmmc-supply = <&reg_3p3v>;
	vqmmc-supply = <&sdhi2_vqmmc>;
	bus-width = <4>;
	sd-uhs-sdr50;
	sd-uhs-sdr104;
	status = "okay";
	};

	&sdhi2_vqmmc {
	status = "okay";
	};

	&wdt1 {
	status = "okay";
	};

	&xspi {
	pinctrl-0 = <&xspi_pins>;
	pinctrl-names = "default";
	status = "okay";

	flash@0 {
	compatible = "jedec,spi-nor";
	reg = <0>;
	vcc-supply = <&reg_1p8v>;
	m25p,fast-read;
	spi-max-frequency = <50000000>;
	spi-tx-bus-width = <4>;
	spi-rx-bus-width = <4>;

	partitions {
	compatible = "fixed-partitions";
	#address-cells = <1>;
	#size-cells = <1>;

	partition@0 {
	label = "bl2";
	reg = <0x00000000 0x00060000>;
	};

	partition@60000 {
	label = "fip";
	reg = <0x00060000 0x007a0000>;
	};

	partition@800000 {
	label = "user";
	reg = <0x800000 0x800000>;
	};
	};
	};
	};