arch/arm64/boot/dts/nvidia/tegra264.dtsi

// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

#include <dt-bindings/clock/nvidia,tegra264.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/tegra186-hsp.h>
#include <dt-bindings/memory/nvidia,tegra264.h>
#include <dt-bindings/reset/nvidia,tegra264.h>

/ {
	compatible = "nvidia,tegra264";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		shmem_bpmp: shmem@86070000 {
			compatible = "nvidia,tegra264-bpmp-shmem";
			reg = <0x0 0x86070000 0x0 0x2000>;
			no-map;
		};
	};

	/* SYSTEM MMIO */
	bus@0 {
		compatible = "simple-bus";

		#address-cells = <2>;
		#size-cells = <2>;

		ranges = <0x00 0x00000000 0x00 0x00000000 0x01 0x00000000>;

		misc@100000 {
			compatible = "nvidia,tegra234-misc";
			reg = <0x0 0x00100000 0x0 0x0f000>,
			      <0x0 0x0c140000 0x0 0x10000>;
		};

		timer@8000000 {
			compatible = "nvidia,tegra234-timer";
			reg = <0x0 0x08000000 0x0 0x140000>;
			interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 776 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		gpcdma: dma-controller@8400000 {
			compatible = "nvidia,tegra264-gpcdma", "nvidia,tegra186-gpcdma";
			reg = <0x0 0x08400000 0x0 0x210000>;
			interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 611 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 612 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 615 IRQ_TYPE_LEVEL_HIGH>;
			#dma-cells = <1>;
			iommus = <&smmu1 0x00000800>;
			dma-coherent;
			dma-channel-mask = <0xfffffffe>;
			status = "disabled";
		};

		hsp_top: hsp@8800000 {
			compatible = "nvidia,tegra264-hsp";
			reg = <0x0 0x08800000 0x0 0xd0000>;
			interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 622 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 623 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 624 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 626 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 637 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "doorbell", "shared0", "shared1", "shared2",
					  "shared3", "shared4", "shared5", "shared6",
					  "shared7";
			#mbox-cells = <2>;
		};

		rtc: rtc@c2c0000 {
			compatible = "nvidia,tegra264-rtc", "nvidia,tegra20-rtc";
			reg = <0x0 0x0c2c0000 0x0 0x10000>;
			interrupt-parent = <&pmc>;
			interrupts = <65 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&bpmp TEGRA264_CLK_CLK_S>;
			clock-names = "rtc";
			status = "disabled";
		};

		serial@c4e0000 {
			compatible = "nvidia,tegra264-utc";
			reg = <0x0 0x0c4e0000 0x0 0x8000>,
			      <0x0 0x0c4e8000 0x0 0x8000>;
			reg-names = "tx", "rx";
			interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>;
			rx-threshold = <4>;
			tx-threshold = <4>;
			status = "disabled";
		};

		serial@c5a0000 {
			compatible = "nvidia,tegra264-utc";
			reg = <0x0 0x0c5a0000 0x0 0x8000>,
			      <0x0 0x0c5a8000 0x0 0x8000>;
			reg-names = "tx", "rx";
			interrupts = <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>;
			rx-threshold = <4>;
			tx-threshold = <4>;
			status = "disabled";
		};

		uart0: serial@c5f0000 {
			compatible = "arm,sbsa-uart";
			reg = <0x0 0x0c5f0000 0x0 0x10000>;
			interrupts = <GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		i2c2: i2c@c600000 {
			compatible = "nvidia,tegra264-i2c";
			reg = <0x0 0x0c600000 0x0 0x10000>;
			interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <400000>;
			clocks = <&bpmp TEGRA264_CLK_AON_I2C>,
				 <&bpmp TEGRA264_CLK_PLLAON>;
			clock-names = "div-clk", "parent";
			assigned-clocks = <&bpmp TEGRA264_CLK_AON_I2C>;
			assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLAON>;
			resets = <&bpmp TEGRA264_RESET_I2C2>;
			reset-names = "i2c";
			status = "disabled";
		};

		i2c3: i2c@c610000 {
			compatible = "nvidia,tegra264-i2c";
			reg = <0x0 0x0c610000 0x0 0x10000>;
			interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <400000>;
			clocks = <&bpmp TEGRA264_CLK_AON_I2C>,
				 <&bpmp TEGRA264_CLK_PLLAON>;
			clock-names = "div-clk", "parent";
			assigned-clocks = <&bpmp TEGRA264_CLK_AON_I2C>;
			assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLAON>;
			resets = <&bpmp TEGRA264_RESET_I2C3>;
			reset-names = "i2c";
			status = "disabled";
		};

		pmc: pmc@c800000 {
			compatible = "nvidia,tegra264-pmc";
			reg = <0x0 0x0c800000 0x0 0x100000>,
			      <0x0 0x0c990000 0x0 0x10000>,
			      <0x0 0x0ca00000 0x0 0x10000>,
			      <0x0 0x0c980000 0x0 0x10000>,
			      <0x0 0x0c9c0000 0x0 0x40000>;
			reg-names = "pmc", "wake", "aotag", "scratch", "misc";
			#interrupt-cells = <2>;
			interrupt-controller;
		};
	};

	/* TOP_MMIO */
	bus@8100000000 {
		compatible = "simple-bus";

		#address-cells = <2>;
		#size-cells = <2>;

		ranges = <0x00 0x00000000 0x81 0x00000000 0x01 0x00000000>, /* MMIO */
			 <0x01 0x00000000 0x00 0x20000000 0x00 0x40000000>, /* non-prefetchable memory (32-bit) */
			 <0x02 0x00000000 0xd0 0x00000000 0x08 0x80000000>; /* ECAM, prefetchable memory, I/O */

		smmu1: iommu@5000000 {
			compatible = "arm,smmu-v3";
			reg = <0x00 0x5000000 0x0 0x200000>;
			interrupts = <GIC_SPI 12 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 13 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "eventq", "gerror";
			status = "disabled";

			#iommu-cells = <1>;
			dma-coherent;
		};

		smmu2: iommu@6000000 {
			compatible = "arm,smmu-v3";
			reg = <0x00 0x6000000 0x0 0x200000>;
			interrupts = <GIC_SPI 1 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "eventq", "gerror";
			status = "disabled";

			#iommu-cells = <1>;
			dma-coherent;
		};

		mc: memory-controller@8020000 {
			compatible = "nvidia,tegra264-mc";
			reg = <0x00 0x8020000 0x0 0x20000>, /* MC broadcast */
			      <0x00 0x8040000 0x0 0x20000>, /* MC  0 */
			      <0x00 0x8060000 0x0 0x20000>, /* MC  1 */
			      <0x00 0x8080000 0x0 0x20000>, /* MC  2 */
			      <0x00 0x80a0000 0x0 0x20000>, /* MC  3 */
			      <0x00 0x80c0000 0x0 0x20000>, /* MC  4 */
			      <0x00 0x80e0000 0x0 0x20000>, /* MC  5 */
			      <0x00 0x8100000 0x0 0x20000>, /* MC  6 */
			      <0x00 0x8120000 0x0 0x20000>, /* MC  7 */
			      <0x00 0x8140000 0x0 0x20000>, /* MC  8 */
			      <0x00 0x8160000 0x0 0x20000>, /* MC  9 */
			      <0x00 0x8180000 0x0 0x20000>, /* MC 10 */
			      <0x00 0x81a0000 0x0 0x20000>, /* MC 11 */
			      <0x00 0x81c0000 0x0 0x20000>, /* MC 12 */
			      <0x00 0x81e0000 0x0 0x20000>, /* MC 13 */
			      <0x00 0x8200000 0x0 0x20000>, /* MC 14 */
			      <0x00 0x8220000 0x0 0x20000>; /* MC 15 */
			reg-names = "broadcast", "ch0", "ch1", "ch2", "ch3",
				    "ch4", "ch5", "ch6", "ch7", "ch8", "ch9",
				    "ch10", "ch11", "ch12", "ch13", "ch14",
				    "ch15";
			interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
			#interconnect-cells = <1>;

			#address-cells = <2>;
			#size-cells = <2>;

			/* limit the DMA range for memory clients to [39:0] */
			dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;

			emc: external-memory-controller@8800000 {
				compatible = "nvidia,tegra264-emc";
				reg = <0x00 0x8800000 0x0 0x20000>,
				      <0x00 0x8890000 0x0 0x20000>;
				interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&bpmp TEGRA264_CLK_EMC>;
				clock-names = "emc";

				#interconnect-cells = <0>;
				nvidia,bpmp = <&bpmp>;
			};
		};

		smmu0: iommu@a000000 {
			compatible = "arm,smmu-v3";
			reg = <0x00 0xa000000 0x0 0x200000>;
			interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "eventq", "gerror";
			status = "disabled";

			#iommu-cells = <1>;
			dma-coherent;
		};

		smmu4: iommu@b000000 {
			compatible = "arm,smmu-v3";
			reg = <0x00 0xb000000 0x0 0x200000>;
			interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "eventq", "gerror";
			status = "disabled";

			#iommu-cells = <1>;
			dma-coherent;
		};

		i2c14: i2c@c410000 {
			compatible = "nvidia,tegra264-i2c";
			reg = <0x00 0x0c410000 0x0 0x10000>;
			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <400000>;
			clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
				 <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			clock-names = "div-clk", "parent";
			assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>;
			assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			resets = <&bpmp TEGRA264_RESET_I2C14>;
			reset-names = "i2c";
			status = "disabled";
		};

		i2c15: i2c@c420000 {
			compatible = "nvidia,tegra264-i2c";
			reg = <0x00 0x0c420000 0x0 0x10000>;
			interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <400000>;
			clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
				 <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			clock-names = "div-clk", "parent";
			assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>;
			assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			resets = <&bpmp TEGRA264_RESET_I2C15>;
			reset-names = "i2c";
			status = "disabled";
		};

		i2c16: i2c@c430000 {
			compatible = "nvidia,tegra264-i2c";
			reg = <0x00 0x0c430000 0x0 0x10000>;
			interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <400000>;
			clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
				 <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			clock-names = "div-clk", "parent";
			assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>;
			assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			resets = <&bpmp TEGRA264_RESET_I2C16>;
			reset-names = "i2c";
			status = "disabled";
		};

		i2c0: i2c@c630000 {
			compatible = "nvidia,tegra264-i2c";
			reg = <0x00 0x0c630000 0x0 0x10000>;
			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <400000>;
			clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
				 <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			clock-names = "div-clk", "parent";
			assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>;
			assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			resets = <&bpmp TEGRA264_RESET_I2C0>;
			reset-names = "i2c";
			status = "disabled";
		};

		i2c1: i2c@c640000 {
			compatible = "nvidia,tegra264-i2c";
			reg = <0x00 0x0c640000 0x0 0x10000>;
			interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <400000>;
			clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
				 <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			clock-names = "div-clk", "parent";
			assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>;
			assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			resets = <&bpmp TEGRA264_RESET_I2C1>;
			reset-names = "i2c";
			status = "disabled";
		};

		i2c4: i2c@c650000 {
			compatible = "nvidia,tegra264-i2c";
			reg = <0x00 0x0c650000 0x0 0x10000>;
			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <400000>;
			clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
				 <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			clock-names = "div-clk", "parent";
			assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>;
			assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			resets = <&bpmp TEGRA264_RESET_I2C4>;
			reset-names = "i2c";
			status = "disabled";
		};

		i2c6: i2c@c670000 {
			compatible = "nvidia,tegra264-i2c";
			reg = <0x00 0x0c670000 0x0 0x10000>;
			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <400000>;
			clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
				 <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			clock-names = "div-clk", "parent";
			assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>;
			assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			resets = <&bpmp TEGRA264_RESET_I2C6>;
			reset-names = "i2c";
			status = "disabled";
		};

		i2c7: i2c@c680000 {
			compatible = "nvidia,tegra264-i2c";
			reg = <0x00 0x0c680000 0x0 0x10000>;
			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <400000>;
			clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
				 <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			clock-names = "div-clk", "parent";
			assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>;
			assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			resets = <&bpmp TEGRA264_RESET_I2C7>;
			reset-names = "i2c";
			status = "disabled";
		};

		i2c8: i2c@c690000 {
			compatible = "nvidia,tegra264-i2c";
			reg = <0x00 0x0c690000 0x0 0x10000>;
			interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <400000>;
			clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
				 <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			clock-names = "div-clk", "parent";
			assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>;
			assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			resets = <&bpmp TEGRA264_RESET_I2C8>;
			reset-names = "i2c";
			status = "disabled";
		};

		i2c9: i2c@c6a0000 {
			compatible = "nvidia,tegra264-i2c";
			reg = <0x00 0x0c6a0000 0x0 0x10000>;
			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <400000>;
			clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
				 <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			clock-names = "div-clk", "parent";
			assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>;
			assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			resets = <&bpmp TEGRA264_RESET_I2C9>;
			reset-names = "i2c";
			status = "disabled";
		};

		i2c10: i2c@c6b0000 {
			compatible = "nvidia,tegra264-i2c";
			reg = <0x00 0x0c6b0000 0x0 0x10000>;
			interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <400000>;
			clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
				 <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			clock-names = "div-clk", "parent";
			assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>;
			assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			resets = <&bpmp TEGRA264_RESET_I2C10>;
			reset-names = "i2c";
			status = "disabled";
		};

		i2c11: i2c@c6c0000 {
			compatible = "nvidia,tegra264-i2c";
			reg = <0x00 0x0c6c0000 0x0 0x10000>;
			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <400000>;
			clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
				 <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			clock-names = "div-clk", "parent";
			assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>;
			assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			resets = <&bpmp TEGRA264_RESET_I2C11>;
			reset-names = "i2c";
			status = "disabled";
		};

		i2c12: i2c@c6d0000 {
			compatible = "nvidia,tegra264-i2c";
			reg = <0x00 0x0c6d0000 0x0 0x10000>;
			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <400000>;
			clocks = <&bpmp TEGRA264_CLK_TOP_I2C>,
				 <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			clock-names = "div-clk", "parent";
			assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>;
			assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>;
			resets = <&bpmp TEGRA264_RESET_I2C12>;
			reset-names = "i2c";
			status = "disabled";
		};

		gic: interrupt-controller@46000000 {
			compatible = "arm,gic-v3";
			reg = <0x00 0x46000000 0x0 0x010000>, /* GICD */
			      <0x00 0x46080000 0x0 0x400000>; /* GICR */
			interrupt-parent = <&gic>;
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;

			redistributor-stride = <0x0 0x40000>;
			#redistributor-regions = <1>;
			#interrupt-cells = <3>;
			interrupt-controller;

			#address-cells = <2>;
			#size-cells = <2>;

			ranges = <0x0 0x0 0x00 0x46000000 0x0 0x1000000>;

			its: msi-controller@40000 {
				compatible = "arm,gic-v3-its";
				reg = <0x0 0x40000 0x0 0x40000>;
				#msi-cells = <1>;
				msi-controller;
			};
		};
	};

	/* DISP_USB MMIO */
	bus@8800000000 {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;

		ranges = <0x00 0x00000000 0x88 0x00000000 0x01 0x00000000>;

		smmu3: iommu@6000000 {
			compatible = "arm,smmu-v3";
			reg = <0x00 0x6000000 0x0 0x200000>;
			interrupts = <GIC_SPI 225 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 226 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "eventq", "gerror";
			status = "disabled";

			#iommu-cells = <1>;
			dma-coherent;
		};
	};

	/* UPHY MMIO */
	bus@a800000000 {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;

		ranges = <0x00 0x00000000 0xa8 0x00000000 0x40 0x00000000>, /* MMIO, ECAM, prefetchable memory, I/O */
			 <0x80 0x00000000 0x00 0x20000000 0x00 0x40000000>; /* non-prefetchable memory (32-bit) */
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,armv8";
			device_type = "cpu";
			reg = <0x00000>;
			status = "okay";

			enable-method = "psci";

			i-cache-size = <65536>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <65536>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
		};

		cpu1: cpu@1 {
			compatible = "arm,armv8";
			device_type = "cpu";
			reg = <0x10000>;
			status = "okay";

			enable-method = "psci";

			i-cache-size = <65536>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <65536>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
		};
	};

	bpmp: bpmp {
		compatible = "nvidia,tegra264-bpmp", "nvidia,tegra186-bpmp";
		mboxes = <&hsp_top TEGRA_HSP_MBOX_TYPE_DB
				   TEGRA_HSP_DB_MASTER_BPMP>;
		memory-region = <&shmem_bpmp>;
		#clock-cells = <1>;
		#reset-cells = <1>;
		#power-domain-cells = <1>;

		i2c {
			compatible = "nvidia,tegra186-bpmp-i2c";
			nvidia,bpmp-bus-id = <5>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		thermal {
			compatible = "nvidia,tegra186-bpmp-thermal";
			#thermal-sensor-cells = <1>;
		};
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
		status = "okay";
	};

	psci {
		compatible = "arm,psci-1.0";
		status = "okay";
		method = "smc";
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
		status = "okay";
	};
};