Documentation/devicetree/bindings/net/ti,dp83822.yaml

# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
# Copyright (C) 2020 Texas Instruments Incorporated
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/ti,dp83822.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: TI DP83822 ethernet PHY

maintainers:
  - Andrew Davis <afd@ti.com>

description: |
  The DP83822 is a low-power, single-port, 10/100 Mbps Ethernet PHY. It
  provides all of the physical layer functions needed to transmit and receive
  data over standard, twisted-pair cables or to connect to an external,
  fiber-optic transceiver. Additionally, the DP83822 provides flexibility to
  connect to a MAC through a standard MII, RMII, or RGMII interface

  Specifications about the Ethernet PHY can be found at:
    http://www.ti.com/lit/ds/symlink/dp83822i.pdf

allOf:
  - $ref: ethernet-phy.yaml#

properties:
  reg:
    maxItems: 1

  ti,link-loss-low:
    type: boolean
    description: |
       DP83822 PHY in Fiber mode only.
       Sets the DP83822 to detect a link drop condition when the signal goes
       high.  If not set then link drop will occur when the signal goes low.
       This property is only applicable if the fiber mode support is strapped
       to on.

  ti,fiber-mode:
    type: boolean
    description: |
       DP83822 PHY only.
       If present the DP83822 PHY is configured to operate in fiber mode
       Fiber mode support can also be strapped. If the strap pin is not set
       correctly or not set at all then this boolean can be used to enable it.
       If the fiber mode is not strapped then signal detection for the PHY
       is disabled.
       In fiber mode, auto-negotiation is disabled and the PHY can only work in
       100base-fx (full and half duplex) modes.

  rx-internal-delay-ps:
    description: |
       DP83822 PHY only.
       Setting this property to a non-zero number sets the RX internal delay
       for the PHY.  The internal delay for the PHY is fixed to 3.5ns relative
       to receive data.

  tx-internal-delay-ps:
    description: |
       DP83822 PHY only.
       Setting this property to a non-zero number sets the TX internal delay
       for the PHY.  The internal delay for the PHY is fixed to 3.5ns relative
       to transmit data.

  ti,cfg-dac-minus-one-bp:
    description: |
       DP83826 PHY only.
       Sets the voltage ratio (with respect to the nominal value)
       of the logical level -1 for the MLT-3 encoded TX data.
    enum: [5000, 5625, 6250, 6875, 7500, 8125, 8750, 9375, 10000,
           10625, 11250, 11875, 12500, 13125, 13750, 14375, 15000]
    default: 10000

  ti,cfg-dac-plus-one-bp:
    description: |
       DP83826 PHY only.
       Sets the voltage ratio (with respect to the nominal value)
       of the logical level +1 for the MLT-3 encoded TX data.
    enum: [5000, 5625, 6250, 6875, 7500, 8125, 8750, 9375, 10000,
           10625, 11250, 11875, 12500, 13125, 13750, 14375, 15000]
    default: 10000

  ti,rmii-mode:
    description: |
       If present, select the RMII operation mode. Two modes are
       available:
         - RMII master, where the PHY outputs a 50MHz reference clock which can
         be connected to the MAC.
         - RMII slave, where the PHY expects a 50MHz reference clock input
         shared with the MAC.
       The RMII operation mode can also be configured by its straps.
       If the strap pin is not set correctly or not set at all, then this can be
       used to configure it.
    $ref: /schemas/types.yaml#/definitions/string
    enum:
      - master
      - slave

  ti,gpio2-clk-out:
    description: |
       DP83822 PHY only.
       The GPIO2 pin on the DP83822 can be configured as clock output. When
       omitted, the PHY's default will be left as is.

       - 'mac-if': In MII mode the clock frequency is 25-MHz, in RMII Mode the
         clock frequency is 50-MHz and in RGMII Mode the clock frequency is
         25-MHz.
       - 'xi': XI clock(pass-through clock from XI pin).
       - 'int-ref': Internal reference clock 25-MHz.
       - 'rmii-master-mode-ref': RMII master mode reference clock 50-MHz. RMII
         master mode reference clock is identical to MAC IF clock in RMII master
         mode.
       - 'free-running': Free running clock 125-MHz.
       - 'recovered': Recovered clock is a 125-MHz recovered clock from a
         connected link partner.
    $ref: /schemas/types.yaml#/definitions/string
    enum:
      - mac-if
      - xi
      - int-ref
      - rmii-master-mode-ref
      - free-running
      - recovered

  mac-termination-ohms:
    enum: [43, 44, 46, 48, 50, 53, 55, 58, 61, 65, 69, 73, 78, 84, 91, 99]

required:
  - reg

unevaluatedProperties: false

examples:
  - |
    mdio0 {
      #address-cells = <1>;
      #size-cells = <0>;
      ethphy0: ethernet-phy@0 {
        reg = <0>;
        rx-internal-delay-ps = <1>;
        tx-internal-delay-ps = <1>;
        ti,gpio2-clk-out = "xi";
        mac-termination-ohms = <43>;
      };
    };

...