Documentation/devicetree/bindings/clock/rockchip,rk3528-cru.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/rockchip,rk3528-cru.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip RK3528 Clock and Reset Controller

maintainers:
  - Yao Zi <ziyao@disroot.org>

description: |
  The RK3528 clock controller generates the clock and also implements a reset
  controller for SoC peripherals. For example, it provides SCLK_UART0 and
  PCLK_UART0 as well as SRST_P_UART0 and SRST_S_UART0 for the first UART
  module.
  Each clock is assigned an identifier, consumer nodes can use it to specify
  the clock. All available clock and reset IDs are defined in dt-binding
  headers.

properties:
  compatible:
    const: rockchip,rk3528-cru

  reg:
    maxItems: 1

  clocks:
    items:
      - description: External 24MHz oscillator clock
      - description: >
          50MHz clock generated by PHY module, for generating GMAC0 clocks only.

  clock-names:
    items:
      - const: xin24m
      - const: gmac0

  "#clock-cells":
    const: 1

  "#reset-cells":
    const: 1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - "#clock-cells"
  - "#reset-cells"

additionalProperties: false

examples:
  - |
    clock-controller@ff4a0000 {
        compatible = "rockchip,rk3528-cru";
        reg = <0xff4a0000 0x30000>;
        clocks = <&xin24m>, <&gmac0_clk>;
        clock-names = "xin24m", "gmac0";
        #clock-cells = <1>;
        #reset-cells = <1>;
    };