| /* SPDX-License-Identifier: GPL-2.0+ */ | |
| #ifndef __DT_BINDINGS_RESET_BCM63268_H | |
| #define __DT_BINDINGS_RESET_BCM63268_H | |
| #define BCM63268_RST_SPI 0 | |
| #define BCM63268_RST_IPSEC 1 | |
| #define BCM63268_RST_EPHY 2 | |
| #define BCM63268_RST_SAR 3 | |
| #define BCM63268_RST_ENETSW 4 | |
| #define BCM63268_RST_USBS 5 | |
| #define BCM63268_RST_USBH 6 | |
| #define BCM63268_RST_PCM 7 | |
| #define BCM63268_RST_PCIE_CORE 8 | |
| #define BCM63268_RST_PCIE 9 | |
| #define BCM63268_RST_PCIE_EXT 10 | |
| #define BCM63268_RST_WLAN_SHIM 11 | |
| #define BCM63268_RST_DDR_PHY 12 | |
| #define BCM63268_RST_FAP0 13 | |
| #define BCM63268_RST_WLAN_UBUS 14 | |
| #define BCM63268_RST_DECT 15 | |
| #define BCM63268_RST_FAP1 16 | |
| #define BCM63268_RST_PCIE_HARD 17 | |
| #define BCM63268_RST_GPHY 18 | |
| #define BCM63268_TRST_SW 29 | |
| #define BCM63268_TRST_HW 30 | |
| #define BCM63268_TRST_POR 31 | |
| #endif /* __DT_BINDINGS_RESET_BCM63268_H */ |