| /* SPDX-License-Identifier: GPL-2.0 */ | |
| #ifndef DT_BINDINGS_MEMORY_TEGRA114_MC_H | |
| #define DT_BINDINGS_MEMORY_TEGRA114_MC_H | |
| #define TEGRA_SWGROUP_PTC 0 | |
| #define TEGRA_SWGROUP_DC 1 | |
| #define TEGRA_SWGROUP_DCB 2 | |
| #define TEGRA_SWGROUP_EPP 3 | |
| #define TEGRA_SWGROUP_G2 4 | |
| #define TEGRA_SWGROUP_AVPC 5 | |
| #define TEGRA_SWGROUP_NV 6 | |
| #define TEGRA_SWGROUP_HDA 7 | |
| #define TEGRA_SWGROUP_HC 8 | |
| #define TEGRA_SWGROUP_MSENC 9 | |
| #define TEGRA_SWGROUP_PPCS 10 | |
| #define TEGRA_SWGROUP_VDE 11 | |
| #define TEGRA_SWGROUP_MPCORELP 12 | |
| #define TEGRA_SWGROUP_MPCORE 13 | |
| #define TEGRA_SWGROUP_VI 14 | |
| #define TEGRA_SWGROUP_ISP 15 | |
| #define TEGRA_SWGROUP_XUSB_HOST 16 | |
| #define TEGRA_SWGROUP_XUSB_DEV 17 | |
| #define TEGRA_SWGROUP_EMUCIF 18 | |
| #define TEGRA_SWGROUP_TSEC 19 | |
| #define TEGRA114_MC_RESET_AVPC 0 | |
| #define TEGRA114_MC_RESET_DC 1 | |
| #define TEGRA114_MC_RESET_DCB 2 | |
| #define TEGRA114_MC_RESET_EPP 3 | |
| #define TEGRA114_MC_RESET_2D 4 | |
| #define TEGRA114_MC_RESET_HC 5 | |
| #define TEGRA114_MC_RESET_HDA 6 | |
| #define TEGRA114_MC_RESET_ISP 7 | |
| #define TEGRA114_MC_RESET_MPCORE 8 | |
| #define TEGRA114_MC_RESET_MPCORELP 9 | |
| #define TEGRA114_MC_RESET_MPE 10 | |
| #define TEGRA114_MC_RESET_3D 11 | |
| #define TEGRA114_MC_RESET_3D2 12 | |
| #define TEGRA114_MC_RESET_PPCS 13 | |
| #define TEGRA114_MC_RESET_VDE 14 | |
| #define TEGRA114_MC_RESET_VI 15 | |
| #define TEGRA114_MC_PTCR 0 | |
| #define TEGRA114_MC_DISPLAY0A 1 | |
| #define TEGRA114_MC_DISPLAY0AB 2 | |
| #define TEGRA114_MC_DISPLAY0B 3 | |
| #define TEGRA114_MC_DISPLAY0BB 4 | |
| #define TEGRA114_MC_DISPLAY0C 5 | |
| #define TEGRA114_MC_DISPLAY0CB 6 | |
| #define TEGRA114_MC_DISPLAY1B 7 | |
| #define TEGRA114_MC_DISPLAY1BB 8 | |
| #define TEGRA114_MC_EPPUP 9 | |
| #define TEGRA114_MC_G2PR 10 | |
| #define TEGRA114_MC_G2SR 11 | |
| #define TEGRA114_MC_MPEUNIFBR 12 | |
| #define TEGRA114_MC_VIRUV 13 | |
| #define TEGRA114_MC_AFIR 14 | |
| #define TEGRA114_MC_AVPCARM7R 15 | |
| #define TEGRA114_MC_DISPLAYHC 16 | |
| #define TEGRA114_MC_DISPLAYHCB 17 | |
| #define TEGRA114_MC_FDCDRD 18 | |
| #define TEGRA114_MC_FDCDRD2 19 | |
| #define TEGRA114_MC_G2DR 20 | |
| #define TEGRA114_MC_HDAR 21 | |
| #define TEGRA114_MC_HOST1XDMAR 22 | |
| #define TEGRA114_MC_HOST1XR 23 | |
| #define TEGRA114_MC_IDXSRD 24 | |
| #define TEGRA114_MC_IDXSRD2 25 | |
| #define TEGRA114_MC_MPE_IPRED 26 | |
| #define TEGRA114_MC_MPEAMEMRD 27 | |
| #define TEGRA114_MC_MPECSRD 28 | |
| #define TEGRA114_MC_PPCSAHBDMAR 29 | |
| #define TEGRA114_MC_PPCSAHBSLVR 30 | |
| #define TEGRA114_MC_SATAR 31 | |
| #define TEGRA114_MC_TEXSRD 32 | |
| #define TEGRA114_MC_TEXSRD2 33 | |
| #define TEGRA114_MC_VDEBSEVR 34 | |
| #define TEGRA114_MC_VDEMBER 35 | |
| #define TEGRA114_MC_VDEMCER 36 | |
| #define TEGRA114_MC_VDETPER 37 | |
| #define TEGRA114_MC_MPCORELPR 38 | |
| #define TEGRA114_MC_MPCORER 39 | |
| #define TEGRA114_MC_EPPU 40 | |
| #define TEGRA114_MC_EPPV 41 | |
| #define TEGRA114_MC_EPPY 42 | |
| #define TEGRA114_MC_MPEUNIFBW 43 | |
| #define TEGRA114_MC_VIWSB 44 | |
| #define TEGRA114_MC_VIWU 45 | |
| #define TEGRA114_MC_VIWV 46 | |
| #define TEGRA114_MC_VIWY 47 | |
| #define TEGRA114_MC_G2DW 48 | |
| #define TEGRA114_MC_AFIW 49 | |
| #define TEGRA114_MC_AVPCARM7W 50 | |
| #define TEGRA114_MC_FDCDWR 51 | |
| #define TEGRA114_MC_FDCDWR2 52 | |
| #define TEGRA114_MC_HDAW 53 | |
| #define TEGRA114_MC_HOST1XW 54 | |
| #define TEGRA114_MC_ISPW 55 | |
| #define TEGRA114_MC_MPCORELPW 56 | |
| #define TEGRA114_MC_MPCOREW 57 | |
| #define TEGRA114_MC_MPECSWR 58 | |
| #define TEGRA114_MC_PPCSAHBDMAW 59 | |
| #define TEGRA114_MC_PPCSAHBSLVW 60 | |
| #define TEGRA114_MC_SATAW 61 | |
| #define TEGRA114_MC_VDEBSEVW 62 | |
| #define TEGRA114_MC_VDEDBGW 63 | |
| #define TEGRA114_MC_VDEMBEW 64 | |
| #define TEGRA114_MC_VDETPMW 65 | |
| #endif |