drivers/gpu/drm/xe/xe_lrc.h

/* SPDX-License-Identifier: MIT */
/*
 * Copyright © 2021 Intel Corporation
 */
#ifndef _XE_LRC_H_
#define _XE_LRC_H_

#include <linux/types.h>

#include "xe_lrc_types.h"

/*
 * Sentinel value stored in lrc->ctx_timestamp while a context is starting.
 * The hardware hasn't yet written the real CTX_TIMESTAMP, so this is not a
 * valid elapsed-time sample and must not be used as one.
 */
#define XE_LRC_CTX_TIMESTAMP_ACTIVE 1ULL

struct drm_printer;
struct xe_bb;
struct xe_device;
struct xe_exec_queue;
enum xe_multi_queue_priority;
enum xe_engine_class;
struct xe_gt;
struct xe_hw_engine;
struct xe_lrc;
struct xe_vm;

struct xe_lrc_snapshot {
	struct xe_bo *lrc_bo;
	void *lrc_snapshot;
	unsigned long lrc_size, lrc_offset;
	unsigned long replay_size, replay_offset;

	u32 context_desc;
	u32 ring_addr;
	u32 indirect_context_desc;
	u32 head;
	u32 start;
	struct {
		u32 internal;
		u32 memory;
	} tail;
	u32 start_seqno;
	u32 seqno;
	u64 ctx_timestamp;
	u64 ctx_timestamp_ms;
	u64 queue_timestamp;
	u64 queue_timestamp_ms;
	u32 ctx_job_timestamp;
};

#define LRC_PPHWSP_FLUSH_INVAL_SCRATCH_ADDR (0x34 * 4)
#define LRC_PPHWSP_PXP_INVAL_SCRATCH_ADDR (0x40 * 4)

#define LRC_WA_BB_SIZE SZ_4K

#define XE_LRC_CREATE_RUNALONE		BIT(0)
#define XE_LRC_CREATE_PXP		BIT(1)
#define XE_LRC_CREATE_USER_CTX		BIT(2)
#define XE_LRC_DISABLE_STATE_CACHE_PERF_FIX	BIT(3)

struct xe_lrc *xe_lrc_create(struct xe_hw_engine *hwe, struct xe_vm *vm,
			     void *replay_state, u32 ring_size, u16 msix_vec, u32 flags);
void xe_lrc_destroy(struct kref *ref);

/**
 * xe_lrc_get - Get reference to the LRC
 * @lrc: Logical Ring Context
 *
 * Increment reference count of @lrc
 */
static inline struct xe_lrc *xe_lrc_get(struct xe_lrc *lrc)
{
	kref_get(&lrc->refcount);
	return lrc;
}

/**
 * xe_lrc_put - Put reference of the LRC
 * @lrc: Logical Ring Context
 *
 * Decrement reference count of @lrc, call xe_lrc_destroy when
 * reference count reaches 0.
 */
static inline void xe_lrc_put(struct xe_lrc *lrc)
{
	if (lrc)
		kref_put(&lrc->refcount, xe_lrc_destroy);
}

/**
 * xe_lrc_ring_size() - Xe LRC ring size
 *
 * Return: Size of LRC ring buffer
 */
static inline size_t xe_lrc_ring_size(void)
{
	return SZ_16K;
}

static inline bool xe_lrc_is_multi_queue(struct xe_lrc *lrc)
{
	return lrc->multi_queue.primary_lrc;
}

size_t xe_gt_lrc_hang_replay_size(struct xe_gt *gt, enum xe_engine_class class);
size_t xe_gt_lrc_size(struct xe_gt *gt, enum xe_engine_class class);
u32 xe_lrc_pphwsp_offset(struct xe_lrc *lrc);
u32 xe_lrc_regs_offset(struct xe_lrc *lrc);

void xe_lrc_set_ring_tail(struct xe_lrc *lrc, u32 tail);
u32 xe_lrc_ring_tail(struct xe_lrc *lrc);
void xe_lrc_set_ring_head(struct xe_lrc *lrc, u32 head);
u32 xe_lrc_ring_head(struct xe_lrc *lrc);
u32 xe_lrc_ring_space(struct xe_lrc *lrc);
void xe_lrc_write_ring(struct xe_lrc *lrc, const void *data, size_t size);

bool xe_lrc_ring_is_idle(struct xe_lrc *lrc);

u32 xe_lrc_indirect_ring_ggtt_addr(struct xe_lrc *lrc);
u32 xe_lrc_ggtt_addr(struct xe_lrc *lrc);
u32 *xe_lrc_regs(struct xe_lrc *lrc);
void xe_lrc_update_hwctx_regs_with_address(struct xe_lrc *lrc);
void xe_default_lrc_update_memirq_regs_with_address(struct xe_hw_engine *hwe);
void xe_lrc_update_memirq_regs_with_address(struct xe_lrc *lrc, struct xe_hw_engine *hwe,
					    u32 *regs);

u32 xe_lrc_read_ctx_reg(struct xe_lrc *lrc, int reg_nr);
void xe_lrc_write_ctx_reg(struct xe_lrc *lrc, int reg_nr, u32 val);

u64 xe_lrc_descriptor(struct xe_lrc *lrc);

u32 xe_lrc_seqno_ggtt_addr(struct xe_lrc *lrc);
struct dma_fence *xe_lrc_alloc_seqno_fence(void);
void xe_lrc_free_seqno_fence(struct dma_fence *fence);
void xe_lrc_init_seqno_fence(struct xe_lrc *lrc, struct dma_fence *fence);
s32 xe_lrc_seqno(struct xe_lrc *lrc);

u32 xe_lrc_start_seqno_ggtt_addr(struct xe_lrc *lrc);
s32 xe_lrc_start_seqno(struct xe_lrc *lrc);

u32 xe_lrc_parallel_ggtt_addr(struct xe_lrc *lrc);
struct iosys_map xe_lrc_parallel_map(struct xe_lrc *lrc);

size_t xe_lrc_reg_size(struct xe_device *xe);
size_t xe_lrc_engine_state_size(struct xe_gt *gt, enum xe_engine_class class);

void xe_lrc_dump_default(struct drm_printer *p,
			 struct xe_gt *gt,
			 enum xe_engine_class);
int xe_lrc_lookup_default_reg_value(struct xe_gt *gt,
				    enum xe_engine_class hwe_class,
				    u32 offset,
				    u32 *value);

u32 *xe_lrc_emit_hwe_state_instructions(struct xe_exec_queue *q, u32 *cs);

void xe_lrc_set_multi_queue_priority(struct xe_lrc *lrc, enum xe_multi_queue_priority priority);

struct xe_lrc_snapshot *xe_lrc_snapshot_capture(struct xe_lrc *lrc);
void xe_lrc_snapshot_capture_delayed(struct xe_lrc_snapshot *snapshot);
void xe_lrc_snapshot_print(struct xe_lrc_snapshot *snapshot, struct drm_printer *p);
void xe_lrc_snapshot_free(struct xe_lrc_snapshot *snapshot);

u32 xe_lrc_ctx_timestamp_ggtt_addr(struct xe_lrc *lrc);
u32 xe_lrc_ctx_timestamp_udw_ggtt_addr(struct xe_lrc *lrc);
u32 xe_lrc_ctx_job_timestamp_ggtt_addr(struct xe_lrc *lrc);
u32 xe_lrc_ctx_job_timestamp(struct xe_lrc *lrc);
int xe_lrc_setup_wa_bb_with_scratch(struct xe_lrc *lrc, struct xe_hw_engine *hwe,
				    u32 *scratch);

/**
 * xe_lrc_update_timestamp - readout LRC timestamp and update cached value
 * @lrc: logical ring context for this exec queue
 * @old_ts: pointer where to save the previous timestamp
 *
 * Read the current timestamp for this LRC and update the cached value. The
 * previous cached value is also returned in @old_ts so the caller can calculate
 * the delta between 2 updates. Note that this is not intended to be called from
 * any place, but just by the paths updating the drm client utilization.
 *
 * Returns the current LRC timestamp
 */
u64 xe_lrc_update_timestamp(struct xe_lrc *lrc, u64 *old_ts);

u64 xe_lrc_timestamp(struct xe_lrc *lrc);

#endif